Abstract: A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to a row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract: A semiconductor memory device includes a first memory die having a first termination resistor for an on-die termination and a second memory die having a second termination resistor for an on-die termination and formed on the first memory die. Each of the first and second memory dies has a center pad type and operates based on a multi-rank structure. When the first memory die is accessed, the second termination resistor is connected to the second memory die, and when the second memory die is accessed, the first termination resistor is connected to the first memory die.

Abstract: An embodiment static random access memory (SRAM) array includes a first SRAM mini array having a first plurality of functional SRAM cells in a first column of the SRAM array. Each of the first plurality of functional SRAM cells share a first bit line (BL). The SRAM array further includes a second SRAM mini array having a second plurality of functional SRAM cells in the first column. Each of the second plurality of functional SRAM cells share a second BL independently controlled from the first BL. The SRAM array further includes and a SRAM dummy array between the first SRAM mini array and the second SRAM mini array. The SRAM dummy array includes a plurality of SRAM array abut dummy cells in the first column. A first endpoint of the first BL and a second endpoint of the second BL are disposed in the SRAM dummy array.

Abstract: Embodiments are directed to a static random access memory (SRAM) device that prevents burn-in of potentially sensitive information. After an SRAM device is fabricated in a semiconductor material, a heating wire is placed in the layers above portions of the SRAM device. By applying current to the heating wire, a certain temperature is reached for a certain amount of time, and the burn-in of the SRAM is prevented. Other embodiments are also presented.

Abstract: An assist driver is coupled to an end of a word line to which a word line driver is not coupled, and couples the other end of the word line to a first power source, in accordance with a voltage of the other end of the word line.

Abstract: There is provided, for example, a write assist circuit for controlling the voltage level of a memory cell power supply line coupled to an SRAM memory cell to be written in the write operation. The write assist circuit reduces the voltage level of the memory cell power supply line to a predetermined voltage level, in response to a write assist enable signal that is enabled in the write operation. At the same time, the write assist circuit controls the reduction speed of the voltage level of the memory cell power supply line, according to the pulse width of a write assist pulse signal. The pulse width of the write assist pulse signal is defined in such a way that the greater the number of rows (or the longer the length of the memory cell power supply line), the greater the pulse width.

Abstract: A circuit for implementing a write operation of a memory is described. The circuit comprises a data line buffer coupled to a data line and an inverted data line for writing data; a plurality of memory elements, each memory element having a first node coupled to the data line and a second node coupled to the inverted data line; and a write assist circuit having a first node coupled to data line and a second node coupled to the inverted data line, wherein the write assist circuit comprises a pair of pull-down transistors comprising first pull-down transistor coupled to the first node of an amplifier portion and a second pull-down transistor coupled to a second node of the amplifier portion, and a pair of pull-up transistors comprising a first pull-up transistor coupled to the first node of the amplifier portion and a second pull-up transistor coupled to the second node of the amplifier portion. A method of implementing a write operation of a memory of a memory is also described.

Abstract: A memory and apparatus are disclosed. The memory includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core. Additionally, the memory includes a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core. The apparatus includes at least one processor. The apparatus also includes a memory array. The memory array includes a memory core having a plurality of memory cells. The memory also includes a first write assist circuit configured to assist writing to a first group of the plurality of memory cells of the memory core and a second write assist circuit configured to assist writing to a second group of the plurality of memory cells of the memory core.

Abstract: A circuit includes: a first data line; a second data line; a write driver including first and second transistors; a first switch connected in series with the first transistor to form a first series-connected pair; a second switch in series with the second transistor to form a second series-connected pair; and a level shifter which includes the first and second transistors. The first series-connected pair is coupled between a first voltage node and the first data line. The second series-connected pair is coupled between the first voltage node and the second data line. Gate terminals of the first and second transistors are correspondingly cross-coupled with the second and first data lines.

Abstract: A variable compensation pass bias based on a state being sensed in non-volatile memory based is provided. Shifts in the apparent charge stored by a memory cell can occur because of coupling based on charge stored by adjacent cells. To account for the shift, compensations can be applied to an adjacent word line when reading based on the different possible conditions of an adjacent cell. The effects of coupling may be more pronounced for memory cells in lower states corresponding to lower threshold voltages. A compensation pass bias can be reduced as the state being sensed at a selected word line increases to account for the different effects. A compensation pass bias for an adjacent word line may be reduced with the application of larger read reference voltages to a selected word line. Other variations to a compensation pass bias are provided.

Abstract: A three-dimensional array especially adapted for memory elements that reversibly change a level of electrical conductance in response to a voltage difference being applied across them. Memory elements are formed across a plurality of planes positioned different distances above a semiconductor substrate. Bit lines to which the memory elements of all planes are connected are oriented vertically from the substrate and through the plurality of planes.

Abstract: A memory device according to one embodiment includes a first interconnection, a second interconnection, a charge storage portion provided between the first interconnection and the second interconnection, a tunnel film provided between the first interconnection and the charge storage portion, and a block film. the charge storage portion is capable of accumulating an electron. The tunnel film includes a fine particulate layer that including conductive fine particulates satisfying the Coulomb blockade condition, a first tunnel insulating layer provided between the first interconnection and the fine particulate layer, and a second tunnel insulating layer provided between the fine particulate layer and the charge storage portion. The block film is provided between the charge storage portion and the second interconnection. The block film has an energy structure in which no concave portion with an energy barrier lower than energy barriers on both sides thereof is present.

Abstract: Some embodiments include apparatus and methods having a memory cell with a first electrode, a second electrode, and a dielectric located between the first and second electrodes. The dielectric may be configured to allow the memory cell to form a conductive path in the dielectric from a portion of a material of the first electrode to represent a first value of information stored in the memory cell. The dielectric may also be configured to allow the memory cell to break the conductive path to represent a second value of information stored in the memory cell.

Abstract: A device includes a cross-point array and an access circuit to access subsets of memory elements respectively corresponding to encoded blocks of data. For each of the subsets of memory elements, a row or a column of the cross-point array that includes a first memory element in the subset and a second memory element in the subset further includes a third memory element that is between the first and second memory elements along the row or column and is in one of the subsets corresponding to another of the encoded blocks.

Abstract: Apparatus, systems, and methods to correct for threshold voltage drift in non-volatile memory devices are disclosed and described. In one example, a compensated demarcation voltage is generated by either a time-based drift compensation scheme or a disturb-based drift compensation scheme, and read and write operations to the non-volatile memory are carried out using the compensated voltage threshold.

Abstract: A memory device can include a plurality of bit lines; plurality of memory elements coupled to the bit lines, each memory element including a memory layer formed between two electrodes, the memory layer being programmable between a plurality of different resistance states by creation and removal of conductive regions therein by application of electric fields; and at least one sense amplifier (SA) configured to compare a first value, corresponding to a resistance state of a first memory element, to a second value, corresponding to a resistance state of a second memory element.

Abstract: A memory device according to an embodiment comprises a data processing circuit that includes: a data write pre-processing circuit that processes input data to generate first intermediate data; a data write processing circuit that sequentially sets a voltage difference between a selected row line and a selected global bit line based on the first intermediate data; a data read processing circuit that detects a current flowing in the selected global bit line or a voltage of the selected global bit line and sequentially generates second intermediate data from a result of that detection; and a data read post-processing circuit that processes the second intermediate data to generate output data, the data write pre-processing circuit and the data read post-processing circuit having a correcting function that corrects a difference that may occur between the input data and the output data.

Abstract: A volatile memory data save subsystem may include a coupling to a shared power source such as a chassis or rack battery, or generator. A data save trigger controller sends a data save command toward coupled volatile memory device(s) such as NVDIMMs and PCIe devices under specified conditions: a programmable amount of time passes without AC power, a voltage level drops below normal but is still sufficient to power the volatile memory device during a data save operation, the trigger controller is notified of an operating system shutdown command, or the trigger controller is notified of an explicit data save command without a system shutdown command. NVDIMMs can avoid reliance on dedicated supercapacitors and dedicated batteries. An NVDIMM may perform an asynchronous DRAM reset in response to the data save command. Voltage step downs may be coordinated among power supplies. After data is saved, power cycles and the system reboots.

Abstract: An example content addressable memory. A bit cell of the memory may include a memristor and a switching transistor that are connected in series between a first data line and a second data line. The bit cell may also include a match-line transistor connected between a match line and a rail. A gate of the match-line transistor may be connected to a common node of the memristor and the switching transistor. The switching transistor may be sized such that its channel resistance when on is between a resistance associated with a low-resistance state of the memristor and a resistance associated with a high-resistance state of the memristor.

Abstract: A non-volatile memory system includes a plurality of NAND strings (or other arrangements) that form a monolithic three dimensional memory structure, bit lines, word lines, and one or more control circuits. Multiple NAND strings of the plurality of NAND strings have different select gates connected to different select lines. The multiple NAND strings are connected to a common bit line. The multiple NAND strings are connected to a common word line via their respective different select gates. The one or more control circuits concurrently program multiple memory cells on the multiple NAND strings.

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Abstract: A method of operating a memory device including a first memory block having a plurality cell strings is provided. Each of the plurality of cell strings includes a string selection transistor connected in series to a first dummy cell, a plurality of normal cells, a second dummy cell and a ground selection transistor. The method includes programming the first dummy cell, and programming the normal cells in at least one of the cell strings after the programming the first dummy cell. The normal cells are selected based on a first program command inputted to the memory device. The programming the first dummy cell is performed at least twice before the normal cells are programmed. A number of times of programming the first dummy cell is different according to a level of a voltage applied to the first dummy cell and a level of a voltage applied to the normal cells.

Abstract: A data writing method for writing data to a flash memory includes writing an initial value to the data storage area, determining whether or not the writing of the initial value is performed normally based on a write flag, writing data to the data storage area when the writing is performed normally, and erasing a block including the data storage area when the writing is not performed normally. An initial value is written to the data storage area before writing data, so that whether or not an error correction code storage area contains the initial value may be confirmed. An erase operation of the block is performed only when the error correction code storage area does not contain the initial value, so that the number of times of erasure of the block may be reduced and the life of the product may be increased.

Abstract: A memory system includes a semiconductor memory device having memory cells arranged in rows and columns, and a controller configured to issue a write command with or without a partial page program command to the semiconductor memory device. The semiconductor memory device, in response to the write command issued without the partial page command, executes a first program operation on a page of memory cells and then a first verify operation on the memory cells of the page using a first verify voltage for all of the memory cells of the page, and in response to the write command issued with the partial page command, executes a second program operation on a subset of the memory cells of the page and then a second verify operation on the memory cells of the subset using one of several different second verify voltages corresponding to the subset.

Abstract: There are provided a high voltage switch circuit and a semiconductor memory device including the same. A high voltage switch circuit may include a switching circuit including a first depletion transistor and a first high voltage transistor, which are coupled in series between an input terminal and an output terminal, and a control signal generator for applying, to the first depletion transistor, a control signal having the same potential level as an input voltage applied to the input terminal, in response to a first enable signal and a second enable signal.

Abstract: A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.

Abstract: A data protection method for a memory storage apparatus is provided. The method includes obtaining a current system time from a host system as a boot time, if the memory storage apparatus is powered on, and a basic input/output system of the host system loads and executes instruction programs in the expansion ROM of the memory storage apparatus for transmitting the current system time to the memory storage apparatus. The method also includes obtaining a shutdown time corresponding to the memory storage apparatus; calculating an off time from the shutdown time to the boot time and performing a refresh operation on physical erasing units of a rewritable non-volatile memory in the memory storage apparatus if the off time is longer than an off time threshold.

Abstract: A semiconductor device includes a plurality of first memory strings each first memory string having a channel with a first length and a plurality of second memory strings each second memory string having a channel with a second length shorter than the first length. A method of operating the semiconductor device includes: performing a first read operation on the first read unit, wherein the first read unit includes the first memory cells sharing the same first word line among first memory cells included in the plurality of the first memory strings; and performing a second read operation on the second read unit, wherein the second read unit includes the second memory cells sharing the same second word line among second memory cells included in the plurality of the second memory strings.

Abstract: Sense circuits in a memory device can be pre-charged to different levels in a sensing process to reduce the amount of time used for sensing. During sensing of first and second memory cells, a control circuit pre-charges first and second sense circuits to first and second voltages, respectively. The first and second sense circuits are associated with the first and second memory cells, respectively. Also, during the sensing, a control gate voltage is applied to the first and second memory cells. The control circuit allows the first and second sense node voltages to discharge in a common discharge period and the cells are sensed using a common trip condition. The first and second memory cells are therefore subject to different concurrent verify tests.

Abstract: Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more programming pulses have been applied to memory cells, a delay between the one or more programming pulses and subsequent program verify pulses may be set based on a chip temperature, the number of the one or more programming pulses that were applied to the memory cells, and/or the programming voltage that was applied to the memory cells during the one or more programming pulses. To mitigate the effects of residual electrons after one or more program verify pulses have been applied to memory cells, a delay between the one or more program verify pulses and subsequent programming pulses may be set based on a chip temperature and/or the programming voltage to be applied to the memory cells during the subsequent programming pulses.

Abstract: A Multi-Time-Programmable-Memory (MTPM) array architecture, whose structure comprising of having Metal-Oxide-Semiconductor Field-Effect-Transistor (MOSFET) memory elements arranged in a set of twin-pairs coupled by wordlines (WLs), bitlines (BLs) and sourcelines (SLs). More specifically, the use of inactive portions of the MTPM array structure as substitutes for conventional BL write driver areas by utilizing a set of twin-pairs acting in parallel. These substituted twin-pair sets will improve programming efficiency (VGS) and retention (VDS) through a lowering Interconnect (IR) drop and VDS drops at the BL write driver.

Abstract: Embodiments of the present disclosure provide a GOA unit and a method for driving the same, a GOA circuit and a display device. The embodiments of the preset disclosure relate in particular to the field of display manufacture. The GOA unit specifically comprises: a first node control module and a second node control module, wherein the first node control module is connected to a first control node, an input signal terminal, a first clock signal terminal, and an output signal terminal, wherein the second node control module is connected to a reset signal terminal, a second clock signal terminal, a third clock signal terminal, a first level terminal, the output terminal, and the first control node. The embodiment of the present disclosure may simplify the structure of a GOA circuit and be used for display manufacture.

Abstract: An input circuit of a memory device includes an input receiver to receive an input signal, a clock receiver to receive a clock signal, a data latch, an input signal delay path coupled to the input receiver and configured to provide a delayed internal input signal to the data latch, a first clock signal delay path coupled to the clock receiver and configured to provide a first delayed internal clock signal, a second clock signal delay path coupled to the input receiver and configured to provide a second delayed internal clock signal, and a multiplexer coupled to receive and select one of the first delayed internal clock signal and the second delayed internal clock signal in response to a test mode control signal, and to provide the selected signal to the data latch.

Abstract: The invention relates to compositions and methods for coating a zirconium alloy cladding of a fuel element for a nuclear water reactor. The coating includes a first tier or layer and a second tier or layer. The first layer includes an elemental metal and the second layer is an oxidation-resistant layer that includes elemental chromium. The first layer serves as an intermediate layer between the zirconium alloy substrate and the second layer. This intermediate layer can be effective to improve adhesion of the second layer to the zirconium alloy substrate. The multilayer coating forms a protective layer which provides improved capability for the zirconium alloy cladding to withstand normal and accident conditions to which it is exposed in the nuclear reactor.

Abstract: Illustrative embodiments provide a nuclear fission reactor, that includes a reactor vessel, a nuclear fission fuel element capable of generating a gaseous fission product, a valve body defining a plenum for receiving the gaseous fission product, and a valve in operative communication with the plenum for controllably venting the gaseous fission product from the plenum.

Abstract: A duct for a nuclear fuel assembly includes a tubular body and an elongated member. The tubular body has a sidewall with an inner face and an outer face and is configured to contain nuclear fuel within a fuel region. The elongated member extends from the outer face along at least a portion of the fuel region and has a contact surface configured to stabilize the duct during operation of the nuclear fuel assembly.

Abstract: A nuclear fission reactor fuel assembly adapted to permit expansion of the nuclear fuel contained therein. The fuel assembly comprises an enclosure having enclosure walls to sealingly enclose a nuclear fuel foam defining a plurality of interconnected open-cell voids or a plurality of closed-cell voids. The voids permit expansion of the foam toward the voids, which expansion may be due to heat generation and/or fission gas release. The voids shrink or reduce in volume as the foam expands. Pressure on the enclosure walls is substantially reduced because the foam expands toward and even into the voids rather than against the enclosure walls. Thus, the voids provide space into which the foam can expand.

Abstract: A method of operating a nuclear reactor is provided. The method includes defining a layer increment of a deposit layer modeling a deposit on a heat transfer surface of the nuclear reactor; periodically updating a thickness of the deposit layer by adding the layer increment to the deposit layer; recalculating properties of the deposit layer after each layer increment is added to the deposit layer; determining a temperature related variable of the heat transfer surface as a function of the recalculated properties of the deposit layer; and altering operation of the nuclear reactor when the temperature related variable of the heat transfer surface reaches a predetermined value. A method of modeling a deposit on a heat transfer surface of a nuclear reactor is also provided.

Abstract: An integral pressurized water reactor (PWR) comprises: a cylindrical pressure vessel including an upper vessel section and a lower vessel section joined by a mid-flange; a cylindrical central riser disposed concentrically inside the cylindrical pressure vessel and including an upper riser section disposed in the upper vessel section and a lower riser section disposed in the lower vessel section; steam generators disposed inside the cylindrical pressure vessel in the upper vessel section; a reactor core comprising fissile material disposed inside the cylindrical pressure vessel in the lower vessel section; and control rod drive mechanism (CRDM) units disposed inside the cylindrical pressure vessel above the reactor core and in the lower vessel section. There is no vertical overlap between the steam generators and the CRDM units.

Abstract: A nuclear reactor control rod drive assembly includes a control rod drive mechanism coupled to a drive shaft and operable to bi-directionally urge the drive shaft through a portion of an inner volume of a reactor vessel at a first force; a control rod manifold coupled to the drive shaft; a plurality of control rods coupled to the control rod manifold, the plurality of control rods adjustable among a plurality of positions within the inner volume of the reactor vessel based on operation of the control rod drive mechanism; and at least one variable strength joint positioned between the control rod drive mechanism and the plurality of control rods.

Abstract: A system for monitoring a condition of a nuclear reactor pressure vessel disposed in a radioactive environment includes an instrument structured to monitor a condition of the nuclear reactor pressure vessel; a powered wireless transmitting modem disposed in the radioactive environment, the wireless transmitting modem being electrically coupled to the instrument; a receiving modem disposed in the line of sight of the transmitting modem, the receiving modem being in wireless communication with the transmitting modem; and a signal processing unit electrically coupled to the receiving modem, the signal processing unit being structured to determine the condition of the nuclear reactor pressure vessel from the instrument. The transmitting modem is powered by a thermocouple disposed in or on the reactor pressure vessel.

Abstract: Methods and systems for detecting an individual leaking fuel channel included in a reactor. One system includes a plurality of inlet lines and a plurality of outlet lines. Each of the plurality of inlet lines feeding annulus fluid in parallel to an annulus space of each of a first plurality of fuel channels included in the reactor, and each of the plurality of outlet lines collecting in parallel annulus fluid exiting an annulus space of each of a second plurality of fuel channels included in the reactor. In some embodiments, the system also includes a detector positioned at an outlet of each of the plurality of outlet lines configured to detect moisture in annulus fluid and identify a first position of an individual leaking fuel channel, and an isolation valve positioned at an inlet of each of the plurality of inlet lines operable to stop annulus fluid from circulating through one of the plurality of inlet lines and to identify a second position of the individual leaking fuel channel.

Abstract: Apparatuses for reducing or eliminating Type 1 LOCAs in a nuclear reactor vessel. A nuclear reactor including a nuclear reactor core comprising a fissile material, a pressure vessel containing the nuclear reactor core immersed in primary coolant disposed in the pressure vessel, and an isolation valve assembly including, an isolation valve vessel having a single open end with a flange, a spool piece having a first flange secured to a wall of the pressure vessel and a second flange secured to the flange of the isolation valve vessel, a fluid flow line passing through the spool piece to conduct fluid flow into or out of the first flange wherein a portion of the fluid flow line is disposed in the isolation valve vessel, and at least one valve disposed in the isolation valve vessel and operatively connected with the fluid flow line.

Abstract: Systems and methods for refueling a nuclear reactor that has a reactor core in a reactor pool having a plurality of elongated reactor core components, a fuel pool for storing core components, and a transfer channel connecting the fuel pool to the reactor pool. The method includes retrieving a replacement core component from the fuel pool, and securing the replacement core component in a first compartment of a handover assembly in a vertical position. The method also includes retrieving a spent core component from the reactor core, and securing the spent core component in a second compartment of the handover assembly in a vertical position. The replacement core component is retrieved from the first compartment and installed into the reactor core. The spent core component is retrieved from the second compartment and stored in a storage rack in the fuel pool.

Abstract: A method of storing a chimney assembly of a reactor pressure vessel during a nuclear reactor outage includes detaching a chimney barrel with upper chimney partitions therein from a top guide assembly of the reactor pressure vessel. A height of the upper chimney partitions is less than a height of the chimney barrel so as to leave a plenum region in a top section of the chimney barrel. The top guide assembly includes lower chimney partitions therein. The lower chimney partitions are removed from the top guide assembly and inserted into the plenum region of the chimney barrel so as to be on the upper chimney partitions. As a result, the chimney assembly can be stored in a relatively compact form during a reactor outage. The chimney assembly includes a combination of at least the chimney barrel, the upper chimney partitions, and the lower chimney partitions.

Abstract: A shipping container containing an unirradiated nuclear fuel assembly is lifted off the ground by operating a crane to raise a lifting tool comprising a winch. The lifting tool is connected with the shipping container by a rigging line connecting with the shipping container at a lifting point located on the shipping container between the top and bottom of the shipping container, and by winch cabling connecting with the shipping container at the top of the shipping container. The shipping container is reoriented by operating the winch to adjust the length of the winch cabling so as to rotate the shipping container about the lifting point. Shortening the winch cabling rotates the shipping container about the lifting point from a horizontal orientation to a vertical orientation, while lengthening the winch cabling rotates the shipping container about the lifting point from the vertical orientation to the horizontal orientation.

Abstract: An object to be decontaminated contaminated with radioactive material, e.g., contaminated soil or water, is introduced into eluting solvent and dissolved, and the radioactive material is separated from the object to be contaminated by elution of the radioactive material into the eluting solvent. The eluting solvent containing the radioactive materials dissolved therein and the object to be decontaminated are separated into solid and liquid. The soil after solid-liquid separation and from which the radioactive material is removed is collected, and the eluting solvent after solid-liquid separation and a separated liquid containing contaminated water are introduced into an electrolysis tank and electrolyzed. Metal ions such as those of the radioactive materials are deposited on the cathode in the electrolysis tank. Hydrogen containing tritium generated in electrolysis is collected in the electrolysis tank. The hydrogen is moved to the outside of the electrolysis tank and trapped.

Abstract: A mobile melting device for consolidating contaminated scrap and to a corresponding method. The melting device has a crucible chamber and a crucible base. The crucible is arranged on the crucible base during operation, and the crucible base and the crucible chamber together form a gas-tight furnace housing. It is thus possible to carry out the method in a vacuum or under protective gas such that even a reactive material can be consolidated. The melting device can be assembled and disassembled with little effort.

Abstract: The present invention provides a method for producing molybdenum-99 comprising: i) providing an electron accelerator; ii) providing a molybdenum converter/target unit (Mo-CTU) comprising one or more metallic components, wherein each one of said metallic components is made of a material selected from the group consisting of natural molybdenum, molybdenum-100, molybdenum-98, and mixtures thereof; iii) directing an electron beam generated via said electron accelerator onto said Mo-CTU to produce a braking radiation (bremsstrahlung); iv) employing said bremsstrahlung onto said Mo-CTU to produce molybdenum-99 and neutrons via a photo-neutron reaction; v) slowing down the neutrons produced in step iv) with a low atomic liquid, e.g. distilled water; and optionally vi) employing the neutrons produced in step iv) to produce a complementary amount of molybdenum-99 via a neutron capture reaction on said Mo-CTU. The invention further provides an apparatus for producing molybdenum-99.