Patents Issued in August 1, 2017
  • Patent number: 9721793
    Abstract: Techniques herein provide precise cuts for fins and nanowires without needing dummy gate pairs to compensate for overlay misalignment. Techniques herein include using an etch mask to remove designated portions of gate structures to define a trench or open space having fin structures, nanowires, etc. The uncovered fin structures are etched away or otherwise removed from the trench segments. The etch mask and material defining the trench provide a combined etch mask for removing uncovered fin portions. Subsequently the trench segments are filled with dielectric material. Without needed dummy gate pairs a given substrate can fit significantly more electrical devices per unit area.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: August 1, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Jeffrey Smith, Anton J. deVilliers
  • Patent number: 9721794
    Abstract: Example embodiments relate to a hardmask composition and/or a method of forming a fine pattern by using the hardmask composition, wherein the hardmask composition includes at least one of a two-dimensional layered nanostructure and a precursor thereof, and a solvent, and an amount of the at least one of a two-dimensional layered nanostructure and the precursor is about 0.01 part to about 40 parts by weight based on 100 parts by weight of the hardmask composition.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeonjin Shin, Sangwon Kim, Seongjun Park
  • Patent number: 9721795
    Abstract: A method of forming patterns includes forming pillars and first peripheral patterns on an underlying layer, forming a separation wall layer covering sidewalls of the pillars and the first peripheral patterns, forming blocking portions on the separation wall layer to fill first openings between the first peripheral patterns, forming a block copolymer layer filling gap regions between the pillars, annealing the block copolymer layer to form first domains and a second domain surrounding the first domains, removing the first domains and removing portions of the separation wall layer to form second openings, removing the second domain and the blocking portions, removing the pillars and the first peripheral patterns to form third openings and fourth openings, and patterning the underlying layer to form fifth openings that extend from the second and third openings and sixth openings that extend from the fourth openings.
    Type: Grant
    Filed: August 3, 2015
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventors: Jong Cheon Park, You Song Kim, Sung Kwang Kim, Jung Hyung Lee
  • Patent number: 9721796
    Abstract: A process is disclosed of forming metal replacement gates for PMOS transistors with oxygen in the metal gates such that the PMOS gates have effective work functions above 4.85. Metal work function layers in the PMOS gates are oxidized at low temperature to increase their effective work functions to the desired PMOS range. Hydrogen may also be incorporated at an interface between the metal gates and underlying gate dielectrics. Materials for the metal work function layers and processes for the low temperature oxidation are disclosed.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: August 1, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, James Joseph Chambers
  • Patent number: 9721797
    Abstract: A semiconductor device and a method for forming the same. The semiconductor device includes a tunnel insulating layer, a charge storage layer including a dopant, and a diffusion barrier layer including at least one of carbon, nitrogen, or oxygen interposed between the tunnel insulating layer and the charge storage layer.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: August 1, 2017
    Assignee: SK Hynix Inc.
    Inventor: Young Ho Yang
  • Patent number: 9721798
    Abstract: Provided is a method and apparatus for depositing an amorphous silicon film. The method includes supplying a source gas and an atmospheric gas onto a substrate in a state where the substrate is loaded in a chamber to deposit the amorphous silicon film on the substrate. The atmospheric gas includes at least one of hydrogen and helium. The source gas includes at least one of silane (SiH2), disilane (Si2H6), and dichlorosilane (SiCl2H2).
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: August 1, 2017
    Assignee: EUGENE TECHNOLOGY CO., LTD.
    Inventors: Seung-Woo Shin, Hai-Won Kim, Woo-Duck Jung, Sung-Kil Cho, Wan-Suk Oh, Ho-Min Choi, Koon-Woo Lee
  • Patent number: 9721799
    Abstract: The present disclosure relates to a semiconductor package and method of making the same. The semiconductor package includes an encapsulation layer, a dielectric layer, a component, and a first patterned conductive layer. The encapsulation layer has a first surface. The component is within the encapsulation layer and has a front surface and a plurality of pads on the front surface. The dielectric layer is on the first surface of the encapsulation layer, and defines a plurality of via holes; wherein the plurality of pads of the component are against the dielectric layer; and wherein the dielectric layer has a second surface opposite the first surface of the encapsulation layer. Each of plurality of via holes extends from the second surface of the dielectric layer to a respective one of the plurality of the pads. The first patterned conductive layer is within the dielectric layer and surrounds the via holes.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: August 1, 2017
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Lin Shih, Chih-Cheng Lee
  • Patent number: 9721800
    Abstract: Disclosed are pre-wetting apparatus designs and methods. These apparatus designs and methods are used to pre-wet a wafer prior to plating a metal on the surface of the wafer. Disclosed compositions of the pre-wetting fluid prevent corrosion of a seed layer on the wafer and also improve the filling rates of features on the wafer.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: August 1, 2017
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, David W. Porter, Mark J. Willey, Robert Rash
  • Patent number: 9721801
    Abstract: A substrate treating method may include jetting a fluid containing an abrasive onto a substrate, and polishing the substrate using the jetted fluid.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hongjin Kim, Kyoungseob Kim, Sungho Shin, Kuntack Lee, Kihong Cho
  • Patent number: 9721802
    Abstract: An apparatus configured to remove metal etch byproducts from the surface of substrates and from the interior of a substrate processing chamber. A plasma is used in combination with a solid state light source, such as an LED, to desorb metal etch byproducts. The desorbed byproducts may then be removed from the chamber.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: August 1, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Subhash Deshmukh, Joseph Johnson
  • Patent number: 9721803
    Abstract: In one embodiment of the present invention, an etching method for a substrate to be processed comprises: (a1) a step in which etchant gas is supplied into a processing container than accommodates a substrate to be processed; (b1) a step in which the inside of the processing container is evacuated; (c1) a step in which a noble gas is supplied into the processing container; and (d1) a step in which microwaves are supplied into the processing container so as to excite the plasma of the noble gas inside the processing container. The sequential process including the step of supplying the etchant of supplying the etchant gas, the evacuating step, the step of supplying the noble gas, and the step of exciting the plasma of the noble gas may be repeated.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: August 1, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Takaba
  • Patent number: 9721804
    Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure on the substrate; performing a first etching process to remove part of the fin-shaped structure for forming a trench; and performing a second etching process to extend the depth of the trench and divide the fin-shaped structure into a first portion and a second portion.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: August 1, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Huang-Ren Wei, Hsuan-Sheng Lin
  • Patent number: 9721805
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming first and second fin structures over a semiconductor substrate. Each of the first and second fin structures has an upper portion and a lower portion. The method also includes forming a phosphosilicate glass (PSG) layer surrounding the upper and lower portions of the first fin structure. The method further includes doping the PSG layer to form a doped PSG layer. In addition, the method includes forming a borosilicate glass (BSG) layer surrounding the upper and lower portions of the second fin structure. The BSG layer extends over the doped PSG layer. The method also includes forming an isolation layer over the BSG layer. The method further includes partially etching the isolation layer, the BSG layer and the doped PSG layer to expose the upper portions of the first and second fin structures.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Hui Lee, Chen-Wei Pan, Yi-Wei Chiu, Tzu-Chan Weng
  • Patent number: 9721806
    Abstract: The disclosed subject matter provides an LDMOS device and fabrication method thereof. In an LDMOS device, a drift region and a body region are formed in a substrate. A first trench is formed in the drift region and in the substrate between the drift region and the body region. The first trench is separated from the drift region by a first shallow trench isolation structure. A gate dielectric layer is formed on a side surface and a bottom surface of the first trench. A gate electrode filling up the first trench is formed on the gate dielectric layer with a top surface above a top surface of the semiconductor substrate. A source region is formed in the body region on one side of the gate electrode and a drain region is formed in the drift region on another side of the gate electrode.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: August 1, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Lei Fang
  • Patent number: 9721807
    Abstract: Embodiments described herein relate to methods for patterning a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment on a spacer material, performing an etching process on a treated region of the spacer material, and repeating the inert plasma treatment and the etching process to form a desired spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as process gas ratios and pressures, may be controlled to influence a desired spacer profile.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: August 1, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Qingjun Zhou, Jungmin Ko, Tom Choi, Sean Kang, Jeremiah Pender, Srinivas D. Nemani, Ying Zhang
  • Patent number: 9721808
    Abstract: Methods of fabricating a semiconductor device are provided. The methods may include forming a stopper layer on a target layer including a cell area and an edge area, forming a hard mask including first upper openings and dam trench on the stopper layer, forming opening spacers on inner walls of the first upper openings and a dam pattern in the dam trench, removing the stopper layer exposed in the first upper openings to form first lower openings, forming pillar patterns in the first lower openings and the first upper openings and an eaves pattern on the dam pattern, removing the hard mask in the cell area, forming a first polymer block between the pillar patterns including second upper openings, etching the stopper layer exposed in the second upper openings to form second lower openings, and removing the first polymer block, the pillar patterns, the dam pattern and the eaves pattern.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dae-Yong Kang, Eunsung Kim, Byungjun Jeon, Joonsoo Park, Soonmok Ha
  • Patent number: 9721809
    Abstract: Disclosed herein is a method of forming a gettering layer for capturing metallic ions on the back side of a semiconductor wafer formed with devices on the face side thereof. The method includes irradiating the back-side surface of the semiconductor wafer with a pulsed laser beam having a pulse width corresponding to a thermal diffusion length of 10 to 230 nm, to thereby form the gettering layer.
    Type: Grant
    Filed: September 17, 2013
    Date of Patent: August 1, 2017
    Assignee: DISCO CORPORATION
    Inventors: Hiroshi Morikazu, Nao Hattori
  • Patent number: 9721810
    Abstract: Methods of doping a semiconductor film are provided. The methods comprise epitaxially growing the III-V semiconductor film in the presence of a dopant, a surfactant capable of acting as an electron reservoir, and hydrogen, under conditions that promote the formation of a III-V semiconductor film doped with the p-type dopant. In some embodiments of the methods, the epitaxial growth of the doped III-V semiconductor film is initiated at a first hydrogen partial pressure which is increased to a second hydrogen partial pressure during the epitaxial growth process.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: August 1, 2017
    Assignee: University of Utah Research Foundation
    Inventors: Feng Liu, Gerald Stringfellow, Junyi Zhu
  • Patent number: 9721811
    Abstract: A semiconductor device for high power application in which a novel semiconductor material having high mass productivity is provided. An oxide semiconductor film is formed, and then, first heat treatment is performed on the exposed oxide semiconductor film in order to reduce impurities such as moisture or hydrogen in the oxide semiconductor film. Next, in order to further reduce impurities such as moisture or hydrogen in the oxide semiconductor film, oxygen is added to the oxide semiconductor film by an ion implantation method, an ion doping method, or the like, and after that, second heat treatment is performed on the exposed oxide semiconductor film.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: August 1, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Junichiro Sakata, Hiroki Ohara
  • Patent number: 9721812
    Abstract: A method for fabricating an optical multi-chip module (MCM) includes temporarily curing an underfill material on a chip including an optical device to prevent flow of the underfill material. The chip is flip-chip mounted on a waveguide module having a mirror for directing light to or from the chip, wherein the underfill material is disposed between the chip and the waveguide module. The underfill material is cured to adhere the chip to the waveguide module.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Akihiro Horibe, Masao Tokunari
  • Patent number: 9721813
    Abstract: The present disclosure provides a cleaning method which enables a cup and a member around the cup to be cleaned thoroughly. In this cleaning method, a cleaning liquid is supplied to a cleaning jig from the upper side of the cleaning jig while rotating the cleaning jig held by a substrate holding unit. The cleaning liquid supplied to the cleaning jig is scattered obliquely upward along an inclined surface of an inclined portion which is provided around the entire circumference of the cleaning jig in the vicinity of the outer circumferential edge of the cleaning jig, thereby cleaning cups.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: August 1, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Nobuhiro Ogata, Hiromi Kiyose, Hidetsugu Yano, Tsukasa Hirayama
  • Patent number: 9721814
    Abstract: In a substrate processing apparatus, an election head from a position above a substrate held by a substrate holding part to an inspection position above a standby pod disposed outside a cup part. At the inspection position, a processing liquid ejected from the ejection head toward the standby pod is irradiated with planar light emitted from a light emitting part. An imaging part acquires an inspection image including bright dots appearing on the processing liquid, and a determination part determines the quality of the ejection operation of the ejection head on the basis of the inspection image. Accordingly, it is possible to eliminate the influence of reflected light from the substrate and droplets, mist, or the like of the processing liquid having collided with the substrate and to accurately determine the quality of the ejection operation of the ejection head.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: August 1, 2017
    Assignee: SCREEN HOLDINGS CO., LTD.
    Inventors: Masanobu Sato, Hiroyuki Yashiki
  • Patent number: 9721815
    Abstract: In a substrate processing apparatus, chemical-solution processing is performed by supplying a chemical solution to the upper surface of a substrate in a state where a top plate is located at a first relative position. Also, cleaning processing is performed by supplying a cleaning liquid to the upper surface of the substrate in a state where the top plate is located at a second relative position closer to the substrate than the first relative position is. Moreover, dry processing is performed on the substrate by rotating the substrate in a state where the top plate is located at a third relative position closer to the substrate than the second relative position is. This allows a chemical atmosphere above the substrate to be efficiently removed during the cleaning processing. Consequently, the occurrence of particles due to the chemical atmosphere above the substrate can be suppressed during the dry processing.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 1, 2017
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Kentaro Tokuri, Hiroaki Takahashi
  • Patent number: 9721816
    Abstract: A decapsulation apparatus has an etch plate, an off-center etch head having an opening, a cover sealing to the etch plate forming an etching chamber, a gasket surrounding the opening, a ram sealed through the cover, a pressure-controlled source of Nitrogen or inert gas continuously purging the etching chamber at a low gas pressure, a f toggle mechanism mounted to a metal plate t, an etchant supply subsystem comprising sources of etchant solutions, an etchant solution pump, supply passages and controls to select etchants and etchant ratios, and a heat exchanger heating or cooling the etchant solution, etchant waste passages f conducting used etchant away. Etchants are mixed in the passages to the reaction region, and turbulence in the reaction region is promoted by impinging etchant solution on the encapsulated device.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 1, 2017
    Assignee: RKD Engineering Corporation
    Inventor: Kirk Alan Martin
  • Patent number: 9721817
    Abstract: Provided are an apparatus for measuring impurities on a wafer and a method of measuring impurities on a wafer. The apparatus includes: a wafer aligning device for aligning a wafer; a loading robot for moving and loading the aligned wafer; a rotation stage for rotating the loaded wafer; a scan robot for holding a natural oxide layer etching solution for the wafer and a metallic impurity recovery solution; and a container for receiving a predetermined etching solution and a recovery solution, wherein the scan robot removes an oxide layer on an edge region of the wafer.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: August 1, 2017
    Assignee: LG Siltron Inc.
    Inventor: Seung Wook Lee
  • Patent number: 9721818
    Abstract: An apparatus for transporting a leadframe sheet during semiconductor die assembly includes a rail having sub-rails defining a machine track and an inner space along which the leadframe sheet is moved. A position detector senses a position of the leadframe sheet as the leadframe sheet moves along the machine track. A controller including a processor is coupled to the position detector for receiving the position of the leadframe sheet. A pressurized gas stopper is positioned within the inner space including a gas distributor having at least one gas inlet for receiving a pressured gas supply and at least one gas outlet for directing a flow of gas toward the leadframe sheet sufficient to stop movement of the leadframe sheet. The controller provides control signals for controlling the flow of gas to provide non-contact stopping of the leadframe sheet at one or more locations along the machine track.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: August 1, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Kane Chen
  • Patent number: 9721819
    Abstract: The invention relates to a method for mounting semiconductor chips provided with bumps as flip chips on substrate locations of a substrate. The method comprises the placing of a flip chip in a cavity arranged in a stationary manner where the bumps are wetted with a fluxing agent and the position of the flip chip is determined by means of a camera. The method further comprises the use of a transport head and a bonding head, which allow rapid and highly precise mounting.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: August 1, 2017
    Assignee: BESI SWITZERLAND AG
    Inventor: Florian Speer
  • Patent number: 9721820
    Abstract: Embodiments of the present invention provide an end effector capable of generating an electrostatic chucking force to chuck a substrate disposed therein without damaging the substrate. In one embodiment, an end effector for a robot, the end effector includes a body having an electrostatic chucking force generating assembly, and a mounting end coupled to the body, the mounting end for coupling the body to the robot.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: August 1, 2017
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Michael S. Cox, Michel Anthony Rosa
  • Patent number: 9721821
    Abstract: In accordance with an embodiment of the invention, there is provided a soft protrusion structure for an electrostatic chuck, which offers a non-abrasive contact surface for wafers, workpieces or other substrates, while also having improved manufacturability and compatibility with grounded surface platen designs. The soft protrusion structure comprises a photo-patternable polymer.
    Type: Grant
    Filed: October 29, 2013
    Date of Patent: August 1, 2017
    Assignee: Entegris, Inc.
    Inventors: I-Kuan Lin, Richard A. Cooke, Jakub Rybczynski
  • Patent number: 9721822
    Abstract: Disclosed is an electrostatic chuck apparatus which is configured of: an electrostatic chuck section; an annular focus ring section provided to surround the electrostatic chuck section; and a cooling base section which cools the electrostatic chuck section and the focus ring section. The focus ring section is provided with an annular focus ring, an annular heat conducting sheet, an annular ceramic ring, a nonmagnetic heater, and an electrode section that supplies power to the heater.
    Type: Grant
    Filed: March 6, 2015
    Date of Patent: August 1, 2017
    Assignees: Tokyo Electron Limited, Sumitomo Osaka Cement Co., Ltd.
    Inventors: Yasuharu Sasaki, Kenji Masuzawa, Toshiyuki Makabe, Mamoru Kosakai, Takashi Satou, Kazunori Ishimura, Ryuuji Hayahara, Hitoshi Kouno
  • Patent number: 9721823
    Abstract: A method of transferring micro-devices is provided. A carrying unit including a carrying substrate, a plurality of electrodes, a dielectric layer covering the electrodes, and a plurality of micro-devices disposed on the electrodes, including a first micro-device and a second micro-device, are also provided. A voltage is applied to an electrode corresponding to the first micro-device, so that an electrostatic force generated on the first micro-device by the carrying unit is larger than a force generated on the second micro-device by the carrying unit. A transfer stamp contacts the first micro-device and the second micro-device, and moves when the transfer stamp contacts the first micro-device and the second micro-device and the electrostatic force is greater than the force generated by the carrying unit, so that the second micro-device is picked up by the transfer stamp and transferred to a receiving unit, and the first micro-device remains on the carrying unit.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: August 1, 2017
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Tsung-Tien Wu, Ho-Cheng Lee, Kang-Hung Liu, Chih-Che Kuo
  • Patent number: 9721824
    Abstract: A bonding structure including a first substrate, a second substrate, and an adhesive layer is provided. The first substrate has a plurality of first trenches. The adhesive layer is located between the first substrate and the second substrate, and the first trenches are filled with the adhesive layer.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 1, 2017
    Assignee: Industrial Technology Research Institute
    Inventors: Kuan-Wei Chen, Pei-Jer Tzeng, Chien-Chou Chen, Po-Chih Chang
  • Patent number: 9721825
    Abstract: Some embodiments include a method. The method can include providing a carrier substrate having an edge. Further, the method can include providing a cross-linking adhesive, and providing a flexible substrate having an edge. Further still, the method can include coupling the flexible substrate to the carrier substrate using the cross-linking adhesive such that at least a portion of the edge of the flexible substrate is recessed from the edge of the carrier substrate and such that the cross-linking adhesive has an exposed portion of the cross-linking adhesive at an offset portion of the first surface of the carrier substrate between the at least the portion of the edge of the flexible substrate and the edge of the carrier substrate. Meanwhile, the method can include etching the exposed portion of the cross-linking adhesive. Other embodiments of related methods and devices are also disclosed.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 1, 2017
    Assignee: ARIZONA BOARD OF REGENTS, A BODY CORPORATE OF THE STATE OF ARIZONA, ACTING FOR AND ON BEHALF OF ARIZONA STATE UNIVERSITY
    Inventors: Michael A. Marrs, Emmett M. Howard, Douglas E. Loy, Nicholas Munizza
  • Patent number: 9721826
    Abstract: A wafer supporting structure in semiconductor manufacturing, and a device and a method for manufacturing semiconductor are provided. In accordance with some embodiments of the instant disclosure, a wafer supporting structure in semiconductor manufacturing includes a transparent ring and at least two arms. The arms are connected to the transparent ring.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Yu Ma, Yii-Chi Lin, Zheng-Yang Pan, Chia-Chiung Lo
  • Patent number: 9721827
    Abstract: One or more semiconductor arrangements are provided. The semiconductor arrangements include a buried layer over a well, a dielectric layer over the buried layer, a first gate stack over the dielectric layer and a S/D region disposed proximate the first gate stack. The S/D region has a first tip proximity region that extends under the first gate stack. One or more methods of forming a semiconductor arrangement are also provided. The methods include forming a S/D recess in at least one of a dielectric layer, a buried layer or a well, wherein the S/D recess is proximate a first gate stack and has a first recess tip proximity region that extends under the first gate stack as a function of the buried layer, and forming a S/D region in the S/D recess such that the S/D region has a first tip proximity region that extends under the first gate stack.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Wei-Fan Lee, Yuan-feng Chao, Yen Chuang
  • Patent number: 9721828
    Abstract: A method of filling STI trenches with dielectric with reduced particle formation. A method of depositing unbiased STI oxide on an integrated circuit during STI trench fill that reduces STI defects during STI CMP.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: August 1, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Andrew Brian Nelson, Richard A. Stice, Joe Tran
  • Patent number: 9721829
    Abstract: An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Li Chiang, Wei-Jen Lai, Feng Yuan, Tsung-Lin Lee, Chih Chieh Yeh
  • Patent number: 9721830
    Abstract: A method of manufacturing a semiconductor device comprising the steps of: forming a trench at an upper portion of a semiconductor substrate forming a preliminary filling insulation layer by coating a siloxane composition on the semiconductor substrate to fill the trench performing a low temperature curing process at a temperature in a range from about 50° C. to about 150° C. such that the preliminary filling insulation layer is transformed into a filling insulation layer including polysiloxane and forming an isolation layer by planarizing the filling insulation layer.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: August 1, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seok-Han Park
  • Patent number: 9721831
    Abstract: A method includes forming a plurality of first semiconductor fins and a plurality of second semiconductor fins in a substrate, depositing a gate electrode layer over the substrate, wherein upper portions of the plurality of first semiconductor fins and the plurality of second semiconductor fins are embedded in the gate electrode layer, depositing a reverse film over the gate electrode layer and applying a chemical mechanical polish process to the reverse film and the gate electrode layer, wherein during the step of applying the chemical mechanical polish process, depositing a slurry between a polishing pad and the reverse film, and wherein a slurry selectivity ratio of the gate electrode layer to the reverse film is greater than 1.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: August 1, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Chin Nien, William Weilun Hong, Ying-Tsung Chen
  • Patent number: 9721832
    Abstract: A method for fabricating silicon-on-insulator (SOI) semiconductor devices, wherein the piezoresistive pattern is defined within a blanket doped layer after fusion bonding. This new method of fabricating SOI semiconductor devices is more suitable for simpler large scale fabrication as it provides the flexibility to select the device pattern/type at the latest stages of fabrication.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 1, 2017
    Assignee: Kulite Semiconductor Products, Inc.
    Inventors: Alexander A. Ned, Sorin Stefanescu, Joseph R. Vandeweert
  • Patent number: 9721833
    Abstract: A semiconductor device with voids within a silicon-on-insulator (SOI) structure and a method of forming the semiconductor device are provided. Voids are formed within a Buried Oxide layer (BOX layer) of the silicon-on-insulator (SOI) semiconductor to enhance a performance index of an RF-SOI switch. The semiconductor device with voids within a silicon-on-insulator (SOI) structure includes a semiconductor substrate; an insulating layer disposed on the substrate; a silicon-on-insulator (SOI) layer disposed on the insulating layer; a device isolation layer and an active area disposed within the SOI layer; one or more voids disposed within the insulating layer; and a sealing insulating sealing an opening of the void.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: August 1, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventor: Francois Hebert
  • Patent number: 9721834
    Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: August 1, 2017
    Assignees: International Business Machines Corporation, Globalfoundries Inc.
    Inventors: Huiming Bu, Andrew M. Greene, Balasubramanian Pranatharthiharan, Ruilong Xie
  • Patent number: 9721835
    Abstract: Recrystallization and grain growth of an interconnect metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 600° C., for example, for short anneal times of five to 180 minutes by forming a metal stress locking layer on the interconnect metal before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the interconnect metal by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing or wet etching leaving the metal interconnect with low stress and improved grain size and texture. Annealing can be done in a forming gas or nitrogen gas atmosphere.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: August 1, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel C. Edelstein, Chih-Chao Yang
  • Patent number: 9721836
    Abstract: A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first conductive feature over the semiconductor substrate. The semiconductor device also includes a first dielectric layer over the semiconductor substrate and surrounding the first conductive feature. The semiconductor device further includes a second conductive feature over the first conductive feature, and the second conductive feature extends into the first conductive feature. In addition, the semiconductor device includes a second dielectric layer over the first dielectric layer and surrounding the second conductive feature. The semiconductor device also includes an etch stop layer between the first dielectric layer and the second dielectric layer. The etch stop layer surrounds the first conductive feature, and a bottom surface of the second conductive feature is above the etch stop layer.
    Type: Grant
    Filed: June 2, 2016
    Date of Patent: August 1, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tai-Yen Peng, Chia-Tien Wu, Jye-Yen Cheng
  • Patent number: 9721837
    Abstract: A method for wafer level fabricating a plurality of optoelectronic devices, starting with a wafer that includes a plurality of light detector sensor regions, includes attaching each of a plurality of light source dies to one of a plurality of bond pads on a top surface of the wafer that includes the plurality of light detector sensor regions. The method also includes attaching, to the wafer, a preformed opaque structure made off-wafer from an opaque material, wherein the preformed opaque structure includes opaque vertical optical barriers. Additionally, solder balls or other electrical connectors are attached to the bottom of the wafer. The wafer is diced to separate the wafer into a plurality of optoelectronic devices, each of which includes at least one of the light detector sensor regions, at least one of the light source dies and at least two of the solder balls or other electrical connectors.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: August 1, 2017
    Assignee: INTERSIL AMERICAS LLC
    Inventor: Sri Ganesh A Tharumalingam
  • Patent number: 9721838
    Abstract: A production method for a semiconductor element (10) includes: a semiconductor element forming step of forming the semiconductor element (10) including a dielectric film (3); a dicing region forming step of forming dicing regions (11) by removing the dielectric film (3) in partition regions that partition the semiconductor element (10); and a dicing step of dicing the dicing regions (11).
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: August 1, 2017
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Fumiaki Matsuura, Tomotoshi Satoh
  • Patent number: 9721839
    Abstract: Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a water soluble mask above the semiconductor wafer, the water soluble mask covering and protecting the integrated circuits. The method also includes baking the water soluble mask to increase the etch resistance of the water soluble mask. The method also includes, subsequent to baking the water soluble mask, patterning the water soluble mask with a laser scribing process to provide a water soluble patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The method also includes plasma etching the semiconductor wafer through the gaps in the water soluble patterned mask to singulate the integrated circuits.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: August 1, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Wei-Sheng Lei, Mohammad Kamruzzaman Chowdhury, Brad Eaton, Ajay Kumar
  • Patent number: 9721840
    Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: August 1, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chien-Ming Lai, Chien-Chung Huang, Yu-Ting Tseng, Ya-Huei Tsai, Yu-Ping Wang
  • Patent number: 9721841
    Abstract: An electronic circuit includes a plurality of fin lines on a substrate and a plurality of gate lines with a first line width, crossing over the fin lines. The gate lines are parallel and have a plurality of discontinuous regions forming as a plurality of slots. A region of any one of the gate lines adjacent to an unbalance of the slots has a second line width smaller than the first line width.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: August 1, 2017
    Assignee: United Microelectronics Corp.
    Inventors: Jun-Jie Wang, Yu-Lin Wang, Ching-Wen Hung, En-Chiuan Liou, Chih-Sen Huang
  • Patent number: 9721842
    Abstract: A method of fabricating advanced node field effect transistors using a replacement metal gate process. The method includes dopant a high-k dielectric directly or indirectly by using layers composed of multi-layer thin film stacks, or in other embodiments, by a single blocking layer. By taking advantage of unexpected etch selectivity of the multi-layer stack or the controlled etch process of a single layer stack, etch damage to the high-k may be avoided and work function metal thicknesses can be tightly controlled which in turn allows field effect transistors with low Tinv (inverse of gate capacitance) mismatch.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: August 1, 2017
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Hemanth Jagannathan, Balaji Kannan, Siddarth A. Krishnan, Unoh Kwon, Rekha Rajaram