Abstract: A data processing system and methods for performing cache eviction are disclosed. An exemplary method includes maintaining a metadata set for each cache unit of a cache device, wherein the cache device comprises a plurality of cache units, each cache unit having a plurality of segments, wherein each metadata set includes deletion hints (DH) metadata indicating whether the plurality of segments of a corresponding cache unit are valid. The exemplary method further includes in response to determining that a cache eviction is to be performed, selecting a predetermined number of cache units from the plurality of cache units, and determining a score for each of the selected cache units based on the DH metadata of the respective metadata set. The DH metadata may include, for example, a validation count for each segment group or cache unit. A deprecated segment can be changed back to being valid, and the score for each of the selected cache units may further be determined based on a determined probability.

Abstract: A grace period detection technique for a preemptible read-copy update (RCU) implementation that uses a combining tree for quiescent state tracking. When a leaf level bitmask indicating online/offline CPUs is fully cleared due to all of its assigned CPUs going offline as a result of hotplugging operations, the bitmask state is not immediately propagated to the root level of the combining tree as in prior art RCU implementations. Instead, propagation is deferred until all tasks are removed from an associated leaf level task list tracking tasks that were preempted inside an RCU read-side critical section. Deferring bitmask propagation obviates the need to migrate the task list to the combining tree root level in order to prevent premature grace period termination. The task list can remain at the leaf level. In this way, CPU hotplugging is accommodated while avoiding excessive degradation of real-time latency stemming from the now-eliminated task list migration.

Abstract: A computer allows non-cacheable loads or stores in a hardware transactional memory environment. Transactional loads or stores, by a processor, are monitored in a cache for TX conflicts. The processor accepts a request to execute a transactional execution (TX) transaction. Based on processor execution of a cacheable load or store instruction for loading or storing first memory data of the transaction, the computer can perform a cache miss operation on the cache. Based on processor execution of a non-cacheable load instruction for loading second memory data of the transaction, the computer can not-perform the cache miss operation on the cache based on a cache line associated with the second memory data being not-cached, and load an address of the second memory data into a non-cache-monitor. The TX transaction can be aborted based on the non-cache monitor detecting a memory conflict from another processor.

Abstract: A shared memory controller receives a flit from another first shared memory controller over a shared memory link, where the flit includes a node identifier (ID) field and an address of a particular line of the shared memory. The node ID field identifies that the first shared memory controller corresponds to a source of the flit. Further, a second shared memory controller is determined from at least the address field of the flit, where the second shared memory controller is connected to a memory element corresponding to the particular line. The flit is forwarded to the second shared memory controller using a shared memory link according to a routing path.

Abstract: Systems and methods for supporting a plurality of load and store accesses of a cache are disclosed. Responsive to a request of a plurality of requests to access a block of a plurality of blocks of a load cache, the block of the load cache and a logically and physically paired block of a store coalescing cache are accessed in parallel. The data that is accessed from the block of the load cache is overwritten by the data that is accessed from the block of the store coalescing cache by merging on a per byte basis. Access is provided to the merged data.

Abstract: Methods and systems that identify and power up ways for future instructions are provided. A processor includes an n-way set associative cache and an instruction fetch unit. The n-way set associative cache is configured to store instructions. The instruction fetch unit is in communication with the n-way set associative cache and is configured to power up a first way, where a first indication is associated with an instruction and indicates the way where a future instruction is located and where the future instruction is two or more instructions ahead of the current instruction.

Abstract: A computing element, system, and method for implementing control structures for a compressed cache in hardware. Embodiments provide a first engine configured to allocate and deallocate virtual memory pages and physical memory pages from pools of available pages to store received data to the compressed cache, a second engine configured to compress received data and store the compressed data. Embodiments also provide for embedding data within the virtual and physical memory pages to indicate page size, type, and data compression.

Abstract: A device driver calculates a tile size for a plurality of cache memories in a cache hierarchy. The device driver calculates a storage capacity of a first cache memory. The device driver calculates a first tile size based on the storage capacity of the first cache memory and one or more additional characteristics. The device driver calculates a storage capacity of a second cache memory. The device driver calculates a second tile size based on the storage capacity of the second cache memory and one or more additional characteristics, where the second tile size is different than the first tile size. The device driver transmits the second tile size to a second coalescing binning unit. One advantage of the disclosed techniques is that data locality and cache memory hit rates are improved where tile size is optimized for each cache level in the cache hierarchy.

Abstract: A processor of an aspect includes operation mode check logic to determine whether to allow an attempted access to an operation mode and access type protected memory based on an operation mode that is to indicate whether the attempted access is by an on-die processor logic. Access type check logic is to determine whether to allow the attempted access to the operation mode and access type protected memory based on an access type of the attempted access to the operation mode and access type protected memory. Protection logic is coupled with the operation mode check logic and is coupled with the access type check logic. The protection logic is to deny the attempted access to the operation mode and access type protected memory if at least one of the operation mode check logic and the access type check logic determines not to allow the attempted access.

Abstract: A computer program product for processing input/output (I/O) data is provided for performing a method that includes receiving a transport control word (TCW) including an indirect data address including a starting location of a transport mode indirect data address list (TIDAL) of storage addresses, the TIDAL including a plurality of entries configured as transport mode indirect data address words (TIDAWs). The method includes accessing an entry of the TIDAL, which includes: 1) based on the entry of the TIDAL indicating that the address is a data address, gathering data from a data storage location corresponding to the data address, and accessing a next entry of the TIDAL, and 2) based on the entry of the TIDAL indicating that the address is an address of a next entry of the TIDAL, obtaining the next entry of the TIDAL from another storage location that is located non-contiguously to the entry storage location.

Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: A hypervisor detects a page fault associated with the request for a device assigned to a guest operating system to perform direct memory access (DMA) of a requested page of memory, invalidates a mapping in a central processing unit (CPU) page table of a guest physical address to a host physical address for a candidate page for being swapped out of host memory, checks a DMA access state of the candidate page to determine whether or not the candidate page can be swapped out from the host memory, and removes the candidate page from the host memory in response to determining that the DMA access state indicates that the candidate page can be swapped out.

Abstract: A method and apparatus for calculating a victim way that is always the least recently used way. More specifically, in an m-set, n-way set associative cache, each way in a cache set comprises a valid bit that indicates that the way contains valid data. The valid bit is set when a way is written and cleared upon being invalidated, e.g., via a snoop address, The cache system comprises a cache LRU circuit which comprises an LRU logic unit associated with each cache set. The LRU logic unit comprises a FIFO of n-depth (in certain embodiments, the depth corresponds to the number of ways in the cache) and m-width. The FIFO performs push, pop and collapse functions. Each entry in the FIFO contains the encoded way number that was last accessed.

Abstract: Key information that is currently in use is archived in a management server to prevent the key information from being lost. A storage device 10 is communicatably connected to a management server 60 managing key information 1. The storage device includes a memory device 21, and a controller 100 controlling the memory device. The controller implements encryption processing on data inputted and outputted to and from the memory device by using the key information. When stoppage of an operation is indicated, the controller determines whether the key information used by the controller is managed by the management server, stops the operation in a case where the key information is managed by the management server, and does not stop the operation in a case where the key information is determined not to be managed by the management server.

Abstract: Data storage systems are disclosed for automatically generating encryption rules based on a set of training files that are known to include sensitive information. The system may use a number of heuristic algorithms to generate one or more encryption rules for determining whether a file includes sensitive information. Further, the system may apply the heuristic algorithms to the content of the files, as determined by using natural language processing algorithms, to generate the encryption rules. Moreover, systems are disclosed that are capable of automatically determining whether to encrypt a file based on the generated encryption rules. The content of the file may be determined using natural language processing algorithms and then the encryption rules may be applied to the content of the file to determine whether to encrypt the file.

Abstract: A method of accessing data in a multiprocessor system, wherein the system includes a plurality of processors, with each processor being associated with a respective cache memory, a cache memory management module, a main memory and a main memory management module, the method including: receiving by the cache memory management module an initial request for access to data by a processor; first transmitting by the cache memory management module a first request with respect to the data to at least one cache memory; second transmitting in parallel to the first transmitting by the cache memory management module, a second request with respect to the data to the main memory management module; checking by the main memory management module, whether to initiate querying of the main memory or not, and querying or not by the main memory management module, of the main memory in accordance with the said checking.

Abstract: A method and apparatus for managing access to a memory of a computing system. A controller transforms a plurality of operations that represent a computing job into an operational memory layout that reduces a size of a selected portion of the memory that needs to be accessed to perform the computing job. The controller stores the operational memory layout in a plurality of memory cells within the selected portion of the memory. The controller controls a sequence by which a processor in the computing system accesses the memory to perform the computing job using the operational memory layout. The operational memory layout reduces an amount of energy consumed by the processor to perform the computing job.

Abstract: A method, data storage device and computer program product for efficiently configuring different types of hardware components. A Universal Serial Bus (USB) key is preloaded with multiple profiles, where each profile contains a configuration file(s) associated with a particular type of hardware component. Upon plugging the USB key into a hardware component, the USB key recognizes the type of hardware component based on the properties of the hardware component available on the USB interface. The USB key identifies a profile containing the configuration file(s) associated with the recognized type of hardware component. The USB key then presents the configuration file(s) contained in the identified profile to the connected hardware component. Such a process may be repeated for configuring another type of hardware component. In this manner, the user is able to efficiently configure different types of hardware by having the USB key function as multiple USB keys.

Abstract: A method, data storage device and computer program product for efficiently configuring different types of hardware components. A Universal Serial Bus (USB) key is preloaded with multiple profiles, where each profile contains a configuration file(s) associated with a particular type of hardware component. Upon plugging the USB key into a hardware component, the USB key recognizes the type of hardware component based on the properties of the hardware component available on the USB interface. The USB key identifies a profile containing the configuration file(s) associated with the recognized type of hardware component. The USB key then presents the configuration file(s) contained in the identified profile to the connected hardware component. Such a process may be repeated for configuring another type of hardware component. In this manner, the user is able to efficiently configure different types of hardware by having the USB key function as multiple USB keys.

Abstract: Aspects of the disclosure enable location of a wireless peripheral by a computing device even when the wireless peripheral is beyond a communication range of, or otherwise inaccessible by, the computing device. A user gives a command to a first computing device to determine the location of the wireless peripheral. The first computing device requests other networked computing devices to locate the wireless peripheral. At least one of the other networked computing devices establishes communication with the wireless peripheral, obtains location information for the wireless peripheral, and communicates the location information to the first computing device. The first computing device communicates the location of the wireless peripheral to the user.

Abstract: An embodiment includes a system, comprising: a device configured to present a logical device and enable a virtual device in response to a control signal; and a processor coupled to the device and configured to: present the logical device through a first device interface; transmit the control signal to the device to enable the virtual device; and after the virtual device is enabled, present the virtual device through a second device interface.

Abstract: A content sharing device may receive, from a content providing device, information that identifies content to be shared with a dongle device via a content sharing service. The content sharing device may receive, from the content providing device, information that identifies a contact with which the content is to be shared. The content sharing device may determine, based on the information that identifies the contact, a dongle device identifier. The dongle device identifier may include a network address associated with the dongle device. The content sharing device may provide, to the dongle device and based on determining the dongle device identifier, information that identifies the content. The information that identifies the content may cause the content to be accessible by a content receiving device connected to the dongle device.

Abstract: In a distributed I/O control system updating data through a network between a shared memory of a slave station performing input/output of data with plural input or output devices and a shared memory of the master station corresponding to the slave station's shared memory, the master station sets group information with respect to the input or output devices, and outputs, according to a cycle table, an input request frame specifying the shared memory in the slave station and the group information, and the slave station performs input/output of data with plural input or output devices, and determines whether an input request content specified by an input request frame from the master station is all information in the shared memory in the slave station, or information corresponding to the group information, to thereby transmit output data according to the input request content.

Abstract: A texture processing pipeline can be configured to service memory access requests that represent texture data access operations or generic data access operations. When the texture processing pipeline receives a memory access request that represents a texture data access operation, the texture processing pipeline may retrieve texture data based on texture coordinates. When the memory access request represents a generic data access operation, the texture pipeline extracts a virtual address from the memory access request and then retrieves data based on the virtual address. The texture processing pipeline is also configured to cache generic data retrieved on behalf of a group of threads and to then invalidate that generic data when the group of threads exits.

Abstract: A system, method and computer program product are provided for conditionally eliminating a memory read request. In use, a memory read request is identified. Additionally, it is determined whether the memory read request is an unnecessary memory read request. Further, the memory read request is conditionally eliminated, based on the determination.

Abstract: A solid state drive (SSD) storage system includes a memory controller, host interface, memory channels and solid state memories as storage elements. The completion status of sub-commands of individual read commands is monitored and used to determine an optimal selection for returning data for individual read commands. The completion of a read command may be dependent on the completion of multiple individual memory accesses at various times. The queueing of multiple read commands which may proceed in parallel or out of order causes interleaving of multiple memory accesses from different commands to individual memories. A system and method is disclosed which enables the selection, firstly of completed read commands, independent of the order they were queued and, secondly, of partially completed read commands which are most likely to complete with the least interruption or delay, for data transfer, which in turn improves the efficiency of the data transfer interface.

Abstract: Methods and apparatus for control access to memory in dual-processor. In particular, there are disclosed methods and apparatus for use where a single memory is shared for instructions for the processors and a data store to reduce conflicts between access requirements.

Abstract: Migrating interrupts from a source I/O adapter of a computing system to a destination I/O adapter of the computing system, includes: collecting, by a hypervisor of the computing system, interrupt mapping information, where the hypervisor supports operation of a logical partition executing and the logical partition is configured to receive interrupts from the source I/O adapter; configuring, by the hypervisor, the destination I/O adapter with the interrupt mapping information collected by the hypervisor; placing, by the hypervisor, the destination I/O adapter and the source I/O in an error state; deconfiguring the source I/O adapter from the logical partition; and enabling the logical partition and destination I/O adapter to recover from the error state.

Abstract: Migrating memory MMIO from a source I/O adapter of a source computing system to a destination I/O adapter of a destination computing system, includes: collecting, by a source hypervisor of the source computing system, MMIO mapping information, where the source hypervisor supports a logical partition on the source computing system and the logical partition is configured for MMIO operations with the source I/O adapter through an MMU; placing, by a destination hypervisor of the destination computing system, the destination I/O adapter in an error state; migrating the logical partition from the source computing system to the destination computing system; configuring, by the destination hypervisor of the destination computing system, the destination computing system for MMIO with the LPAR utilizing the MMIO mapping information collected by the source hypervisor; and restarting the logical partition on the destination computing system, including recovering, by the logical partition, from the error state.

Abstract: A flexible server system includes an embedded processor, one or more processor boards, one or more storage boards, and a switch including a plurality of ports. The embedded processor, the one or more processor boards, and the one or more storage boards are connected to a corresponding one of the plurality of ports. The embedded processor, the one or more processor boards, the one or more storage boards, and the switch each include a peripheral component interconnect express (PCIe) interface. The one or more processor boards and the one or more storage boards are connected to the switch through connectors where each of the corresponding connectors have a same size. The embedded processor controls the switch to route a packet from one of the plurality of ports to another one of the plurality of ports.

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

Abstract: According to one embodiment, a first module is responsible for protocol control in compliance with a first interface standard. A second module is provided separately from the first module and is responsible for protocol control in compliance with a second interface standard. A third module is responsible for a physical layer shared between the first interface standard and the second interface standard.

Abstract: Embodiments of a multi-processor array are disclosed that may include a plurality of processors and configurable communication elements coupled together in a interspersed arrangement. Each configurable communication element may include a local memory and a plurality of routing engines. The local memory may be coupled to a subset of the plurality of processors. Each routing engine may be configured to receive one or more messages from a plurality of sources, assign each received message to a given destination of a plurality of destinations dependent upon configuration information, and forward each message to assigned destination. The plurality of destinations may include the local memory, and routing engines included in a subset of the plurality of configurable communication elements.

Abstract: Approaches for bridging communication between first and second buses are disclosed. Address translation information and associated security indicators are stored in a memory. Each access request from the first bus includes a first requester security indicator and a requested address. Each access request from the first bus and directed to the second bus is either rejected, or translated and communicated to the second bus, based on the requester security indicator and the security indicator associated with the address translation information for the requested address. Each access request from the second bus to the first bus includes the requested address, and the access request is translated and communicated to the first bus along with the security indicator that is associated with the address translation information for the requested address.

Abstract: Various embodiments herein each include at least one of devices, methods, and software for coupled device deployment location classification in an automated manner. One embodiment, in the form of a method, includes searching a device tree of a computing device to identify any devices of interest. This method, for each identified device of interest, may then identify a path within the computing device of the device of interest and classify, based on the identified path, a relative location of the device of interest. This method may then store the classification of the device of interest in a memory device of the computing device.

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Abstract: A method for determining cable connections identifies a plurality of cables connected to a link included in a first device. The method identifies a first cable connected to the link included in the first device. The method determines that a second cable connected to is connected to a link included in a second device The method further determines that only one of an inbound and an outbound channel of a signaling lane included in the first cable is operable. The method utilizes a second cable to perform one of disabling signal transmission or detecting loss of signal on the operable channel. The method enables and disables signal transmission on the operable channel to determine that the first cable is connected to the link included in the remote device.

Abstract: A device includes a memory, at least two input/output (IO) pins, and slave identifier (ID) selection circuitry. The memory stores a slave ID, which identifies the device to other devices in a serial communication process. The slave ID selection circuitry changes the stored slave ID based on which one of the IO pins is coupled to a supply voltage. By changing the slave ID of the device based on which one of the IO pins is coupled to a supply voltage, a number of devices with otherwise identical slave IDs may change their slave IDs in order to participate in a serial communication process on the same bus. Further, the slave ID of the device may be changed without using an additional IO pin on the device.

Abstract: A method for a deterministic selection of a sensor from a plurality of sensors, having a control unit and multiple sensors connected to the control unit by means of a three-wire bus, wherein the sensors are connected to the three-wire bus through at least two lines in parallel to one another, and a protocol frame in conformity with the SENT specification is used between the control unit and the sensors for a data exchange, and a particular sensor is selected within the protocol frame by the control unit through the predefined duration of a selection signal, wherein the duration of the selection signal is determined by the interval between a first falling signal edge and a second falling signal edge.

Abstract: A method of operating a microphone system includes the steps of monitoring an I/O terminal to detect whether a signal on that terminal achieves a pre-defined logic level during a monitoring period. The I/O terminal and a second I/O terminal are configured to one of a hardware mode or a communications-bus mode depending on whether the pre-defined logic level is detected. A microphone system includes two I/O terminals and an automatic detection and mode switching circuit, as well as a communications bus interface circuit and a hardware control circuit. The mode automatic detection and mode switching circuit couples the two I/O terminals to either the communications bus interface circuit or the hardware control circuit in response to the logic level detected on one of the I/O terminals during a monitoring period.

Abstract: A receiver includes a phase click detector, a controller, and a comparator. The phase click detector detects phase clicks in an input signal, where a phase click corresponds to a change in phase of at least a first threshold. The controller is coupled to the phase click detector for calculating a number of phase clicks within one or more time periods. The comparator compares the number of phase clicks within the one or more time periods, and provides an arrival signal if the number of phase clicks is less than a second threshold.

Abstract: A serial communication circuit includes a receiving unit configured to serially receive input data including a command and a synchronization identification code that is different from the command and a determining unit configured to receive the synchronization identification code from the receiving unit and when the synchronization identification code coincides with a slave selection value, to instruct a start of response processing based on the command.

Abstract: An electronic device includes: a memory; and a processor. The processor causes a display section to display variables and variable values stored in the memory in a list form, causes the display section to display a first variable specified by a user operation as a first part of an expression, causes the display section to display the variables and the variable values after the first variable is displayed, causes the display section to display a second variable specified by a user operation as a second part of the expression, together with the first part, and calculates the expression based on the first part and the second part by referring to a variable value of the first variable and a variable value of the second variable to obtain a calculation result.

Abstract: A reconfigurable circuit includes a plurality of processing elements and an input/output data interface unit, and the reconfigurable circuit is configured to control connections of the plurality of processing elements for each context. The input/output data interface unit is configured to hold operation input data which is input to the plurality of processing elements and operation output data which is output from the plurality of processing elements. The input/output data interface unit includes a plurality of ports, and a plurality of registers. The registers are configured to be connected to the plurality of ports, and to include m (m being an integer of 2 or more) number of banks in a depth direction.

Abstract: Embodiments are provided for an asynchronous processor using master and assisted tokens. In an embodiment, an apparatus for an asynchronous processor comprises a memory to cache a plurality of instructions, a feedback engine to decode the instructions from the memory, and a plurality of XUs coupled to the feedback engine and arranged in a token ring architecture. Each one of the XUs is configured to receive an instruction of the instructions form the feedback engine, and receive a master token associated with a resource and further receive an assisted token for the master token. Upon determining that the assisted token and the master token are received in an abnormal order, the XU is configured to detect an operation status for the instruction in association with the assisted token, and upon determining a needed action in accordance with the operation status and the assisted token, perform the needed action.

Abstract: A new class of polyhedron is constructed by decorating each of the triangular facets of an icosahedron with the T vertices and connecting edges of a “Goldberg triangle.” A unique set of internal angles in each planar face of each new polyhedron is then obtained, for example by solving a system of n equations and n variables, where the equations set the dihedral angle discrepancy about different types of edge to zero, where the independent variables are a subset of the internal angles in 6 gons. Alternatively, an iterative method that solves for angles within each hexagonal ring may be solved for that nulls dihedral angle discrepancy throughout the polyhedron. The 6 gon faces in the resulting “Goldberg polyhedra” are equilateral and planar, but not equiangular, and nearly spherical.

Abstract: Generating notifications comprising text and image data for client devices with limited display screens is disclosed. An image to be included in the notification is resized and reshaped using image processing techniques. The resized image is further analyzed to identify optimal portions for placing the text data. The text data can also be analyzed and shortened for including at the identified portion of resized image to generate a notification. The resulting notification displays the text and image data optimally within the limited screen space of the client device so that a user observing the notification can obtain the information at a glance.

Abstract: A system and method for providing the dynamic display of content and related advertisements are provided. The advertisements are displayed based on predetermined customer types. A network resource, such as Web page, can include a plurality of dynamic content modules. Depending on the available display area and additional display criteria, each dynamic content module displays a subset content and related advertisements. Each dynamic content module corresponds to an integration of multiple layers of content, such as text, graphics, and image rendering information.

Abstract: A system and method for automatically generating a narrative story receives data and information pertaining to a domain event. The received data and information and/or one or more derived features are then used to identify a plurality of angles for the narrative story. The plurality of angles is then filtered, for example through use of parameters that specify a focus for the narrative story, length of the narrative story, etc. Points associated with the filtered plurality of angles are then assembled and the narrative story is rendered using the filtered plurality of angles and the assembled points.

Abstract: Provided are printers and other electronic devices, systems, methods, and computer program products that automatically detect and determine UTF-16 encoding schemes and endiannesss thereof in an incoming XML data steam for XML declarations without a UTF-16 byte-order mark (BOM) or encoding declaration. This allows for the automatic and unambiguous accurate detection of UTF-16 encoded XML data within a mixed encoding environment, such as from multiple sources using more than one encoding scheme, even when XML data does not start with a BOM or encoding declaration.