Abstract: A Cu—Ga sputtering target made of a composition containing: as metal components excluding fluorine, 5 atomic % or more and 60 atomic % or less of Ga and 0.01 atomic % or more and 5 atomic % or less of K; and the Cu balance containing inevitable impurities is provided. In the Cu—Ga sputtering target, the Cu—Ga sputtering target has a region containing Cu, Ga, K, and F, in an atomic mapping image by a wavelength separation X-ray detector.

Abstract: A Co sputtering target having a purity of 99.99% to 99.999% and a Si content of 1 wtppm or less. Provided is a Co sputtering target capable of improving barrier properties and adhesiveness by suppressing conversion into highly reactive silicide by a reduction in the Si content in cobalt.

Abstract: This invention relates to graphical user-interactive displays for use in MS-based analysis of protein impurities, as well as methods and software for generating and using such. One aspect provides a user-interactive display comprising an extracted mass chromatogram (XIC), an MS1 spectrum and an MS2 spectrum, all simultaneously representing a user-selected peptide. Another aspect provides a user interactive display simultaneously presenting paired spectra (XIC, MS1 and/or MS2) for a variant peptide and its corresponding wildtype counterpart.

Abstract: An ion optical apparatus and a mass spectrometer are provided. The ion optical apparatus includes at least one planar insulating substrate which is covered with metal patterns to form an electrode array including a plurality of cell electrodes, wherein each of the cell electrodes is arrayed according to a first direction to form a geometric pattern distribution of the electrode array, wherein cell electrodes are applied with radio frequency (RF) voltages having different phases to confine ions, a direct current (DC) voltage gradient is applied along at least part of the cell electrodes in the electrode array to drive ions to move in the first direction along the electrode array, and a corresponding electric field distribution is formed by the geometric pattern distribution to drive ions to move in a second direction substantially orthogonal to the first direction, thereby realizing ion deflection, focusing or defocusing.

Abstract: Before a sample is pierced with a probe of a PESI ion source, a total ion current is measured under a condition with no voltage applied from a high voltage generator to the probe as well as under a condition with the voltage applied. If the probe is properly attached to the holder, a considerable difference in total ion current occurs between the period with no voltage applied and the period with the voltage applied. By comparison, if the probe is improperly attached, no significant difference in the total ion current occurs between the period with no voltage applied and the period with the voltage applied. Referring to a threshold determined under the normal condition, a probe attachment checker detects an insufficient attachment of the probe by checking the difference in the total ion current, and displays an error message on a display unit if an improper attachment is detected.

Abstract: There is provided a mass spectrometer comprising a time of flight mass analyser comprising an acceleration electrode, a time of flight region and an ion detector, and a control system arranged and adapted (i) to apply a plurality of extraction pulses to said acceleration electrode in order to accelerate consecutive groups of ions into said time of flight region, wherein ions having a relatively high mass to charge ratio in a preceding group of ions arrive at said detector after ions having a relatively low mass to charge ratio in a subsequent group of ions, wherein ions within each consecutive group of ions have a mass to charge ratio within one or more predetermined, selected or otherwise known mass to charge ratio ranges, and (ii) to determine a frequency or period of said plurality of extraction pulses that will avoid coincidence of ions from said consecutive groups of ions at said ion detector, wherein said plurality of extraction pulses are applied at said determined frequency or period.

Abstract: An ion transport optical system is disposed between a collision cell and an orthogonal acceleration unit. When releasing ions that are held in the collision cell, an accelerating electric field in which a large potential difference exists is created between an exit-side end of an ion guide and a first stage of the ion transport optical system, and a decelerating electric field in which a relatively small potential difference exists is created between a final stage of the ion transport optical system and an entrance end of the orthogonal acceleration unit. In the accelerating electric field, the velocity of ions is increased overall by imparting a large amount of energy to the ions, and spreading of ions in the ion travel direction that is caused by differences between the mass-to-charge ratios of the ions is reduced.

Abstract: Embodiments of the present disclosure generally relate to methods for forming a high-k gate dielectric in a transistor. The high-k gate dielectric may be formed by introducing a fluorine containing gas into a processing chamber during the deposition of the high-k gate dielectric in the processing chamber. In one embodiment, the high-k gate dielectric is formed by an ALD process in a processing chamber, and a fluorine containing gas is introduced into the processing chamber during one or more stages of the ALD process. Fluorine ions, molecules or radicals from the fluorine containing gas (may be activated by a plasma) can fill the oxygen vacancies in the high-k dielectric.

Abstract: A substrate processing apparatus includes a spray nozzle that allows a plurality of liquid droplets to collide with a substrate held by a spin chuck, a liquid piping that supplies a mixed liquid of water and a chemical liquid to the spray nozzle, a first flow control valve and a second flow control valve each of which changes the concentration of the chemical liquid in the mixed liquid, and a controller that causes the liquid piping to supply the mixed liquid having a concentration of the chemical liquid determined in accordance with a substrate to be processed.

Abstract: III-N semiconductor heterostructures including a raised III-N semiconductor structures with inclined sidewall facets are described. In embodiments, lateral epitaxial overgrowth favoring semi-polar inclined sidewall facets is employed to bend crystal defects from vertical propagation to horizontal propagation. In embodiments, arbitrarily large merged III-N semiconductor structures having low defect density surfaces may be overgrown from trenches exposing a (100) surface of a silicon substrate. III-N devices, such as III-N transistors, may be further formed on the raised III-N semiconductor structures while silicon-based transistors may be formed in other regions of the silicon substrate.

Abstract: The present application provides a low temperature poly-silicon thin film, a low temperature poly-silicon thin film transistor and manufacturing methods thereof, and a display device. The manufacturing method of a low temperature poly-silicon thin film comprises steps of: forming an amorphous silicon thin film on a base; and performing a laser annealing process on the amorphous silicon thin film by using a mask plate to form a low temperature poly-silicon thin film, wherein the mask plate includes a transmissive region and a shielding region surrounding the transmissive region, and two sides of the shielding region adjacent to the transmissive region are in concave-convex shapes. Performance of the low temperature poly-silicon thin film formed by the manufacturing method of a low temperature poly-silicon thin film in the present application is enhanced.

Abstract: The present invention relates to a method for forming a layer, to be patterned, of an element by using a fluorinated material, which has orthogonality, and a solvent, the method comprising: a first step of printing with the fluorinated material so as to form, on a surface of a substrate, a mask template provided with an exposure part and a non-exposure part; a second step of coating the exposure part with a material to be patterned; a the third step of lifting-off the non-exposure part with the fluorinated solvent so as to form the layer to be patterned in the exposure part.

Abstract: A photomask includes a reticle substrate, a main pattern disposed on the reticle substrate and defining a photoresist pattern realized on a semiconductor substrate, and anti-reflection patterns adjacent to the main pattern. A distance between a pair of the anti-reflection patterns adjacent to each other is a first length, and a width of at least one of the pair of anti-reflection patterns is a second length. A sum of the first length and the second length is equal to or smaller than a minimum pitch defined by resolution of an exposure process. A distance between the main pattern and the anti-reflection pattern nearest to the main pattern is equal to or smaller than the first length.

Abstract: A bipolar junction transistor includes an intrinsic base formed on a substrate. The intrinsic base includes a superlattice stack including a plurality of alternating layers of semiconductor material. A collector and emitter are formed adjacent to the intrinsic base on opposite sides of the base. An extrinsic base structure is formed on the intrinsic base.

Abstract: A method of forming a semiconductor structure includes depositing a first III-V layer over a substrate. The method includes depositing a first III-V compound layer over the first III-V layer. Depositing the first III-V compound layer includes depositing a lower III-V compound layer. Depositing the first III-V compound layer includes depositing an upper III-V compound layer over the lower III-V compound layer, wherein the first III-V layer has a doping concentration greater than that of the upper III-V compound layer. The method includes repeating depositing III-V compound layers until a number of III-V compound layers is equal to a predetermined number of III-V compound layers. The method includes forming a second III-V compound layer an upper most III-V compound layer, wherein the second III-V compound layer is undoped or doped. The method includes forming an active layer over the second III-V compound layer.

Abstract: A system for manufacture of I-III-VI-absorber photovoltaic cells involves sequential deposition of films comprising one or more of silver and copper, with one or more of aluminum indium and gallium, and one or more of sulfur, selenium, and tellurium, as compounds in multiple thin sublayers to form a composite absorber layer. In an embodiment, the method is adapted to roll-to-roll processing of photovoltaic cells. In an embodiment, the method is adapted to preparation of a CIGS absorber layer having graded composition through the layer of substitutions such as tellurium near the base contact and silver near the heterojunction partner layer, or through gradations in indium and gallium content. In a particular embodiment, the graded composition is enriched in gallium at a base of the layer, and silver at the top of the layer. In an embodiment, each sublayer is deposited by co-evaporation of copper, indium, gallium, and selenium, which react in-situ to form CIGS.

Abstract: A silicon-based substrate on which a nitride compound semiconductor layer is formed on a front surface thereof, including a first portion provided on the front surface side which has a first impurity concentration and a second portion provided on an inner side of the first portion which has a second impurity concentration higher than the first impurity concentration, wherein the first impurity concentration being 1×1014 atoms/cm3 or more and less than 1×1019 atoms/cm3. Consequently, there is provided the silicon-based substrate in which the crystallinity of the nitride compound semiconductor layer formed on an upper side thereof can be maintained excellently while improving a warpage of the substrate.

Abstract: A method of forming an integrated circuit includes forming a patterned mask layer on a material layer, wherein the patterned mask layer has a plurality of first features, and a first distance between adjacent first features of the plurality of first features. The method further includes patterning the material layer to form the first features in the material layer. The method further includes increasing the first distance between adjacent first features of the plurality of first features to a second distance. The method further includes treating portions of the material layer exposed by the patterned mask layer. The method further includes removing the patterned mask layer; and removing non-treated portions of the material layer.

Abstract: Disclosed herein is a new and improved system and method for fabricating monolithically integrated diamond semiconductor. The method may include the steps of seeding the surface of a substrate material, forming a diamond layer upon the surface of the substrate material; and forming a semiconductor layer within the diamond layer, wherein the diamond semiconductor of the semiconductor layer has n-type donor atoms and a diamond lattice, wherein the donor atoms contribute conduction electrons with mobility greater than 770 cm2/Vs to the diamond lattice at 100 kPa and 300K, and wherein the n-type donor atoms are introduced to the lattice through ion tracks.

Abstract: A method for removing crystal originated particles from a crystalline silicon body having opposite first and second surfaces includes: increasing a surface area of at least one of the first and second surfaces by an etch process; and oxidizing the increased surface area at a temperature of at least 1000° C. and for a duration of at least 20 minutes.

Abstract: An electroplating apparatus that promotes uniform electroplating on the substrates having thin seed layers includes a convex anisotropic high resistance ionic current source (AHRICS), such as an electrolyte-permeable resistive domed plate. The AHRICS is positioned in close proximity of the substrate, so that a distance from the central portion of the AHRICS to the substrate is smaller than the distance from the edge portion of the AHRICS to the substrate. The apparatus further includes a plating chamber configured to hold the electrolyte and an anode. The apparatus further includes a substrate holder configured to hold the substrate. In some embodiments, the apparatus further includes a secondary (thief) cathode configured to divert ionic current from the near-edge region of the substrate.

Abstract: A semiconductor device is provided. The semiconductor device includes a semiconductor substrate including a first doped region and a second doped region and a gate stack on the semiconductor substrate. The semiconductor device also includes a main spacer layer on a sidewall of the gate stack and a protection layer between the main spacer layer and the semiconductor substrate. The protection layer is doped with a quadrivalent element. The semiconductor device further includes an insulating layer formed over the semiconductor substrate and the gate stack and a contact formed in the insulating layer. The contact includes a first portion contacting the first doped region, and the contact includes a second portion contacting the second doped region. The first portion extends deeper into the semiconductor substrate than the second portion.

Abstract: A method for providing a uniform recess depth between different fin gap sizes includes depositing a dielectric material between fins on a substrate. Etch lag is tuned for etching the dielectric material between narrow gaps faster than the dielectric material between wider gaps such that the dielectric material in the narrow gaps reaches a target depth. An etch block is formed in die narrow gaps. The wider gaps are etched to the target depth. The etch block is removed.

Abstract: Disclosed is a method of chemically-mechanically polishing a substrate. The method comprises, consists of, or consists essentially of (a) contacting a substrate containing at least one Group III-V material, with a polishing pad and a chemical-mechanical polishing composition comprising water, abrasive particles having a negative surface charge, and an oxidizing agent for oxidizing the Group III-V material in an amount of from about 0.01 wt. %to about 5 wt. %, wherein the polishing composition has a pH of from about 2 to about 5; (b) moving the polishing pad and the chemical-mechanical polishing composition relative to the substrate; and (c) abrading at least a portion of the substrate to polish the substrate. In some embodiments, the Group III-V material is a semiconductor that includes at least one element from Group III of the Periodic Table and at least one element from Group V of the Periodic Table.

Abstract: Embodiments of the invention describe a method and apparatus for multi-film deposition and etching in a batch processing system. According to one embodiment, the method includes arranging the substrates on a plurality of substrate supports in a process chamber, where the process chamber contains processing spaces defined around an axis of rotation in the process chamber, rotating the plurality of substrate supports about the axis of rotation, depositing a first film on a patterned film on each of the substrates by atomic layer deposition, and etching a portion of the first film on each of the substrates, where etching a portion of the first film includes removing at least one horizontal portion of the first film while substantially leaving vertical portions of the first film. The method further includes repeating the depositing and etching steps for a second film that contains a different material than the first film.

Abstract: Disclosed is a pattern forming method including: forming an acrylic resin layer on an underlayer; forming an intermediate layer on the acrylic resin layer; forming a patterned EUV resist layer on the intermediate layer; forming a pattern on the acrylic resin layer by etching the intermediate layer and the acrylic resin layer with the EUV resist layer as an etching mask; removing the EUV resist layer and the intermediate layer after the pattern is formed on the acrylic resin layer; and smoothing a surface of the acrylic resin layer after the EUV resist layer and the intermediate layer are removed.

Abstract: A method for monitoring a rapid heating process to which a semiconductor wafer is subjected includes performing the heating process for a region of the semiconductor wafer, irradiating the semiconductor wafer with a laser beam, detecting light of the laser beam that is reflected from the semiconductor wafer, creating haze data based on the detected light and determining heated regions and/or transition regions between heated and non-heated regions of the semiconductor wafer on the basis of the haze data.

Abstract: A method of fabricating a semiconductor structure includes forming a plurality of semiconductor fins disposed on a semiconductor substrate, wherein at least one of the fins is an unwanted fin including a semiconductor material; providing a conformal protective layer over the plurality of semiconductor fins; forming a mask having an opening over the unwanted fin; removing a portion of the unwanted fin to expose a fin spike; oxidizing the fin spike to form an oxidized semiconductor material; and removing the oxidized semiconductor material to expose a fin base.

Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

Abstract: A method is provided. The method includes attaching a bridge layer to a first substrate. The method also includes forming a first connector, the first connector electrically connecting the bridge layer to the first substrate. The method also includes coupling a first die to the bridge layer and the first substrate, and coupling a second die to the bridge layer.

Abstract: A package substrate and a semiconductor package are provided. The package substrate includes an insulating layer having opposing first and second surfaces; a first wiring layer formed in the insulating layer, exposed from the first surface of the insulating layer, and having a plurality of first conductive pads; a second wiring layer formed in the insulating layer, exposed from the second surface, and having a plurality of second conductive pads; a third wiring layer formed on the first surface and electrically connected with the first wiring layer; a plurality of first metal bumps formed on the first conductive pads corresponding; and at least one conductive via vertically embedded in the insulating layer and electrically connected to the second and third wiring layers. Therefore, the surfaces of first conductive pads are reduced, and the non-wetting between the first conductive pads and the solder materials formed on conductive bumps is avoided.

Abstract: Disclosed herein are an etching apparatus and method that are capable of performing an etching process in the state where a flexible film is wound around a drum-type jig, and a flexible film etched by the etching method. The etching apparatus includes a process tank containing an etchant therein, a drum-type jig rotatably provided in the process tank to be immersed into the etchant in a state where a flexible film on which a thin film is formed is wound around the drum-type jig, and a drum-type jig driver configured to rotate the drum-type jig. The etching apparatus has a compact structure to efficiently perform the etching process on the large area flexible film on which the thin film is formed.

Abstract: According to the present disclosure, there is provided a substrate holding module that is capable of accommodating a substrate transferred by a transfer robot. The substrate holding module includes a pedestal including a holding mechanism configured to hold the substrate, a cover configured to cover the pedestal, and a moving mechanism configured to move the cover away from the pedestal.

Abstract: A substrate processing apparatus includes a washing liquid supply unit which supplies a washing liquid to a washing liquid discharge port which is open in the outer circumferential surface of a body, a rotation unit which relatively rotates the opposing member and the body around a rotational axis passing through the central portion of the upper surface of the substrate and a washing control unit which controls the washing liquid supply unit and the rotation unit so as to wash the cylindrical gap, where the washing control unit performs a rotation step of controlling the rotation unit so as to relatively rotate the opposing member and the body and a washing liquid discharging step of controlling the washing liquid supply unit so as to discharge a washing liquid from the washing liquid discharge port simultaneously with the rotation step.

Abstract: Disclosed is a liquid processing method of drying a substrate held horizontally after supplying deionized water to the substrate. The liquid processing method includes: supplying the deionized water to a front surface of the substrate; supplying a first solvent to the front surface of the substrate after supplying the deionized water; supplying a water-repellent agent to the front surface of the substrate to impart water-repellency to the front surface of the substrate; supplying a second solvent to the front surface of the substrate to which water-repellency is imparted; and removing the second solvent from the front surface of the substrate. A specific gravity of the first solvent is smaller than a specific gravity of the water-repellent agent, and a specific gravity of the second solvent is larger than the specific gravity of the water-repellent agent.

Abstract: A substrate cleaning apparatus comprises: a cleaning member 11,21 that comes into contact with a substrate W and cleans the substrate W; a member rotating unit 15, 25 that rotates the cleaning member 11, 21; a pressing drive unit 19, 29 that presses the cleaning member 11, 21 against the substrate W; a torque detecting unit 16, 26 for detecting torque applied to the member rotating unit 15, 25; and a control unit 50 that controls pressing force on the basis of a result of detection by the torque detecting unit 16, 26.

Abstract: A method for selectively etching one exposed material of a substrate relative to another exposed material of the substrate includes a) arranging the substrate in a processing chamber; b) setting a chamber pressure; c) setting an RF frequency and an RF power for RF plasma; d) supplying a plasma gas mixture to the processing chamber; e) striking the RF plasma in the processing chamber in one of an electric mode (E-mode) and a magnetic mode (H-mode); and f) during plasma processing of the substrate, changing at least one of the chamber pressure, the RF frequency, the RF power and the plasma gas mixture to switch from the one of the E-mode and the H-mode to the other of the E-mode and the H-mode.

Abstract: A thermal system includes a base member, a two-phase fluid, a tuning heater, and a chuck. The base member includes at least one fluid passageway. The two-phase fluid is disposed within the fluid passageway. A pressure of the two-phase fluid is controlled such that the two-phase fluid provides at least one of heating and cooling to the base member. The tuning heater is secured to the base member. The chuck is secured to the tuning heater opposite to the base member. The tuning heater includes a plurality of zones to fine tune a heat distribution provided by the base member to the chuck.

Abstract: System and methods for processing a substrate using a reactor with multiple heating zones and control of said heating zones using a common terminal shared between two power supplies are provided. The reactor includes a heater assembly for supporting the substrate and a showerhead for supplying process gases into the reactor. An inner heater and an outer heater are integrated in the heater assembly. An inner power supply has a positive terminal connected to a first end of the inner heater and a negative terminal is connected to a second end of the inner heater that is coupled to a common terminal. An outer power supply has a positive terminal connected to a first end of the outer heater and a negative terminal connected to a second end of the outer heater that is coupled to the common terminal. A common-terminal heater module is configured to receive a measured temperature that is proximate to the inner heater.

Abstract: A semiconductor die pick and place device comprising a handing mechanism comprising a pick arm movable between a placement location and a pick-up location. A reference feature is located on the pick arm, and a light reflecting module is carried by the pick arm. The light reflecting module is operable to reflect an image of the reference feature to an image capturing module such that the reference feature appears to the light reflecting module to be in focus at a virtual position that is equivalent to a position at the pick-up location and/or the placement location.

Abstract: A line charge volume and methods for use in delivery of gas to a reactor for processing semiconductor wafers is provided. The line charge volume includes a chamber that extends between a first end and a second end, and the first end includes an inlet port and an outlet port. A pressure sensor is integrated with the chamber. The pressure sensor has a measurement side for measuring a deflection of a diaphragm. The diaphragm is directly exposed to an interior of the chamber so that pressure produced by a gas that is provided into the chamber via the inlet port produces a force upon the diaphragm. The measurement side includes electronics for measuring a capacitance value corresponding to the deflection of the diaphragm. The deflection is correlated to a pressure difference, and the pressure difference is equivalent to a pressure volume (Pv) of the chamber.

Abstract: Detection circuit for detecting electrical capacitance of electrode device in electrostatic holding device with clamp carrier, particularly for detecting component held by holding device, includes phase control circuit couplable to electrode device and has reference oscillator device, phase comparator and VCO circuit (VCOC). Phase comparator is arranged to generate a control voltage of VCOC as a function of reference signal from reference oscillator device and of VCO feedback signal from VCOC, at least one phase control circuit is configured for controlling VCOC as a function of capacitance to be detected, and for outputting an output signal characteristic of capacitance based on control voltage of VCOC, phase control circuit is configured for connection to electrode device such that VCOC contains capacitance to be detected as frequency-determining component, and reference oscillator device is configured for generating reference signal with adjustable reference frequency.

Abstract: A wafer container that reduces or alleviates one or more of the problems associated with excessive container wall deflection due to loading and excessive particulate generation, particularly as those problems are experienced with containers for 450 mm diameter and larger wafers. The container has an enclosure and door with interlocking features to enable transfer of tension load to the door to minimize deflection of container surfaces. The container may include a gasketing arrangement compatible with the interlock feature. The container may include a removable door guide that improves centering of the door during door installation, and that is made of low particle generating material to reduce particulates.

Abstract: A wafer grooving apparatus (100) for forming an elongate recess (103) in a semiconductor wafer surface, the apparatus comprising: a wafer table (110) for receiving and holding a semiconductor wafer; a radiation device (120) for generating a radiation beam (121); a beam directing device (130) for directing the radiation beam to a top surface (102) of the wafer so as to create a beam spot (142) where the radiation beam ablates wafer material on the wafer surface to form a recess; a wafer table displacement drive (170) for effecting a mutual displacement between the radiation beam and the wafer surface in a radiation beam displacement direction; a recess profile measuring device (180) arranged at a predetermined distance behind the beam directing device in the radiation beam displacement direction effected by the wafer table displacement drive for measuring a depth profile of the recess that has been formed by the radiation beam.

Abstract: A substrate aligner providing minimal substrate transporter extend and retract motions to quickly align substrate without back side damage while increasing the throughput of substrate processing. In one embodiment, the aligner having an inverted chuck connected to a frame with a substrate transfer system capable of transferring substrate from chuck to transporter without rotationally repositioning substrate. The inverted chuck eliminates aligner obstruction of substrate fiducials and along with the transfer system, allows transporter to remain within the frame during alignment. In another embodiment, the aligner has a rotatable sensor head connected to a frame and a substrate support with transparent rest pads for supporting the substrate during alignment so transporter can remain within the frame during alignment. Substrate alignment is performed independent of fiducial placement on support pads.

Abstract: A chuck for wafer processing that counters the deleterious effects of thermal expansion of the wafer. Also, a combination of chuck and shadow mask arrangement that maintains relative alignment between openings in the mask and the wafer in spite of thermal expansion of the wafer. A method for fabricating a solar cell by ion implant, while maintaining relative alignment of the implanted features during thermal expansion of the wafer.

Abstract: A substrate support includes an inner portion arranged to support a substrate, an edge ring surrounding the inner portion, and a controller that calculates a desired pocket depth of the substrate support. Pocket depth corresponds to a distance between an upper surface of the edge ring and an upper surface of the substrate. Based on the desired pocket depth, the controller selectively controls an actuator to raise and lower at least one of the edge ring and the inner portion to adjust the distance between the upper surface of the edge ring and the upper surface of the substrate.

Abstract: According to various aspects and embodiments, a method for forming a packaged electronic device is provided. In accordance with one embodiment, the method comprises depositing a layer of temporary adhesive material on at least a portion of a surface of a first substrate having a coefficient of thermal expansion, depositing a layer of dielectric material on at least a portion of the layer of temporary adhesive material, forming at least one seal ring on at least a portion of the layer of dielectric material, providing a second substrate having a coefficient of thermal expansion that is substantially the same as the coefficient of thermal expansion of the first substrate, the second substrate having at least one bonding structure attached to a surface of the second substrate, and aligning the at least one seal ring to the at least one bonding structure and bonding the first substrate to the second substrate.

Abstract: A substrate support includes an inner portion arranged to support a substrate, a lift ring surrounding the inner portion, the lift ring arranged to support an outer edge of the substrate, and a controller configured to control an actuator to adjust a height of the lift ring relative to the inner portion by selectively raising and lowering at least one of the lift ring and the inner portion of the substrate support. To adjust the height of the lift ring, the controller selectively adjusts the height of the lift ring to a transfer height for transfer of the substrate to the lift ring and retrieval of the substrate from the lift ring, and adjusts the height of the lift ring to a processing height for processing of the substrate.

Abstract: An array of gated devices includes a plurality of gated devices arranged in rows and columns and individually including an elevationally inner region, a mid region elevationally outward of the inner region, and an elevationally outer region elevationally outward of the mid region. A plurality of access lines are individually laterally proximate the mid regions along individual of the rows. A plurality of data/sense lines are individually elevationally outward of the access lines and electrically coupled to the outer regions along individual of the columns. A plurality of metal lines individually extends along and between immediately adjacent of the rows elevationally inward of the access lines. The individual metal lines are directly against and electrically coupled to sidewalls of the inner regions of each of immediately adjacent of the rows. The metal lines are electrically isolated from the data/sense lines. Other arrays of gated devices and methods of forming arrays of gated devices are disclosed.