Abstract: An apparatus includes one or more disc media cassettes configured to store multiple disc-based media. Multiple disc drives are configured to read and write data to the multiple disc-based media. A robotic delivery device is configured to transport a selected disc-based media to and from at least one disc drive of the multiple disc drives, and to transport the selected disc-based media directly to a spindle on the at least one disc drive.

Abstract: A method of video encoding is provided to reduce the cost of network DVR storage by building on a concept of Just-In Time (JIT) transcoding which eliminates storing all formats of content in a DVR. A super-encoding procedure is provided that encodes a high resolution format, such as HEVC, while metadata is provided for lower resolution formats, such as MPEG4. The metadata can include items like motion vectors to reduce the computational costs during JIT transcoding. The super-encoded data is stored in memory of the DVR. High resolution encoded data is read directly out of the DVR memory, while lower resolutions are transcoded from the DVR memory data using the metadata to increase efficiency.

Abstract: The portable sound recorder (1) according to the invention comprises A) a plurality of microphones (1A-F) arranged for picking up voices or sounds from an external environment; B) a protective outer shell (10) that encloses: B.1) a logic unit (2) programmed or in any case arranged for processing the electrical or opto-electronic signals emitted by the plurality of microphones improving the quality of the sounds recorded; B.2) a mass memory (4) arranged for memorising and store/conserve the sounds picked up by the plurality of microphones; B.3) an electric power supply (6) that supplies the logic unit and the mass memory; and where the plurality of microphones comprises at least two microphones of the Micro-ElectroMechanical System (MEMS) type.

Abstract: Techniques and apparatuses for generating highlight reels are described. These techniques and apparatuses enable a user to quickly and easily generate a highlight reel to highlight audiovisual media, such as photos and video clips.

Abstract: A system and method for automated video editing. A reference media is selected and analyzed. At least one video may be acquired, and thereby synced to the reference audio media. Once synced, audio analysis is used to assemble an edited video. The audio analysis can include information, including user inputs, video analysis, and metadata. The system and method for automated video editing may be applied to collaborative creation, simulated stop motion animation, and real-time implementations.

Abstract: Various embodiments of the invention provide systems and methods for low bandwidth consumption online content editing, where user-created content comprising high definition/quality content is created or modified at an online content editing server according to instructions from an online content editor client, and where a proxy version of the resulting user-created content is provided to online content editor client to facilitate review or further editing of the user-created content from the online content editor client. In some embodiments, the online content editing server utilizes proxy content during creation and modification operations on the user-created content, and replaces such proxy content with corresponding higher definition/quality content, possibly when the user-created content is published for consumption, or when the user has paid for the higher quality content.

Abstract: Systems and methods for creating videos played on an audio track are provided. In some embodiments, a master take may be selected after one or more video takes are captured. The video portions of the takes may then be played on top of the audio track of the master take. The takes may be analyzed to determine notable events occurring within each take. The video takes may be played on top of the audio track of the chosen master take so that they all appear integrated into a single scene. Clips from the video takes may be paired or matched with certain sections of the audio track based on, for example, the notable events.

Abstract: An imaging device includes an imaging element that acquires a first image based on signal charge generated during a first accumulation time, and a second image based on signal charge generated during a second accumulation time relatively longer than the first accumulation time and synchronized with the first image during a synchronization period including the first accumulation time, and a moving image file generating unit that generates a moving image file including a first moving image based on the first image, a second moving image based on the second image, and synchronization information for synchronizing the first moving image and the second moving image frame by frame.

Abstract: According to various embodiments, a content marking command is received from a mobile device at a particular time. For example, a user selection of the content marking command may be received via a user interface displayed on the mobile device. The content marking command may indicate a user interest in a particular moment of an event viewed by the user. Moreover, the event viewed by the user and video content data corresponding to the event may be identified. Further, content marking data may be generated, whether content marking data indicates a particular portion of the identified video content data corresponding to the particular moment of the event.

Abstract: A data storage system allows a subscriber to store data at the time the subscriber experiences the date with an indication, such as a press of a button or a voice command. The indication causes a request to obtain and store the data to be issued. For example, the subscriber can store music while listening to it, store or request movies while viewing them, or store movie soundtracks while viewing movies. The entire music file can be stored, for example, in a vehicle in which the subscriber is traveling. For some environments, such as storage in a cellular telephone, a portion of the music is stored in a format compatible for that environment, such as cellular telephone ring tone format. When the indication is received, a determination is made as to which music is required, generally by determining the time of the indication. The music heard by the listener is then downloaded for storage in accordance with the subscriber's request.

Abstract: Aspects of the invention described here are directed to a tape library that is constructed within an integrated with a standard freight/shipping container to form a freight/shipping container tape library. The freight/shipping container library can be assembled at a manufacturing site, loaded with tape media, equipped with the tape drives, provided with robotic transporters and all the necessary computing systems, wiring, and electronics to fully function as a storage system when transported to an end user location.

Abstract: A disk drive includes a housing, a disk recording medium disposed in the housing, and a plurality of filters disposed along a flow channel formed in the housing and overlapped with each other. Each of the filters including an outer member formed of an electrostatic woven fabric and electrostatic non-woven fibers contained in an enclosed space formed by the outer member.

Abstract: A hermetically-sealed hard disk drive (HDD) involves the inner surfaces of sidewalls of a second cover overlapping with and adhesively bonded with the outermost surfaces of sidewalls of an enclosure base. Matching angled sidewalls for the inner and outermost surfaces, and an adhesive bond that provides a hermetic seal in which a ratio of the height to the thickness of the adhesive bond is in a range of 50-100:1, may be utilized to provide a hermetic seal having a long, narrow diffusion path to inhibit diffusion of gas through the adhesive bond. The second cover may include preformed corner corrugations, and the base may include corner pockets in which corner pleats, formed with the corner corrugations by bending inward the cover sidewalls, are received within when the cover and base are bonded together.

Abstract: A SSD storage module comprising a printed circuit board (1), an encapsulating colloid (2), and an electronic circuit (3) welded on an inner surface of the printed circuit board (1) and having a data storage function; the encapsulating colloid (2) is formed on the inner surface of the printed circuit board (1) and is configured for seamlessly encapsulating the electronic circuit (3), an outer surface of the printed circuit board (1) is provided with a plurality of metal contact pieces (11), the plurality of metal contact pieces (11) are electrically connected with the electronic circuit (3), and the plurality of metal contact pieces (11) comprise a plurality of SATA interface contact pieces (110).

Abstract: A vertical non-volatile memory device includes a substrate, and a first stack of word lines and a second stack of word lines extending in a first direction on the substrate and separated from each other in a second direction perpendicular to the first direction. The device further includes first array lines extending in the second direction on the first and the second stack, and connected to word lines of the first and the second stack through at least two of first via contacts in a same level. The device further include first word select lines being in a same level and extending in the first direction, and connected to each of the first array lines through at least one of second via contacts. Ends of each of the first and the second stack have a form of stairs on the substrate.

Abstract: Apparatuses included a single-ended main input/output line in a semiconductor device are described. An example apparatus includes: a pair of differential data lines coupled to a sense amplifier; a single-ended data line; a first transistor coupled between the one of the pair of differential data lines and the power line and coupled to the single-ended data line at a control node thereof; a second transistor coupled between the single-ended data line and the power line and coupled to the one of the pair of differential data lines at a control node thereof; and a third transistor coupled between the single-ended data line and the other of the pair of differential data lines.

Abstract: A memory device operable in an ultra-deep power-down mode can include: a command user interface; a voltage regulator having an output that provides a supply voltage for a plurality of components of the memory device, where the plurality of components comprises the command user interface; a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode; the memory device being operable to enter the ultra-deep power-down mode in response to receiving a first predetermined command that causes the output of the voltage regulator to be disabled to completely power down the plurality of components during the ultra-deep power-down mode; and the memory device being operable to exit the ultra-deep power-down mode in response to receiving one of a hardware reset command sequence, a reset pin assertion, a power supply cycling, and a second predetermined command.

Abstract: Apparatuses and methods for read threshold voltage selection are provided. One example method can include setting a first soft read threshold voltage and a second soft read threshold voltage based on a difference between a first number of memory cells that are read as being programmed to a first state when read using a first threshold voltage and a second number of memory that are read as being programmed to the first state when read using another threshold voltage.

Abstract: An amplifier circuit is disclosed having an amplifier with first and second input terminals. The amplifier circuit includes a first compensation capacitor coupled to the first input terminal and having a first capacitance, a second compensation capacitor coupled to the second input terminal and having a second capacitance, a first transistor coupled between the first compensation capacitor and a reference voltage and having a gate terminal that receives a first control signal, and a second transistor coupled between the second compensation capacitor and the reference voltage and having a gate terminal for receiving a second control signal. The amplifier circuit includes a programmable latch circuit arranged to provide the first and second control signals, wherein the first and second transistors are of the same conductivity type, and the first control signal and the second control signal are complementary signals with respect to each other.

Abstract: Examples of the present disclosure provide apparatuses and methods for storing a first element in memory cells coupled to a first sense line and a plurality of access line. The examples can include storing a second element in memory cells coupled to a second sense line and the plurality of access lines. The memory cells coupled to the first sense line can be separated from the memory cells coupled to the second sense line by at least memory cells coupled to a third sense line and the plurality of access lines. The examples can include storing the second element in the memory cells coupled to the third sense line.

Abstract: Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

Abstract: Memory devices, systems, and methods that maximize command and address (CA) signal group rate with minimized margin degradation across a channel and associated operating modes are disclosed and described. In one example, the operating mode can be 1 bit per 1.5 clock cycles.

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received MRW is either ignored or implemented by the first DRAM.

Abstract: The semiconductor memory includes a plurality of word lines; and a plurality of columns including a plurality of resistive storage cells corresponding to the plurality of word lines, the plurality of columns being divided into a plurality of pages each having one or more columns; a memory circuit coupled to the semiconductor memory to sense data stored in the resistive storage cells; and a memory control circuit coupled to the semiconductor memory and the memory circuit to control sensing of the stored data by the memory circuit to, in a read operation, sense data of resistive storage cells included in a selected page by continuously active-precharging one or more word lines among the plurality of word lines in a period in which the selected page among the plurality of pages is activated.

Abstract: Provided is a memory control technique for avoiding that the issue of a refresh command and the issue of a calibration command are arranged in succession. The memory control circuit issues a refresh command to make a request for a refresh operation based on a set refresh cycle, and issues a calibration command to make a request for a calibrating operation based on a set calibration cycle, for which the control function of suppressing the issue of the calibration command only for a given time after the issue of the refresh command, and suppressing the issue of the refresh command only for a given time after the issue of the calibration command is adopted.

Abstract: A high speed, low power method to control and switch the magnetization direction of a magnetic region in a magnetic device for memory cells using spin polarized electrical current. The magnetic device comprises a pinned magnetic layer, a reference magnetic layer with a fixed magnetization direction and a free magnetic layer with a changeable magnetization direction. The magnetic layers are separated by insulating non-magnetic layers. A current can be applied to the device to induce a torque that alters the magnetic state of the device so that it can act as a magnetic memory for writing information. The resistance, which depends on the magnetic state of the device, can be measured to read out the information stored in the device.

Abstract: A method and circuit for implementing Electronic Fuse (eFuse) visual security of stored data using embedded dynamic random access memory (EDRAM), and a design structure on which the subject circuit resides are provided. The circuit includes EDRAM and eFuse circuity having an initial state of a logical 0. The outputs of the eFuse and an EDRAM are connected through an exclusive OR (XOR) gate, enabling EDRAM random data to be known at wafer test and programming of the eFuse to provide any desired logical value out of the XORed data combination.

Abstract: Systems and methods are disclosed for configuring dynamic random access memory (DRAM) in a personal computing device (PCD). An exemplary method includes providing a shared command access (CA) bus in communication with a first DRAM and a second DRAM. A first command from a system on a chip (SoC) is received at the first DRAM and the second DRAM. A decoder of the first DRAM determines whether to mask a mode register write (MRW) in response to the received first command. A second command containing configuration information is received vie the shared CA bus at the first DRAM and the second DRAM. Responsive to the determination by the decoder of the first DRAM, the received. MRW is either ignored or implemented by the first DRAM.

Abstract: This technology relates to a semiconductor device. The semiconductor device may include a sense amplification unit suitable for sensing and amplifying data loaded onto a data line pair, and a voltage supply unit suitable for supplying a pull-down power line with a first voltage in response to a pull-down driving signal in an active mode, and for supplying the pull-down power line with a second voltage having a higher voltage level than the first voltage in response to the pull-down driving signal during an initial period of the active mode.

Abstract: A semiconductor device includes a plurality of memory cells being disposed in a matrix in a memory cell array area, each of the memory cells includes a capacitive element including a cell plate electrode, a capacitive insulating film, and a storage node electrode, and a switch transistor coupled between the storage node electrode and a bit line and being controlled based on a potential of a word line, a peripheral circuit disposed in a peripheral circuit area adjacent to the memory cell array area, and a signal line formed at a boundary between the memory cell array area and the peripheral circuit area. The capacitive element has a cylinder shape. The storage node electrode is formed on inner wall of a hole which penetrates through a first insulating film layer and a second insulating film layer.

Abstract: Embodiments are generally directed to memory refresh operation with page open. An embodiment of a memory device includes a memory array including a plurality of memory banks; and a control logic to provide control operations for the memory device including a page open refresh mode, wherein the control logic is to perform a refresh cycle in response to a refresh command with a memory page of the memory array open, the refresh operation including precharge of one or more memory banks of the plurality of memory banks, refresh of the one or more memory banks, and activation of the memory page.

Abstract: A semiconductor device enabling expansion of a noise margin. For example, in a memory area in which each memory cell MC is coupled to a word line WLA for a first port and a word line WLB for a second port, and a plurality of memory cells MC are disposed in a matrix shape, each word line is disposed in the order of WLA0, WLB0, WLB1, WLA1, WLA2. Further, a pitch d2 between WLA-WLA and between WLB-WLB is made smaller than a pitch d1 between WLA-WLB. As such, the word lines of an identical port are disposed at the pitch d2 on one of both sides of a certain word line and the word lines of different ports are disposed at the pitch d1 on the other.

Abstract: In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage distribution circuit may connect a word line driver circuit to a bit-cell voltage circuit such that an operating voltage is received at a bit-cell circuit before a word line signal form the word line driver circuit is received at the bit-cell circuit, where the operating voltage is provided by the bit-cell voltage circuit. The method may further include the bit-cell circuit providing the operating voltage along a bit line based on a data stored at the bit-cell circuit and based on the word line signal. In some embodiments, a static noise margin of one or more portions of the bit-cell circuit may be improved. Additionally, in some cases, a wakeup time of the bit-cell circuit may be ignored, resulting in a faster read operation.

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract: Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including dual demarcation voltage sensing before writes.

Abstract: The present disclosure relates to a method and apparatus for performing a read operation of an RRAM cell, which applies a non-zero bias voltage to unselected bit-lines and select-lines to increase a read current window without damaging corresponding access transistors. In some embodiments, the method may be performed by activating a word-line coupled to a row of RRAM cells comprising a selected RRAM device by applying a first read voltage to the word-line. A second read voltage is applied to a bit-line coupled to a first electrode of the selected RRAM device. One or more non-zero bias voltages are applied to bit-lines and select-lines coupled to RRAM cells, within the row of RRAM cells, having unselected RRAM devices.

Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Abstract: A semiconductor memory apparatus includes a column address decoding unit configured to decode a column address and generate a column select signal; a row address decoding unit configured to decode a row address and generate a word line select signal; a driving driver unit configured to provide different voltages to a plurality of resistive memory elements in response to the column select signal; a sink current control unit configured to generate a plurality of sink voltages with different voltage levels in response to the word line select signal; and a plurality of current sink units configured to flow current from the plurality of respective resistive memory elements to a ground terminal in response to the plurality of sink voltages.

Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.

Abstract: A technique for reducing power consumption of a content addressable memory (CAM) system is provided. In a CAM system, an equalizer circuit is coupled to a border portion between a plurality of match line parts generated by dividing each match line corresponding to a piece of entry data, and a precharge circuit precharges each of the match line parts collectively corresponding to a piece of entry data to voltage VDD or VSS. When comparing the entry data and search data, the equalizer circuit couples, in accordance with a control signal, the match line parts after the match line parts are precharged by the precharge circuit. In an equalization period, search operation through the search line is started. A search transistor for comparing search data and entry data includes an NMOS search transistor.

Abstract: According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.

Abstract: In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.

Abstract: There are provided a memory chip and an operating method thereof. A memory chip includes a main memory block including a plurality of sub-memory blocks, a peripheral circuit for programming memory cells included in the sub-memory blocks in units of pages, and a control circuit for controlling the peripheral circuit such that, after a program operation of a sub-memory block selected among the sub-memory blocks is completed, a program operation of a sub-memory block selected next among the sub-memory blocks is performed.

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract: Systems and methods for detecting a command execution abort are disclosed. Power failure may abort the writing of data in a memory device prematurely, resulting in potential data corruption. A memory device controller in the memory device sends commands, such as write or erase commands, to one or more memory integrated circuit chips. Along with executing the commands, the memory integrated circuit chips track execution of the commands by storing the address at which the command is being executed along with flag(s) indicative of the progress executing the command (e.g., command has begun and/or completed execution). When a power failure occurs, the memory device controller may poll the memory integrated circuit chips for the address/flags information to determine whether (or where) the command abort occurred. Thus, relying on the address/flag(s), the memory device controller may more quickly or easily determine whether a command abort has occurred.

Abstract: According to one embodiment, a semiconductor device includes a memory cell array, word lines, bit lines, a source line, and a circuit controlling a read operation of the information. The memory cell array includes a plurality of memory strings. The plurality of memory strings includes a plurality of memory cells connected in series. The plurality of memory cells connected to one of the word lines is included in a unit of a page. Each bit line is connected to one end of the plurality of memory strings. The source line is connected to one other end of the plurality of memory strings. The circuit applies a pre-charge voltage to the plurality of bit lines in the read operation and changes the pre-charge voltage according to at least one of a number of used pages, a position of the page, or a number of programmed memory cells.

Abstract: A syndrome weight of failed decoding attempts is used to select parameters for future read retry operations. The following exemplary steps are performed until a decoding success or a predefined limited number of readings is reached: (i) reading a codeword using different read threshold voltages; (ii) mapping the readings to a corresponding likelihood value using a likelihood value assignment; and (iii) recording a syndrome weight for failed decoding attempts of the readings using the different read threshold voltages.

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: A circuit includes a current generating circuit and a sense amplifier. The current generating circuit includes a first current mirror that generates a first current having a first current value less than a value of a first cell current through a first reference cell, and based on a ratio of the first cell current to the first current. A second current mirror generates a second current having a second current value less than a value of a second cell current through a second reference cell, and based on a ratio of the second cell current to the second current. The current generating circuit generates a reference current having a reference current value based on the first and second current values. The sense amplifier receives a third current having a third current value and generates a voltage output based on the reference and third current values.