Abstract: A semiconductor device includes a silicon substrate, a silicon germanium (SiGe) layer including a lower portion extending over the silicon substrate and a fin structure protruding above the lower portion, a first dielectric layer disposed over a side surface of the fin structure and a top surface of the lower portion of the silicon germanium (SiGe) layer, an indium gallium arsenide (InGaAs) layer disposed over a surface of the first dielectric layer, a high k oxide layer disposed over a surface of the InGaAs layer, and a metal layer disposed over a surface of the high k oxide layer. The InGaAs layer includes a source region, a channel region, and a drain region. The metal layer is configured to be a first gate electrode, and the fin structure in the SiGe layer is configured to be a second gate electrode.

Abstract: A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET.

Abstract: The present disclosure proposes a dual-gate thin film transistor and manufacturing method thereof and an array substrate. A manufacturing method includes: forming a first gate electrode, a gate insulating layer, a semiconductor layer, and an etch stop layer on a first substrate sequentially; forming a drain electrode, an independent electrode, and a source electrode on the exposed semiconductor layer; forming an insulating passivation layer on surfaces of the exposed etch stop layer, the drain electrode, the source electrode, and the independent electrode; and forming a second gate electrode on the insulating passivation layer in an area corresponding to the first gate electrode. The present disclosure can resolve the leakage current problem caused by the effective channel length between the source electrode and the drain electrode to improve the electrical properties of the dual-gate thin film transistor and improve its stability. The present disclosure can simplifies processes and reduce cost.

Abstract: The present invention provides a thin film transistor including a gate electrode, a source electrode, a drain electrode, and a semiconductor layer, which are laminated on a substrate. The semiconductor layer is a polysilicon thin film. The polysilicon thin film in regions corresponding to the source electrode and the drain electrode has a smaller crystal grain size than that of the polysilicon thin film in a channel region between the source electrode and the drain electrode.

Abstract: A semiconductor device with improved electrical characteristics is provided. A semiconductor device with improved field effect mobility is provided. A semiconductor device in which the field-effect mobility is not lowered even at high temperatures is provided. A semiconductor device which can be formed at low temperatures is provided. A semiconductor device with improved productivity can be provided. In the semiconductor device, there is a range of a gate voltage where the field-effect mobility increases as the temperature increases within a range of the gate voltage from 0 V to 10 V. For example, such a range of a gate voltage exists at temperatures ranging from a room temperature (25° C.) to 120° C. In the semiconductor device, the off-state current is kept extremely low (lower than or equal to the detection limit of a measurement device) within the above temperature range.

Abstract: A display device is disclosed, which includes: a substrate; a first conductive layer disposed on the substrate and including a gate with a gate edge parallel to a first direction; a semiconductor layer disposed on the first conductive layer; and a second conductive layer disposed on the semiconductor layer and including a drain and a data line extending along the first direction, the second conductive layer electrically connecting to the semiconductor layer, the drain including a drain edge parallel to the first direction, the gate edge located between the data line and the drain edge, and a projection of the drain on the substrate located in a projection of the semiconductor layer on the substrate. Herein, a maximum width of the semiconductor layer overlapping the gate edge along the first direction is smaller than maximum widths thereof overlapping the gate and the drain edge along the first direction.

Abstract: A vertical semiconductor transistor and a method of forming the same. A vertical semiconductor transistor has at least one semiconductor region, a source, and at least one gate region. The at least one semiconductor region includes a III-nitride semiconductor material. The source is formed over the at least one semiconductor region. The at least one gate region is formed around at least a portion of the at least one semiconductor region.

Abstract: Solar cells of varying composition are disclosed, generally including a central substrate, conductive layer(s), antireflection layers(s), passivation layer(s) and/or electrode(s). Multifunctional layers provide combined functions of passivation, transparency, sufficient conductivity for vertical carrier flow, the junction, and/or varying degrees of anti-reflectivity. Improved manufacturing methods including single-side CVD deposition processes and thermal treatment for layer formation and/or conversion are also disclosed.

Abstract: This invention relates to a novel structure of photovoltaic devices (e.g. photovoltaic cells also called as solar cells) are provided. The cells are based on the micro or nano scaled structures which could not only increase the surface area but also have the capability of self-concentrating the light incident onto the photonics devices. More specifically, the structures are based on 3D structure including quintic or quintic-like shaped micor-nanostructures. By using such structures reflection loss of the light from the cell is significantly reduced, increasing the absorption, which results in increasing the conversion efficiency of the solar cell, and reducing the usage of material while increasing the flexibility of the solar cell. The structures can be also used in other optical devices wherein the reflection loss and absorption are required to enhanced to significantly improve the device performances.

Abstract: Fabrication methods and structures relating to multi-level metallization for solar cells as well as fabrication methods and structures for forming back contact solar cells are provided.

Abstract: A method of growing a FE material thin film using physical vapor deposition by pulsed laser deposition or RF sputtering is disclosed. The method involves creating a target to be used for the pulsed laser deposition in order to create a KBNNO thin film. The resultant KBNNO thin film is able to be used in photovoltaic cells.

Abstract: A photovoltaic device is presented. The photovoltaic device includes a buffer layer disposed on a transparent conductive oxide layer; a window layer disposed on the buffer layer; and an interlayer interposed between the transparent conductive oxide layer and the window layer. The interlayer includes a metal species, wherein the metal species includes gadolinium, beryllium, calcium, barium, strontium, scandium, yttrium, hafnium, cerium, lutetium, lanthanum, or combinations thereof.

Abstract: A method and apparatus, the method comprising: forming first electrode portions on a substrate; providing a sheet of two dimensional material overlaying at least part of the first electrode portions; forming second electrode portions on a superstrate; positioning the superstrate overlaying the substrate so that the second electrode portions are aligned with the first electrode portions; and laminating the substrate and the superstrate together so that the sheet of two dimensional material is positioned between the aligned first electrode portions and the second electrode portions.

Abstract: The photoelectric conversion device includes a quantum dot accumulation zone, a base layer having current collecting properties which is disposed on at least one major surface of the quantum dot accumulation zone, and a plurality of columnar carrier collection zones, each extending from the base layer into the quantum dot accumulation zone and having an open end. Each of the carrier collection zones is composed mainly of metal oxide. An open end part has a higher mole ratio of oxygen to metal than a body part other than the open end part.

Abstract: A process of growth in the thickness of at least one facet of a colloidal inorganic sheet. By sheet is meant a structure having at least one dimension, the thickness, of nanometric size and lateral dimensions great compared to the thickness, typically more than 5 times the thickness. By homostructured is meant a material of homogeneous composition in the thickness and by heterostructured is meant a material of heterogeneous composition in the thickness. The process allows the deposition of at least one monolayer of atoms on at least one inorganic colloidal sheet, this monolayer being constituted of atoms of the type of those contained or not in the sheet. Homostructured and heterostructured materials resulting from such process as well as the applications of the materials are also described.

Abstract: The present disclosure provides interconnect elements and methods of using interconnect elements. In one embodiment, the interconnect element includes: a first end including at least three members, each member having a pair of parallel gap apertures for mounting an adjoining first component; a second opposing end including at least two members, each member having a pair of parallel gap apertures for mounting an adjoining second component; and one or more interconnect connecting portions to attach the first end of the interconnect element to the second end of the interconnect element.

Abstract: Flat top beam laser processing schemes are disclosed for producing various types of hetero-junction and homo-junction solar cells. The methods include base and emitter contact opening, back surface field formation, selective doping, and metal ablation. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero-junction solar cells. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, that are either planar or textured/three-dimensional. These techniques are highly suited to thin crystalline semiconductor, including thin crystalline silicon films.

Abstract: Solar cell element with a carrier (14), a thin film layer structure on a surface of the carrier, the thin film layer structure comprises a transparent first electrode layer (20), active layers (22, 23) in which a portion of the energy of the incident light is absorbed and a second electrode layer (24), the thin film layer structure has a light reflecting rear boundary surface, and the surface of said carrier (14) comprises at least two planar surface regions that close and angle with and form continuation of each other so that between them a recess is formed, and a portion of light reflected from the rear boundary surface of a first surface region will pass through the recess to fall on the second surface region and generates additional charge carriers therein, and the thin film structure on the surface regions constitutes a uniform uninterrupted thin film structure, wherein the extent of absorption of the thin film structure in the visible spectral region of light is at most 90% of the energy of the incident

Abstract: The invention concerns a method for producing a photovoltaic module, comprising:•—providing a plurality of bifacial photovoltaic cells each having a short-circuit current ratio (B),•—asymmetrically cutting each cell into two portions, such that the ratio between the surface areas of said portions is substantially equal to the short-circuit current ratio (B) of said cell or to the average short-circuit ratio of the set of cells,•—juxtapositioning said cell portions in a main plane of the module in order to form pairs of cell portions chosen such that the front face of the first portion has a short-circuit current substantially equal to the short-circuit current of the rear face of the second portion, said portions being arranged such that the front face of the first portion and the rear face of the second portion coincide with the front face of the module,•—creating an electrical connection of the front face of the first portion with the rear face of the second portion.

Abstract: A solar cell module comprises a solar cell element, first and second connection tabs, and first and second solder portions. The solar cell element includes a semiconductor substrate, a front busbar electrode, and a back busbar electrode. The first solder portion connects the front busbar electrode and the first connection tab. The second solder portion connects the back busbar electrode and the second connection tab. A distance between the first lateral surface and a first bonding surface where the first solder portion is bonded to the front busbar electrode is shorter than a distance between the first lateral surface and a second bonding surface where the second solder portion is bonded to the back busbar electrode. A distance between the second lateral surface and the first bonding surface is shorter than a distance between the second lateral surface and the second bonding surface.

Abstract: A method for producing a rear-side contact system for a silicon thin-film solar cell having pn junction formed from a silicon absorber layer and an emitter layer includes applying an organic insulation layer to the emitter layer; producing contact holes in the insulation layer as far as the absorber layer and the emitter layer; subsequently insulating the contact holes; subsequently applying a low-melting metal layer to form n and p contacts in the contact holes; separating the metal layer into n-contacting and p-contacting regions by laser-cutting; before applying the organic insulation layer to the emitter layer, applying a TCO layer; producing holes for contacts for the silicon absorber layer in the organic insulation; and subsequently selectively doping the produced holes for the contacts as far as the silicon absorber layer.

Abstract: A method of fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a metal layer on the dielectric layer. The method can also include configuring a laser beam with a particular shape and directing the laser beam with the particular shape on the metal layer, where the particular shape allows a contact to be formed between the metal layer and the solar cell structure.

Abstract: Systems and methods for the conversion of energy of high-energy photons into electricity which utilize a series of materials with differing atomic charges to take advantage of the emission of a large multiplicity of electrons by a single high-energy photon via a cascade of Auger electron emissions. In one embodiment, a high-energy photon converter preferably includes a linearly layered nanometric-scaled wafer made up of layers of a first material sandwiched between layers of a second material having an atomic charge number differing from the atomic charge number of the first material. In other embodiments, the nanometric-scaled layers are configured in a tubular or shell-like configuration and/or include layers of a third insulator material.

Abstract: A photoelectronic device includes a semiconductor substrate doped with a first type impurity, a second semiconductor layer doped with a second type impurity of an opposite type to the first type impurity, a transparent electrode formed on a second surface of the second semiconductor layer, the second surface being opposite a first surface on which the semiconductor substrate is formed, and a barrier layer disposed between the second semiconductor layer and the semiconductor substrate or between the second semiconductor layer and the transparent electrode. The second semiconductor layer has a band gap energy less than that of the semiconductor substrate, and the barrier layer includes a semiconductor material or an insulator having a band gap greater than that of the semiconductor substrate.

Abstract: Various laser processing schemes are disclosed for producing various types of hetero-junction and homo-junction solar cells. The methods include base and emitter contact opening, selective doping, metal ablation, annealing to improve passivation, and selective emitter doping via laser heating of aluminum. Also, laser processing schemes are disclosed that are suitable for selective amorphous silicon ablation and selective doping for hetero-junction solar cells. Laser ablation techniques are disclosed that leave the underlying silicon substantially undamaged. These laser processing techniques may be applied to semiconductor substrates, including crystalline silicon substrates, and further including crystalline silicon substrates which are manufactured either through wire saw wafering methods or via epitaxial deposition processes, or other cleavage techniques such as ion implantation and heating, that are either planar or textured/three-dimensional.

Abstract: The invention relates to a method for producing doping regions in a semiconductor layer of a semiconductor component, wherein the method includes the following steps: A) implanting a first dopant of a first doping type into at least one implantation region in the semiconductor layer, which implantation region adjoins a first side of the semiconductor layer; B) applying a doping layer, which contains a second dopant of a second doping type, indirectly or directly at least to the first side of the semiconductor layer, wherein the first and the second doping type are opposite; C) by the effect of heat, simultaneously driving the second dopant from the doping layer into the semiconductor layer and performing one or more of the processes of at least partially activating the implanted dopant in the implantation region and/or performing at least partial recovery of crystal damage in the semiconductor layer, which crystal damage was produced by the implantation, and/or driving in the first dopant from the implantatio

Abstract: The disclosed technology generally relates to chalcogenide thin films, and more particularly to ternary and quaternary chalcogenide thin films having a wide band-gap, and further relates to photovoltaic cells containing such thin films, e.g., as an absorber layer. In one aspect, a method of forming a ternary or quaternary thin film chalcogenide layer containing Cu and Si comprises depositing a copper layer on a substrate. The method additionally comprises depositing a silicon layer on the copper layer with a [Cu]/[Si] atomic ratio of at least 0.7, and thereafter annealing in an inert atmosphere. The method further includes performing a first selenization or a first sulfurization, thereby forming a ternary thin film chalcogenide layer on the substrate. In another aspect, a composite structure includes a substrate having a service temperature not exceeding 600° C.

Abstract: A method of manufacturing a solar cell is disclosed. The method includes forming a control passivation layer on a back surface of a semiconductor substrate containing impurities of a first conductivity type, forming an emitter region containing impurities of a second conductivity type opposite the first conductivity type and a back surface field region containing impurities of the first conductivity type on the control passivation layer, forming a passivation layer on the emitter region and the back surface field region, forming first and second openings in the passivation layer by using a pulse type laser having a continuously uniform intensity, forming a first electrode electrically and physically connected to the emitter region through the first opening, and forming a second electrode electrically and physically connected to the back surface field region through the second opening.

Abstract: The invention provides a packaging method for ultraviolet light emitting diode, comprising: (S1) providing a carrier, connected to an electrode; (S2) fixing an UV LED chip on the carrier and electrically connecting the UV LED chip to the electrodes; (S3) covering the UV LED chip with transparent silicon-and-oxygen-containing solution; and (S4) performing a thermal curing process.

Abstract: A group III-nitride semiconductor device comprises a light emitting semiconductor structure comprising a p-type layer and an n-type layer operable as a light emitting diode or laser. On top of the p-type layer there is arranged an n+ or n++-type layer of a group III-nitride, which is transparent to the light emitted from the underlying semiconductor structure and of sufficiently high electrical conductivity to provide lateral spreading of injection current for the light-emitting semiconductor structure.

Abstract: A core-shell nanowire device includes an eave region having a structural discontinuity from the p-plane in the upper tip portion of the shell to the m-plane in the lower portion of the shell. The eave region has at least 5 atomic percent higher indium content than the p-plane and m-plane portions of the shell.

Abstract: Solid state lighting (“SSL”) devices with improved contacts and associated methods of manufacturing are disclosed herein. In one embodiment, an SSL device includes an SSL structure having a first semiconductor material, a second semiconductor material spaced apart from the first semiconductor material, and an active region between the first and second semiconductor materials. The SSL device also includes a first contact on the first semiconductor material and a second contact on the second semiconductor material, where the first and second contacts define the current flow path through the SSL structure. The first or second contact is configured to provide a current density profile in the SSL structure based on a target current density profile.

Abstract: A light-emitting diode and a manufacturing method therefor are disclosed. The light-emitting diode comprises: a first conductive semiconductor layer; at least two light-emitting units arranged by being spaced from each other on the first conductive semiconductor layer, respectively including an active layer and a second conductive semiconductor layer, and including one or more contact holes through which the first conductive semiconductor layer is partially exposed; an additional contact area located between the light-emitting units; a second electrode making ohmic contact with the second conductive semiconductor layer; a lower insulation layer; and a first electrode making ohmic contact with the first conductive semiconductor layer through the contact holes of each of the light-emitting units and the additional contact area.

Abstract: The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprises: a metal connecting structure; a barrier layer on the metal connecting structure, the barrier layer comprising a first metal multilayer on the metal connecting structure and a second metal multilayer on the first metal multilayer; a metal reflective layer on the barrier layer; and a light-emitting stack electrically coupled to the metal reflective layer, wherein the first metal multilayer comprises a first metal layer comprising a first metal material and a second metal layer comprising a second metal material, and the second metal multilayer comprises a third metal layer comprising a third metal material and a fourth metal layer comprising a fourth metal material.

Abstract: An embodiment provides a light emitting device comprising: a substrate; a plurality of light emitting cells disposed on the substrate to be spaced apart from one another, each light emitting cell comprising a first conductive type semiconductor layer, an active layer, and a second conductive type semiconductor layer, the light emitting cell having a via hole passing through the second conductive type semiconductor layer, the active layer and a part of the first conductive type semiconductor layer; a first electrode layer electrically connected to the first conductive type semiconductor layer at a bottom of the via hole; a second electrode layer disposed on the second conductive type semiconductor layer; and a first passivation layer electrically separating the first electrode layer from the second electrode layer, wherein the first electrode layer of one light emitting cell is electrically connected to the second electrode layer of another light emitting cell adjacent to the one light emitting cell, and due t

Abstract: An optoelectronic semiconductor chip and a method for producing the same are disclosed. In an embodiment an optoelectronic semiconductor chip includes a support substrate, a semiconductor layer sequence having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type and an active layer arranged therebetween, and a mirror layer arranged between the support substrate and the semiconductor layer sequence. The chip further includes a dielectric encapsulation layer arranged at least partly between the semiconductor layer sequence and the support substrate and a transparent dielectric cover layer partially covering a region of the encapsulation layer, wherein the mirror layer and side flanks of the mirror layer are covered by an electrically conductive protective layer.

Abstract: A light emitting device of side-view type includes a substrate, a light emitting element, an insulating member and a light reflecting or sealing member. The substrate includes a pair of connection terminals at least on a first main surface. The light emitting element is disposed on a first main surface side of the substrate and connected to the connection terminals. The insulating member is disposed to cover at least a portion of the connection terminals. The light reflecting or sealing member covers the light emitting element. The connection terminals each includes an element connection portion and an outer connection portion disposed on the first main surface of the substrate. The outer connection portion is configured to connect with an external unit. The insulating member is placed in contact with the light reflecting or sealing member, and disposed between the element connection portion and the outer connection portion.

Abstract: An LED module according to the present invention includes: a mounting substrate; a first LED group including a plurality of LEDs mounted in a first light-emitting area extending in a first direction on the mounting substrate; a second LED group including a plurality of LEDs mounted in a second light-emitting area located outside the first light-emitting area; a dam material surrounding a periphery of the second light-emitting area; a first fluorescent resin coating the first LED group and causing the first light-emitting area to emit light having a first color temperature; and a second fluorescent resin coating at least the second LED group and causing the second light-emitting area to emit light having a second color temperature higher than the first color temperature, and viscosity of the first fluorescent resin is higher than viscosity of the second fluorescent resin.

Abstract: To provide an illumination method and a light-emitting device which are capable of achieving, under an indoor illumination environment where illuminance is around 5000 lx or lower when performing detailed work and generally around 1500 lx or lower, a color appearance or an object appearance as perceived by a person, will be as natural, vivid, highly visible, and comfortable as though perceived outdoors in a high-illuminance environment, regardless of scores of various color rendition metric. Light emitted from the light-emitting device illuminates an object such that light measured at a position of the object satisfies specific requirements. A feature of the light-emitting device is that light emitted by the light-emitting device in a main radiant direction satisfies specific requirements.

Abstract: Provided is a semiconductor light emitting device package. The semiconductor light emitting device package includes a substrate, a semiconductor light emitting device on the substrate, and an encapsulation layer which covers the semiconductor light emitting device. The encapsulation layer includes a plurality of ring portions which are disposed sequentially from an edge toward a center of the substrate in plan view, and a center portion which is surrounded by an innermost one of the plurality of ring portions.

Abstract: A light emitting device includes a substrate, a light emitting element provided on the substrate, a first resin layer provided on the substrate to directly cover the light emitting element having a first side surface and a second side surface, and the first side surface and the second side surface differ from each other in inclination angle with respect to the substrate, and a second resin layer provided so as to surround side surfaces of the first resin layer.

Abstract: Display devices with improved display contrast and methods of manufacturing the display devices. Some embodiments include a method of manufacturing a light emitting diode (LED) array. The method includes forming a first mesa area of a first LED and a second mesa area of a second LED, where a trench is defined between the first and second mesa areas. At least a portion of the trench is filled with a non-transparent or substantially non-transparent polymeric material that absorbs light emitted from the first and second LEDs.

Abstract: The present invention relates to a method for providing a reflective coating to a substrate for a light-emitting device, comprising the steps of: providing a substrate having a first surface portion with a first surface material and a second surface portion with a second surface material different from the first surface material; applying a reflective compound configured to attach to said first surface material to form a bond with the substrate in the first surface portion that is stronger than a bond between the reflective compound and the substrate in the second surface portion; curing said reflective compound to form a reflective coating having said bond between the reflective coating and the substrate in the first surface portion; and subjecting said substrate to a mechanical treatment with such an intensity as to remove said reflective coating from said second surface portion while said reflective coating remains on said first surface portion.

Abstract: A light-emitting device comprises a semiconductor light-emitting stack comprising a first connecting layer; and a substrate under the semiconductor light-emitting stack, wherein the substrate comprises a second connecting layer connecting the first connecting layer; wherein the first connecting layer comprises a first region, a first pattern, and a first connecting surface; wherein a difference of a reflectivity between the first pattern and the first region is larger than 20%; wherein the second connecting layer comprises a second region and a side of the first pattern fully contact the second region.

Abstract: A method for obtaining copper arsenic chalcogen derived nanoparticles, including selecting a first precursor material from the group comprising copper, arsenic, antimony, bismuth, and mixtures thereof, selecting a second material from the group comprising sulfur, selenium, tellurium, and mixtures thereof, and then reacting both precursors in a solvent medium at conditions conducive to the formation of copper arsenic chalcogen derived nanoparticles.

Abstract: An energy harvest is disclosed. The disclosed energy harvest includes: a first charging member including a plurality of first protruding parts; and a second charging member including a plurality of second protruding parts arranged between the first protruding parts and including a material different from that of the first protruding parts. When at least one of the first and second charging members moves, side surfaces of the first protruding parts and side surfaces of the second protruding parts come into contact with each other, or gaps between the side surfaces of the first protruding parts and the side surfaces of the second protruding parts are changed. The energy harvest generates electrical energy from the contact or the gap change.

Abstract: An elastic wave resonator includes an interdigital transducer electrode provided on a piezoelectric substrate and including a first electrode layer made of Al or an alloy with Al as its primary component and including a first main surface on a side where the piezoelectric substrate is located and a second main surface on the opposite side from the first main surface. An SH wave is used as a propagated elastic wave. When a resonant frequency of the elastic wave resonator is fr and an anti-resonant frequency of the elastic wave resonator is fa, a minimum value of an absolute value of a distortion component in the first main surface calculated through a two-dimensional finite element method is about 1.4×10?3 or less at a frequency f expressed as: f=fr+0.06×bw, where bw is fa?fr.

Abstract: A device for performing a precision movement comprising a plate composed of piezoelectric material and comprising electrodes which are provided at mutually opposite and preferably parallel planes, are connectable to a controlled voltage source having electrical voltage and in this case bring about a change in the form and/or mass of the plate is characterized in that at least one of the electrodes is designed in an elastic fashion to form a base module.

Abstract: A magnetic piezoelectric composite adjusts magnetic anisotropy strength in a bimetallic member and includes: a piezoelectric layer to produce a strain in response to receipt of a strain voltage; and the bimetallic member disposed on the piezoelectric layer, the bimetallic member including: a plurality of metal layers, such that a second metal layer is interposed between a pair of first metal layers, the bimetallic member being ferromagnetic; and a magnetic anisotropy strength that changes in response to receipt of the strain from the piezoelectric layer.

Abstract: The present disclosure relates to a precursor solution for the preparation of a ceramic of the BZT-?BXT type, where X is selected from Ca, Sn, Mn, and Nb, and ? is a molar fraction selected in the range between 0.10 and 0.90, said solution comprising: 1) at least one barium precursor compound; 2) a precursor compound selected from the group consisting of at least one calcium compound, at least one tin compound, at least one manganese compound, and at least one niobium compound; 3) at least one anhydrous precursor compound of zirconium; 4) at least one anhydrous precursor compound of titanium; 5) a solvent selected from the group consisting of a polyol and mixtures of a polyol and a secondary solvent selected from the group consisting of alcohols, carboxylic acids, ketones, and mixtures thereof; and 6) a chelating agent, as well as method of using the same.