Abstract: A micro-concentrator module includes a cover glass provided with solar cells on one side thereof. The cover glass is adapted to hover above a substrate containing an array of MEMS based reflectors. Springs between the cover glass and the substrate displace the cover glass from a stowed position during transport to a deployed operational position above the substrate. Tethers connecting the cover glass with the substrate limit the displacement of the cover glass to a distance corresponding to the focal length of the reflectors.

Abstract: The present invention relates to a photovoltaic module. A photovoltaic module according to an embodiment of the present invention comprises a solar cell module, a micro-inverter to convert DC power generated by the solar cell module into AC power, a controller to control the micro-inverter's operation, and an interface unit connected to power grid supplying external electrical power and to provide the AC power to the power grid, the controller to control operation of the micro-inverter such that the AC power is matched to the external electrical power flowing into the power grid. The photovoltaic module according to the present invention can provide electrical power generated at solar cell modules through a simple connection to power grid which supplies electrical power to home, reducing consumption of electrical power flowing into home.

Abstract: A solar photovoltaic module remote-access module switch and real-time temperature monitoring system is provided.

Abstract: A grounding spacer is provided. The grounding spacer comprising a circular body having a top surface, a bottom surface, and a central aperture, and a plurality of radially spaced penetration features, wherein at least one of the penetration features has at least a portion thereof extending from the top surface, and wherein at least one of the penetration features has at least a portion thereof extending from the bottom surface.

Abstract: Methods and structures for extracting at least one electric parametric testing from a back contact solar cell are provided.

Abstract: Certain aspects of the present disclosure generally relate to a voltage-controlled oscillator (VCO) that is configurable (e.g., in a dynamic manner) in multiple modes of operation (e.g., low/high-band modes). The VCO may include a resonant circuit coupled to a plurality of switches that may be used to adjust current flow within one or more inductive elements of the resonant circuit. By adjusting the current flow within the inductive elements, an inductance of the resonant circuit may be adjusted, which in turn adjusts a band of the VCO.

Abstract: A dual-frequency-output crystal controlled oscillator includes a crystal resonator, an oscillator circuit, a first output terminal, a second output terminal, and a selection circuit. The crystal resonator includes an input terminal for measurement and an output terminal for measurement. The oscillator circuit is configured to amplify an output of the crystal resonator; a first output terminal configured to output a first frequency based on an output from the oscillator circuit. The second output terminal is configured to output a second frequency lower than the first frequency based on the output from the oscillator circuit. The selection circuit is configured to turn on/off an output of the first frequency. The input terminal for measurement is disposed such that a distance between the input terminal for measurement and the second output terminal is longer than a distance between the input terminal for measurement and the first output terminal.

Abstract: Aspects of this disclosure relate to compensating for dynamic error vector magnitude. A compensation circuit can generate a compensation signal based at least partly on an amount of time that an amplifier, such as a power amplifier, is turned off between successive transmission bursts of the amplifier. For example, the compensation circuit can charge a capacitor based at least partly on an amount of time that the amplifier is turned off between successive transmission bursts and generate the compensation signal based at least partly on an amount of charge stored on the capacitor. A bias circuit can receive the compensation signal, generate a bias signal based at least partly on the compensation signal, and provide the bias signal to the amplifier to bias the amplifier.

Abstract: A power-adjustable RF (radio frequency) output circuit is disclosed, which includes a RF frequency source transformer, wherein: one output end of the RF frequency source transformer is connected with a gate of a power amplifier module, another output end of the RF frequency source transformer is connected with a gate bias voltage control circuit; a source of the power amplifier module is connected with ground; the gate of the power amplifier module is connected with a resistor which is connected with ground, a drain of the power amplifier module is connected with a fixed voltage DC (direct current) power supply and also connected with a RF filtering network for outputting a RF power through the RF filtering network.

Abstract: The single-input single-output two-box polar behavioral model for envelope tracking power amplifiers estimates magnitude and phase of the output signal in separate paths. More specifically, the model is a two-box polar behavioral model using a complex magnitude and phase splitter that feeds a parallel combination of a generalized memory polynomial function and a memoryless polynomial function applied to the input signal's magnitude and phase, respectively. The present model is experimentally validated using a gallium nitride-based envelope tracking power amplifier driven by multi-carrier test signals.

Abstract: A driver circuit for a composite power amplifier configured to operate in at least one Chireix-mode a first and a second sub-amplifier for amplification of an input signal into an output signal is disclosed. An input network of the driver circuit comprises a means configured to provide a first signal which is linearly derivable from the input signal, and a second signal which is non-linearly derivable from the input signal. The input network combines the first signal, at zero degrees phase shift, and the second signal, at 90 degrees phase shift, to obtain a first feeding signal for the first sub-amplifier. Furthermore, the input network combines the first signal, at 180 degrees phase shift, and the second signal, at 90 degrees phase shift, to obtain a second feeding signal for the second sub-amplifier.

Abstract: An inductor-less low noise amplifier (LNA) with high linearity is disclosed. The low noise amplifier includes: an input signal stage receiving an input signal; a first amplifier configured to receive the input signal, generate a first amplification signal by amplifying the received input signal, and output the generated first amplification signal, as a first output signal, to a first output terminal; a second amplifier configured to receive the input signal, generate a second amplification signal by amplifying the received input signal, and output the generated second amplification signal, as a second output signal, to a second output terminal; an output signal stage outputting a superimposition signal obtained by superimposing the first output signal and the second output signal; a first resistor feeding back the superimposition signal to the input signal stage; and a switch connecting/disconnecting between the input signal stage and the output signal stage.

Abstract: Cascode power amplifier with voltage limiter. A power amplification system can include an input transistor having an input transistor gate configured to receive a radio-frequency (RF) signal, an input transistor source coupled to a ground voltage, and an input transistor drain. The power amplification can further include an output transistor having an output transistor drain configured to output an amplified version of the RF signal, an output transistor gate coupled to a bias voltage, and an output transistor source. The power amplification system can further include a high voltage limiter coupled between the output transistor drain and output transistor gate. The high voltage limiter can be configured to prevent a gate-drain voltage of the output transistor from exceeding a high voltage threshold.

Abstract: A power amplifier comprising an amplifying element for amplifying a signal input to the amplifier, a matching network for varying the reactance presented to the output of the amplifying element at the fundamental frequency of the input signal, the matching network being switchable between first and second operating configurations, wherein in the first operating configuration, a net inductive reactance is presented to the output at the fundamental frequency and in the second operating configuration, a net capacitive reactance is presented to the output at the fundamental frequency.

Abstract: An in-line waveguide divider divides power of an incoming high-frequency signal among openings. Amplification boards disposed on a base are provided for respective openings and are each connected in parallel with one another to the in-line waveguide divider. An in-line waveguide combiner includes openings formed correspondingly to the amplification boards, and is connected to the amplification boards. An electrically conductive amplifier cover includes walls formed to provide isolation between circuits of the amplification boards continuously from the in-line waveguide divider to the in-line waveguide combiner, and the entire surface of the amplification boards at the in-line waveguide combiner side is covered with the electrically conductive amplifier cover except openings and openings. Each of the amplification boards includes a waveguide-to-microstrip transition corresponding to the opening, an amplifier element, and a microstrip-to-waveguide transition corresponding to the opening.

Abstract: An example automatic gain control (AGC) circuit includes a base current-gain circuit having a programmable source degeneration resistance responsive to first bits of an AGC code word. The AGC circuit further includes a programmable current-gain circuit, coupled between an input and an output of the base current-gain circuit, having a programmable current source responsive to second bits of the AGC code word. The AGC circuit further includes a bleeder circuit, coupled to the output of the base current-gain circuit, having a programmable current source responsive to logical complements of the second bits of the AGC code word. The AGC circuit further includes a load circuit coupled to the output of the base current-gain circuit.

Abstract: Cascode amplifier having feedback circuits. In some embodiments, an amplifier can include a first transistor and a second transistor arranged in a cascode configuration, with each transistor having a gate. The amplifier can further include a first feedback circuit implemented between an output of the second transistor and the gate of the second transistor. The amplifier can further include a second feedback circuit implemented between the output of the second transistor and the gate of the first transistor.

Abstract: In a power amplifier module for performing slope control of a transmitting signal, a gain variation due to a variation in battery voltage is suppressed while suppressing an increase in circuit size. The power amplifier module includes: a first regulator for outputting a first voltage corresponding to a control voltage for controlling a signal level; a second regulator for outputting a second voltage that rises as a battery voltage drops; a first amplifier supplied with the first voltage as a power-supply voltage to amplify an input signal and output an amplified signal; and a second amplifier for amplifying the amplified signal, wherein the second amplifier includes a first amplification unit supplied with the second voltage as the power-supply voltage to amplify the amplified signal, and a second amplification unit supplied with the battery voltage as the power-supply voltage to amplify the amplified signal.

Abstract: A diplexer module includes substrates, an external connection terminal, a first diplexer including a first transmission filter and a first reception filter, a second diplexer including a second transmission filter and a second reception filter, and a switch. The external connection terminal is connected to the switch, the switch is connected to the first diplexer and the second diplexer, and the first transmission filter, the second transmission filter, the second reception filter, and the first reception filter are aligned in this order when the substrates are seen in plan view from above.

Abstract: There is provided a variable RF filter receiving an input differential radio frequency signal from a differential input terminals (501, 502) and allowing a radio frequency signal around a desired frequency to pass therethrough, wherein first passive mixers (901, . . . , 904) driven by a rectangular wave clock signal having an arbitrarily determined frequency are connected in parallel to a signal line across the differential input terminals (501, 502) and differential output terminals (918, 919), and wherein a load of each of the first passive mixers (901, . . . , 904) is configured by inductors (903, . . . , 906). Further, as a clock signal driving each of the first passive mixers (901, . . . , 904), an odd-multiple-wave Lo signal (for example, a triple-wave Lo signal) is used, the signal having a frequency odd-multiple times (for example, three times) as high as that of the Lo signal which is the fundamental wave of the passing radio frequency signal.

Abstract: Systems, devices, and methods for tunable filters that are configured to support multiple frequency bands, such as within the field of cellular radio communication, can include a first resonator and a second resonator configured to block signals within one or more frequency ranges, and one or more coupling element connected to both the first resonator and the second resonator. The one or more coupling element can be configured to provide low insertion loss within a pass band.

Abstract: A magnetoresistive effect device includes at least one magnetoresistive effect element including a magnetization fixed layer, a spacer layer, and a magnetization free layer, a first port, a second port, a first signal line which is connected to the first port and through which high-frequency current corresponding to a high-frequency signal input into the first port flows, a second signal line, and a direct-current input terminal. The magnetoresistive effect element is arranged so that a high-frequency magnetic field occurring from the first signal line is applied to the magnetization free layer. The magnetoresistive effect element is connected to the second port via the second signal line. The direct-current input terminal is connected to the magnetoresistive effect element.

Abstract: Disclosed is a surface acoustic wave device including a piezoelectric substrate, first and second bus bars formed on the piezoelectric substrate to be opposite each other, a plurality of first inter-digital electrodes that are electrically connected to the first bus bar and extend from the first bus bar toward the second bus bar, and a plurality of second inter-digital electrodes that are electrically connected to the second bus bar and extend from the second bus bar toward the first bus bar, in which the first inter-digital electrodes and the second inter-digital electrodes are alternately arranged.

Abstract: An acoustic resonator includes a substrate having via holes provided therein and having a membrane structure formed on a first surface of the substrate, and a cap accommodating the membrane structure and bonded to the substrate. The cap includes a support block in contact with the membrane structure.

Abstract: A bulk acoustic wave (BAW) device includes a substrate, a reflector on the substrate, a piezoelectric layer on the reflector and including a first opening through which a portion of the reflector is exposed, an electrode layer on the portion of the reflector exposed through the first opening, a passivation layer on the piezoelectric layer and a portion of the electrode layer and including a second opening through which a portion of the electrode layer is exposed, an under-bump metallization layer on the portion of the electrode layer exposed through the second opening and extending over the second opening and the first opening on the passivation layer, and a copper pillar structure on the under-bump metallization layer such that the entirety of the under-bump metallization layer is covered by the copper pillar structure.

Abstract: There are provided an acoustic resonator module, and a method of manufacturing the same. An acoustic resonator module includes a resonating part disposed on a substrate and an inductor electrically connected to the resonating part, and having at least a portion disposed to be spaced apart from the substrate.

Abstract: The present disclosure relates to a high power and low loss acoustic filter that includes a first node, a second node, a first power bypass path, and a first acoustic resonator (AR) path. The first power bypass path extends between the first node and the second node. The first AR path also extends between the first node and the second node, is in parallel with the first power bypass path, and includes at least one first acoustic resonator that form an acoustic resonator network. Herein, the first AR path has a notch filter response. The first power bypass path and the first AR path form a first filter cell that has a band-pass filter response.

Abstract: An elastic wave resonator includes a first, second and third reflectors. The first reflector is between a portion including a first IDT electrode and a third IDT electrode and a portion including a second IDT electrode and a fourth IDT electrode and is shared by the first to fourth IDT electrodes. The second reflector is shared by the first and third IDT electrodes. The third reflector is shared by the second and fourth IDT electrodes. The first and third IDT electrodes share a first common busbar. The second and fourth IDT electrodes share a second common busbar. The first and second common busbars are connected to the first reflector. A first busbar, a second busbar, a third busbar, and a fourth busbar of the respective first to fourth IDT electrodes are electrically connected to each other.

Abstract: An elastic wave resonator including a pair of comb-shaped electrodes and a pair of reflector electrodes formed on a piezoelectric substrate. In one example, the pair of comb-shaped electrodes includes first and second overlapping regions in which electrode fingers of the comb-shaped electrodes interdigitate, the second overlapping region being provided on both outside edges of the first overlapping region in an overlapping width direction, an overlapping width of the first overlapping region being greater than an overlapping width of the second overlapping region, the pair of comb-shaped electrodes being configured to excite a first elastic wave in the first overlapping region and to excite a second elastic wave in the second overlapping region, a frequency of the first elastic wave being higher than a frequency of the second elastic wave.

Abstract: An acoustic wave filter includes a substrate, a first resonator disposed on the substrate, a second resonator disposed on the substrate to be spaced apart from the first resonator, a connector electrically connecting the first and second resonators, and a variable capacitor formed in the connector to tune a pass band frequency of the acoustic wave filter.

Abstract: A compound acoustic wave filter device comprises a support substrate having an including two or more circuit connection pads. An acoustic wave filter includes a piezoelectric filter element and two or more electrodes. The acoustic wave filter is micro-transfer printed onto the support substrate. An electrical conductor electrically connects one or more of the circuit connection pads to one or more of the electrodes.

Abstract: A duplexer includes: a first filter connected between a common terminal and a first terminal and including first series and first parallel resonators; a second filter having a passband higher than that of the first filter, connected between the common terminal and a second terminal, and including second series and second parallel resonators; a first chip including the first series and second parallel resonators mounted thereon; a second chip including the first parallel and second series resonators mounted thereon, wherein when GA and HGB represent temperature coefficients of antiresonant frequencies of the first and second series resonators, and HGA and GB represent temperature coefficients of resonant frequencies of the first and second parallel resonators, a magnitude relationship among GA, GB, HGA, and HGB is none of a relationship in which GA (GB) differs from HGA (HGB), and GB (GA) and HGB (HGA) are located between GA (GB) and HGA (HGB).

Abstract: Provided herein are apparatus and methods for high linearity voltage variable attenuators (VVAs). In certain configurations, a high linearity VVA includes multiple shunt arms or circuits that operate in parallel with one another between a signal node and a first DC voltage, such as ground. Thus, the shunt arms are in shunt with respect to a signal path of the VVA. The multiple shunt arms include a first shunt arm of one or more n-type field effect transistor (NFETs) and a second shunt arm of one or more p-type field effect transistor (PFETs). The gates of the NFETs are controlled using a control voltage, and the gates of the PFETs are controlled using a complementary control voltage that changes inversely with respect to the control voltage.

Abstract: An input/output (I/O) circuit may be provided. The I/O circuit may include an input control circuit and an output control circuit. The input control circuit may be configured to apply a stress to a transmission path based on an input signal while in a test mode and buffer the input signal using a drivability changed by the stress applied to the transmission path to generate first and second transmission signals while in a normal mode after the test mode. The output control circuit may be configured to drive and output an output signal according to the first and second transmission signals based on a test mode signal.

Abstract: A semiconductor module including a semiconductor element, a controller, a cooler, and a temperature sensor are included. The controller is connected to the semiconductor module and controls switching operation of the semiconductor element. The temperature sensor measures a coolant temperature, which is a temperature of the coolant. The controller controls turn-off speed of the semiconductor element based on the coolant temperature. The controller increases the turn-off speed as the coolant temperature rises.

Abstract: A method and apparatus for saving power in integrated circuits is disclosed. An IC includes functional circuit blocks which are not placed into a sleep mode when idle. A power management circuit may monitor the activity levels of the functional circuit blocks not placed into a sleep mode. When the power management circuit detects that an activity level of one of the non-sleep functional circuit blocks is less than a predefined threshold, it reduce the frequency of a clock signal provided thereto by scheduling only one pulse of a clock signal for every N pulses of the full frequency clock signal. The remaining N?1 pulses of the clock signal may be inhibited. If a high priority transaction inbound for the functional circuit block is detected, an inserted pulse of the clock signal may be provided to the functional unit irrespective of when a most recent regular pulse was provided.

Abstract: Technology is described for a relative timed clock gated cell. In one example, the relative timed clock gated cell includes a trigger latch and a data clock latch. The trigger latch includes a clock input coupled to a trigger line for transmitting a trigger signal. The trigger latch is configured to generate a data clock signal on an output. The trigger signal is based on a clock signal. The data clock latch includes a clock input coupled to the output of the trigger latch that latches a data input of the data clock latch based on the data clock signal. Various other computing circuitries and methods are also disclosed.

Abstract: An electronic latch circuit (100) and a multi-phase signal generator (300) are disclosed. The electronic latch circuit (100) comprises an output circuit (105) comprising a first output (X, 106), a second output (Y, 107) and a third output (Z, 108). The electronic latch circuit (100) further comprises an input circuit (101) comprising a first input (A, 102), a second input (B, 103) and a clock signal input (CLK, 104). The electronic latch circuit (100) is configured to change state based on input signals at the inputs (A, B, CLK) of the input circuit (101) and a present state of the output circuit (105). The multi-phase signal generator (300) comprises a plurality N of the electronic latch circuit (100) for generating N phase signals with individual phases. The plurality N of the electronic latch circuit (100) are cascaded with each other.

Abstract: A semiconductor device includes: first through fourth active regions spaced apart from one another; a first gate line disposed to overlap with the first and second active regions, but not with the third and fourth active regions, and to extend in a first direction; a second gate line disposed to overlap with the third and fourth active regions, but not with the first and second active regions, and to extend in the first direction while being spaced apart from the first gate line; and a dummy gate line disposed to overlap with the first through fourth active regions and a field region, to be spaced apart from the first and second gate lines in a second direction, and to extend in the first direction, wherein a signal input to the first or second active region is transmitted to the third or fourth active region.

Abstract: A circuit that stabilizes an output signal of a voltage regulator includes a glitch amplifier, a pulse generator, and a transistor. The glitch amplifier amplifies glitches in the output signal and generates a glitch amplifier output signal. The pulse generator receives the glitch amplifier output signal and generates a control signal. When there is a positive glitch in the output signal and a voltage level of the glitch amplifier output signal is less than a first threshold voltage, the pulse generator deactivates the control signal, which turns off the transistor. When there is a negative glitch in the output signal and the voltage level of the glitch amplifier output signal is greater than a second threshold voltage, the pulse generator activates the control signal, which turns on the transistor and provides a compensating current surge to reduce a voltage droop in the output signal.

Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: There is provided an electronic circuit including a timing signal generation unit for generating a timing signal; a data signal supply unit for synchronizing with the timing signal generated to supply a data signal; a data signal transmission circuit for transmitting the data signal supplied; a timing signal transmission circuit for transmitting the timing signal generated by a circuit having a substantially same delay time as the data signal transmission circuit; and a data holding unit for synchronizing with the timing signal transmitted to hold and output the data signal transmitted. Also, there are provided a solid state image capturing apparatus and a method of controlling the electronic circuit.

Abstract: A semiconductor device that enables a memory size reduction is provided. The semiconductor device includes a converter circuit, a memory circuit, and a detection circuit. The converter circuit has a function of converting first data that includes a digital voltage value to second data that includes an analog current value. The memory circuit has a function of storing third data that includes an analog current value. The detection circuit has a function of generating data that indicates whether the analog current values of the second and third data match.

Abstract: Disclosed herein are a method and an apparatus for generating a random PWM voltage reference signal for driving an inverter, which can more simply generate random position PWM (RPPWM) in which a position of an active vector is changed to achieve the same effect as when a switching frequency is changed.

Abstract: A pulse modulator comprises a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground. One pulse modulator comprises a plurality of stages connected as an induction adder. Each stage includes a plurality of cells and at least some of the cells each include a solid state power switch having a source, a drain, a gate and a separate gate drive connected to ground to control the discharge of a capacitor. In one embodiment the solid state power switch is a power MOSFET.

Abstract: A first stacked RF switch, which operates in one of an ON mode and an OFF mode, and includes a group of RF switching circuits coupled in series between a first RF switch connection node and a second RF switch connection node, is disclosed. The group of RF switching circuits includes a first RF switching circuit, which includes a first switching transistor element coupled between a first source connection node and a first drain connection node, a first source/drain (S/D) bias resistive element coupled across the first switching transistor element, and a first S/D shorting circuit coupled across the first S/D bias resistive element. During the ON mode, the first switching transistor element is ON and the first S/D shorting circuit is ON. During a first interval immediately following a transition from the ON mode to the OFF mode, the first S/D shorting circuit is ON.

Abstract: An overvoltage detector for an RF switch is disclosed. The overvoltage detector is made up of circuitry having a detector output that couples to a controller, a body voltage input that couples to a charge pump, and a body voltage output that couples to a body terminal of the RF switch. The overvoltage detector is configured to detect an overvoltage across the RF switch by monitoring body leakage current flowing between the body voltage input and the body voltage output. Upon detecting body leakage current over a predetermined level, the overvoltage detector generates an overvoltage signal at the detector output to indicate an overvoltage across the RF switch.

Abstract: A switch for controlling a power supply and a method of operating the switch are disclosed. The switch includes a first transistor having a drain and a source connected between VIN and VOUT and a gate connected to be driven to a first voltage that is greater than VIN, an external capacitor operable, when connected to the gate of the first transistor, to control a rise time of VOUT, and a circuit coupled to the gate of the first transistor and to the external capacitor, the circuit connected to couple the external capacitor to the gate of the first transistor responsive to an enable signal turning on and to uncouple the external capacitor from the gate of the first transistor responsive to the voltage on the gate reaching the first voltage.

Abstract: A fault detector for an anti-parallel thyristor includes: a power supply unit configured to supply power to the first and second thyristors; a first current sensor configured to output a first current measurement value that flows through the first thyristor; a second current sensor configured to output a second current measurement value that flows through the second thyristor; and a detector which notifies a fault of a thyristor when the first and second current measurement values satisfy a set fault condition,

Abstract: According to a first aspect of the present disclosure, a power switching circuit is provided, comprising: a bandgap reference circuit configured to receive an input voltage and to generate a reference voltage in response to receiving said input voltage; a supply selection circuit configured to receive at least two supply voltages, to select the highest voltage of said supply voltages and to provide said highest voltage to the bandgap reference circuit. According to a second aspect of the present disclosure, a corresponding method of operating a power switching circuit is conceived.