Patents Issued in December 28, 2017
  • Publication number: 20170371648
    Abstract: During development of an application storing monitoring tools within the source code of the application. During deployment, extracting all monitoring rules from the source code of the application; obtaining information to complete the monitoring rules and customize the monitoring rules to the application which is to be monitored; discarding duplicate monitoring rules; and sending the monitoring rules to a target monitoring tool for configuration of monitoring rules within the application.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Francesco Fabrizi, Andrea Gianfelici, Angelo Littera, Claudio Valant
  • Publication number: 20170371649
    Abstract: In a computer-implemented method for validating interoperability of installed components of a computer system, site data identifying the installed components of the computer system and a version of each of the installed components is received, component dependency data identifying at least one component of the installed components requiring installation of another component of the installed components is received and component interoperability data identifying versions of a component of the installed components that are interoperable with versions of another component of the installed components is received. A version dependency compatibility acyclic graph is generated based at least on the installed components, the component dependency data and component interoperability data. It is determined whether the installed components are interoperable based on the version dependency compatibility acyclic graph.
    Type: Application
    Filed: January 6, 2017
    Publication date: December 28, 2017
    Applicant: VMware, Inc.
    Inventors: Hui Li, Michael Toback
  • Publication number: 20170371650
    Abstract: In a computer-implemented method for performing an upgrade analysis of a computer system, a version dependency compatibility acyclic graph defining component dependency and component version interoperability for a plurality of installed components of the computer system is accessed. Upgradable components of the installed components are determined based on the version dependency compatibility acyclic graph. An upgrade analysis request for an upgradable component of the plurality of installed components is received. Installed components of the plurality of installed components that are impacted by an upgrade of the upgradable component are determined based on the version dependency compatibility acyclic graph.
    Type: Application
    Filed: January 6, 2017
    Publication date: December 28, 2017
    Applicant: VMware, Inc.
    Inventors: Hui Li, Michael Toback
  • Publication number: 20170371651
    Abstract: A static analysis tool configured to determine a significance of static analysis results. The static analysis tool can perform operations that include performing a static analysis of a computer program and generating the static analysis results in response to the performing the static analysis of the computer program. The operations can further include analyzing a description of a result item from the static analysis results, and based on the analyzing the description of the result item, assigning to the result item information from an ontology scheme. The operations can further include determining a significance value for the result item in response to the assigning the information from the ontology scheme and automatically performing an action associated with the result item based on one or more of the information assigned from the ontology scheme or the significance value.
    Type: Application
    Filed: February 15, 2017
    Publication date: December 28, 2017
    Inventors: Fionnuala G. Gunter, Christy L. Norman Perez, Michael T. Strosaker, George C. Wilson
  • Publication number: 20170371652
    Abstract: Software translation quality and efficiency are improved by providing user interface (UI) context for translators. Unicode symbols are used to uniquely tag user-visible strings from the source code and into resource files. Those strings include titles, product names, error messages, strings in images and any other text that may be present on the user interface. Once the ‘pseudo’ resource files are integrated into a build, automation is run to gather screenshots of the application. Image recognition is then used to link screenshots of the UI in which a resource file string appears, such that screenshots will be brought forward and displayed to the translator when working on translating the user-visible strings of the software being localized.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: Yu-Ning Hsu, I-Hsiang Liao, Chih-Yuan Lin, Cheng-Yu Yu
  • Publication number: 20170371653
    Abstract: A method and apparatus for scheduling instructions of a shader program for a graphics processing unit (GPU) with a fixed number of registers. The method and apparatus include computing, via a processing unit (PU), a liveness-based register usage across all basic blocks in the shader program, computing, via the PU, the range of numbers of waves of a plurality of registers for the shader program, assessing the impact of available post-register allocation optimizations, computing, via the PU, the scoring data based on number of waves of the plurality of registers, and computing, via the PU, the number of waves for execution for the plurality of registers.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Robert A. Gottlieb, Christopher L. Reeve, Michael John Bedy
  • Publication number: 20170371654
    Abstract: Described is a system and method for using virtual vector register files. In particular, a graphics processor includes a logic unit, a virtual vector register file coupled to the logic unit, a vector register backing store coupled to the virtual vector register file, and a virtual vector register file controller coupled to the virtual vector register file. The virtual vector register file includes a N deep vector register file and a M deep vector register file, where N is less than M. The virtual vector register file controller performing eviction and allocation between the N deep vector register file, the M deep vector register file and the vector register backing store dependent on at least access requests for certain vector registers.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Applicants: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ljubisa Bajic, Michael Mantor, Syed Zohaib M. Gilani, Rajabali M. Koduri
  • Publication number: 20170371655
    Abstract: A processor includes: a storage unit that stores instructions; a counting unit that specifies an instruction to be decoded by a count value; a decoding unit that decodes an instruction; and a control unit that, when the decoded instruction is a repeat instruction, updates the count value of the counting unit so as to cause repeat target instructions in number corresponding to a designated number of instructions, out of instructions succeeding the repeat instruction, to be repeatedly executed a designated number of repetition times, and generates updated operands being operation objects of the repeat target instructions that are to be executed for the second or later time, and when the repeat target instructions are to be executed for the second or later time, updates operands of the repeat target instructions for use in the second or later time execution, to the generated updated operands and outputs the updated operands.
    Type: Application
    Filed: May 26, 2017
    Publication date: December 28, 2017
    Applicant: FUJITSU LIMITED
    Inventors: Masato Nakagawa, Takumi Maruyama, Shuji Yamamura, Masahiro Kuramoto
  • Publication number: 20170371656
    Abstract: Detection of whether a result of a floating point operation is safe. Characteristics of the result are examined to determine whether the result is safe or potentially unsafe, as defined by the user. An instruction is provided to facilitate detection of safe or potentially unsafe results.
    Type: Application
    Filed: February 28, 2014
    Publication date: December 28, 2017
    Applicant: International Business Machines Corporation
    Inventors: Michael F. Cowlishaw, Shawn D. Lundvall, Ronald M. Smith, SR., Phil C. Yeh
  • Publication number: 20170371657
    Abstract: Systems and methods relate to efficient memory operations. A single instruction multiple data (SIMD) gather operation is implemented with a gather result buffer located within or in close proximity to memory, to receive or gather multiple data elements from multiple orthogonal locations in a memory, and once the gather result buffer is complete, the gathered data is transferred to a processor register. A SIMD copy operation is performed by executing two or more instructions for copying multiple data elements from multiple orthogonal source addresses to corresponding multiple destination addresses within the memory, without an intermediate copy to a processor register. Thus, the memory operations are performed in a background mode without direction by the processor.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Eric Wayne MAHURIN, Jakub Pawal GOLAB, Lucian CODRESCU
  • Publication number: 20170371658
    Abstract: Managing a divided load reorder queue including storing load instruction data for a load instruction in an expanded LRQ entry in the LRQ; launching the load instruction from the expanded LRQ entry; determining that the load instruction is in a finished state; moving a subset of the load instruction data from the expanded LRQ entry to a compact LRQ entry in the LRQ, wherein the compact LRQ entry is smaller than the expanded LRQ entry; and removing the load instruction data from the expanded LRQ entry.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: RICHARD J. EICKEMEYER, DAVID A. HRUSECKY, ELIZABETH A. MCGLONE, BRIAN W. THOMPTO, ALBERT J. VAN NORSTRAND, JR.
  • Publication number: 20170371659
    Abstract: Technology related to load-store queues for block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes issue logic and a load-store buffer. The issue logic can be configured to issue load and store instructions out of program order. Each of the load and store instructions can include an identifier specifying a relative program order of the respective instruction. The load-store buffer can be configured to enqueue the issued load and store instructions; generate hash values for addresses of the load and store instructions; and update a hash data structure using the generated hash values for the issued store instructions as an index of the hash data structure. For the load instructions, the hash data structure can be searched to generate load response data for the load instructions. The generated load response data can be forwarded to an execution unit of the processor.
    Type: Application
    Filed: July 31, 2016
    Publication date: December 28, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Aaron L. Smith, Jan S. Gray
  • Publication number: 20170371660
    Abstract: Technology related to load-store queues for block-based processor architectures is disclosed. In one example of the disclosed technology, a processor includes multiple processor cores and a load-store queue. Each processor core is configured to execute an instruction block including load and store instructions. The instruction block can be identified by a block identifier, and each of the load and store instructions is identified with a load-store identifier. The load-store queue can be configured to enqueue load and store instructions from the processor cores in a buffer indexed based on a function of the block identifier and the load-store identifier. The buffer can be searched for store instructions having a target address matching a target address of a load instruction received from a first processor core. Load response data can be returned for the received load instruction to the first processor core based on the search of the buffer.
    Type: Application
    Filed: July 31, 2016
    Publication date: December 28, 2017
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Aaron L. Smith, Jan S. Gray
  • Publication number: 20170371661
    Abstract: A method and apparatus for implementing power modes in microcontrollers (MCUs) using power profiles. In one embodiment of the method, a central processing unit (CPU) of the MCU executes a first instruction for calling a subroutine stored in a memory of the MCU, wherein the first instruction comprises a first parameter to be passed to the subroutine. Thereafter the CPU writes a first value to a first special function register (SFR) of the MCU in response to executing the first instruction, wherein the first value is related to the first parameter. The MCU operates in a first power mode in response to the CPU writing the first value to the first SFR. The CPU also executes a second instruction for calling the subroutine, wherein the second instruction comprises a second parameter to be passed to the subroutine. In response the CPU writes a second value to a second SFR of the MCU in response to executing the second instruction, wherein the second value is related to the second parameter.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventor: Dale Sparling
  • Publication number: 20170371662
    Abstract: A mechanism is described for facilitating extension of register files in computing environments. A method of embodiments, as described herein, includes facilitating, inside an extended register file, performance of one or more tasks relating to an instruction, where the one or more tasks are performed by an extension mechanism being hosted inside the extended register file of a computing device.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventor: Tomas G. AKENINE-MOLLER
  • Publication number: 20170371663
    Abstract: Example implementations relate to global capabilities transferrable across node boundaries. For example, in an implementation, a switch that routes traffic between a node and global memory may receive an instruction from the node. The switch may recognize that data referenced by the instruction is a global capability, and the switch may process that global capability accordingly.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Dejan S Milojicic, Paolo Faraboschi, Chris I Dalton
  • Publication number: 20170371664
    Abstract: A program information generation system includes circuitry configured to acquire a program and operation information, the program including a plurality of instruction codes including a start instruction code for starting a critical section and an end instruction code for ending the critical section, the operation information indicating an execution order of the plurality of instruction codes; identify the instruction code included in a first section corresponding to the critical section from the operation information, on the basis of the start instruction code, the end instruction code, and the operation information; determine a second section, corresponding to the first section, within the program on the basis of the instruction code included in the first section; and generate classification information for allowing specification of the instruction code included in the critical section or the instruction code included in a non-critical section, on the basis of the second section.
    Type: Application
    Filed: February 23, 2017
    Publication date: December 28, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mayuko KOEZUKA, Hidenori Matsuzaki, Akira Kuroda, Nobuaki Tojo
  • Publication number: 20170371665
    Abstract: Systems, apparatuses, and methods for adjusting group sizes to match a processor lane width are described. In early iterations of an algorithm, a processor partitions a dataset into groups of data points which are integer multiples of the processing lane width of the processor. For example, when performing a K-means clustering algorithm, the processor determines that a first plurality of data points belong to a first group during a given iteration. If the first plurality of data points is not an integer multiple of the number of processing lanes, then the processor reassigns a first number of data points from the first plurality of data points to one or more other groups. The processor then performs the next iteration with these first number of data points assigned to other groups even though the first number of data points actually meets the algorithmic criteria for belonging to the first group.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Mauricio Breternitz, Mayank Daga
  • Publication number: 20170371666
    Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Michael K. Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Publication number: 20170371667
    Abstract: A processor including a physical register file, a rename table, mapping logic, size tracking logic, and merge logic. The rename table maps an architectural register with a larger index and a smaller index. The mapping logic detects a partial write instruction that specifies an architectural register that is already identified by an entry of the rename table mapped to a second physical register allocated for a larger write operation, and includes an index for the allocated register for the partial write instruction into the smaller index location of the entry. The size tracking logic provides a merge indication for the partial write instruction if the write size of the previous write instruction is larger. The merge logic merges the result of the partial write instruction with the second physical register during retirement of the partial write instruction.
    Type: Application
    Filed: August 25, 2016
    Publication date: December 28, 2017
    Inventor: XIAOLONG FEI
  • Publication number: 20170371668
    Abstract: Embodiments include method, systems and computer program products for variable branch target buffer line size for compression. In some embodiments, a branch target buffer (BTB) congruence class for a line of a first parent array of a BTB may be determined. A threshold indicative of a maximum number branches to be stored in the line may be set. A branch may be received to store in the line of the first parent array. A determination may be made that storing the branch in the line would exceed the threshold and the line can be responsively split into an even half line and an odd half line.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: James J. Bonanno, Michael J. Cadigan, JR., Brian R. Prasky
  • Publication number: 20170371669
    Abstract: A method for predicting a fetch address of a next instruction to be fetched includes selecting, at a processor, a first way identifier or a second way identifier as a way pointer based on an active fetch address and historical prediction data. A first predictor table includes a first entry having the first way identifier and a second predictor table includes a second entry having the second way identifier. The method also includes selecting a first or second fetch address as a predicted fetch address based on the way pointer. A target table includes a first way storing the first fetch address and a second way storing the second fetch address. The first way and the second way are associated with the active fetch address. The first fetch address is associated with the first way identifier and the second fetch address is associated with the second way identifier.
    Type: Application
    Filed: June 24, 2016
    Publication date: December 28, 2017
    Inventors: Anil Krishna, Gregory Wright
  • Publication number: 20170371670
    Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction comprising a first instruction address; searching, by the processor, an index accelerator predictor one time for the stream; determining, by the processor, a prediction for a taken branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; observing a plurality of taken branches from the exit accelerator predictor; maintaining frequency information based on the observed taken branches; determining, based on the frequency information, an updated prediction of the observed plurality of taken branches; and updating, by the processor, the index accelerator predictor with the the updated prediction.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: James J. Bonanno, Michael J. Cadigan, JR., Adam B. Collura, Daniel Lipetz
  • Publication number: 20170371671
    Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction including a first instruction address. The computer-implemented method further includes searching, by the processor, a stream-based index accelerator predictor one time for the stream; determining, by the processor, a prediction for a branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; and updating, by the processor, a stream-based index accelerator predictor with information indicative of the prediction.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Inventors: James J. Bonanno, Michael J. Cadigan, JR., Adam B. Collura, Christian Jacobi, Daniel Lipetz, Anthony Saporito
  • Publication number: 20170371672
    Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction comprising a first instruction address; searching, by the processor, an index accelerator predictor one time for the stream; determining, by the processor, a prediction for a taken branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; observing a plurality of taken branches from the exit accelerator predictor; maintaining frequency information based on the observed taken branches; determining, based on the frequency information, an updated prediction of the observed plurality of taken branches; and updating, by the processor, the index accelerator predictor with the the updated prediction.
    Type: Application
    Filed: March 1, 2017
    Publication date: December 28, 2017
    Inventors: James J. Bonanno, Michael J. Cadigan, JR., Adam B. Collura, Daniel Lipetz
  • Publication number: 20170371673
    Abstract: A processor including physical registers, a reorder buffer, a master free list, a slave free list, a master recycle circuit, and a slave recycle circuit. The reorder buffer includes instruction entries in which each entry stores physical register indexes for recycling physical registers. The reorder buffer retires up to N instructions in each processor cycle. Each master and slave free list includes N input ports and stores physical register indexes, in which the master free list stores indexes of physical registers to be allocated to instructions being issued. When an instruction is retired, the master recycle circuit routes a first physical register index stored in an instruction entry of the instruction to an input port of the master free list, and the slave recycle circuit routes a second physical register index stored in the instruction entry of the instruction to an input port of the slave free list.
    Type: Application
    Filed: August 12, 2016
    Publication date: December 28, 2017
    Inventor: XIAOLONG FEI
  • Publication number: 20170371674
    Abstract: An apparatus includes: a cache to retain an instruction; an instruction-control circuit to read out the instruction from the cache; and an instruction-execution circuit to execute the instruction read out from the cache, wherein the cache includes: a pipeline processing circuit including a plurality of selection stages in each of which, among a plurality of requests for causing the cache to operate, a request having a priority level higher than priority levels of other requests is outputted to a next stage and a plurality of processing stages in each of which processing based on a request outputted from a last stage among the plurality of selection stages is sequentially executed; and a cache-control circuit to input a request received from the instruction-control circuit to the selection stage in which processing order of the processing stage is reception order of the request.
    Type: Application
    Filed: June 7, 2017
    Publication date: December 28, 2017
    Applicant: FUJITSU LIMITED
    Inventor: Yuji Shirahige
  • Publication number: 20170371675
    Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for implementing an iteration synchronization construct (ISC) for a parallel pipeline. The apparatus may initialize a first instance of the ISC for a first stage iteration of a first parallel stage of the parallel pipeline and a second instance of the ISC for a second stage iteration of the first parallel stage of the parallel pipeline. The apparatus may determine whether an execution control value is specified for the first stage iteration, and add a first execution control edge to the parallel pipeline after determining that an execution control value is specified for the first stage iteration. The apparatus may determine whether execution of the first stage iteration is complete and send a ready signal from the first instance of the ISC to the second instance if the ISC after determining that execution of the first stage iteration completed.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Weiwei Chen, Tushar Kumar
  • Publication number: 20170371676
    Abstract: A data processing apparatus is provided comprising a front-end interface electronically coupled to a main processor. The front-end interface is configured to receive data stored in a repository, in particular an external storage and/or a network, determine whether the data is a single-access data or a multiple-access data by analyzing an access parameter designating the data, route the multiple-access data for processing by the main processor, and route the single-access data for pre-processing by the front-end interface and routing results of the pre-processing to the main processor.
    Type: Application
    Filed: September 11, 2017
    Publication date: December 28, 2017
    Applicant: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Uri WEISER, Tal HOROWITZ, Jintang WANG
  • Publication number: 20170371677
    Abstract: A graph-based program specification includes components, at least one having at least one input port for receiving a collection of data elements, or at least one collection type output port for providing a collection of data elements. Executing a program specified by the graph-based program specification at a computing node, includes: receiving data elements of a first collection into a first storage in a first order via a link connected to a collection type output port of a first component and an input port of a second component, and invoking a plurality of instances of a task corresponding to the second component to process data elements of the first collection, including retrieving the data elements from the first storage in a second order, without blocking invocation of any of the instances until after any particular instance completes processing one or more data elements.
    Type: Application
    Filed: August 24, 2017
    Publication date: December 28, 2017
    Inventors: Craig W. Stanfill, Richard Shapiro, Stephen A. Kukolich, Joseph Skeffington Wholey, III
  • Publication number: 20170371678
    Abstract: The present disclosure belongs to the field of computer technologies, and discloses a method and apparatus for running a game client. The method includes: receiving a startup instruction of a target game client, and sending a startup request corresponding to the target game client to a server; receiving startup data, sent by the server, corresponding to the target game client, and starting, based on the startup data, the target game client; sending, when a preset data obtaining condition of a target game unit in the corresponding target game client is satisfied, a data request carrying a unit identifier of the target game unit to the server; and receiving operating data of the target game unit sent by the server, and running, based on the operating data, the target game unit. By means of the present disclosure, storage resources of a mobile terminal can be saved.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Inventor: Minghui WANG
  • Publication number: 20170371679
    Abstract: A method for managing an initiation of a computing system. In an embodiment, the method includes a computer processor detecting that a first computing system receives a request to initiate a second computing system. The method further includes accessing a table that includes information associated with a plurality of storage entities that include bootable OS images, where the plurality of storage entities are included in at least one storage system. The method further includes determining a first storage entity that includes a corresponding instance of a first bootable OS image of the requested second computing system. The method further includes initiating the requested second computing system based, at least in part, on the instance of the bootable OS image of the first storage entity.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 28, 2017
    Inventors: Sudhir Chandrasekhar, Syed A. Rehman
  • Publication number: 20170371680
    Abstract: A method for managing an initiation of a computing system. In an embodiment, the method includes a computer processor detecting that a first computing system receives a request to initiate a second computing system. The method further includes accessing a table that includes information associated with a plurality of storage entities that include bootable OS images, where the plurality of storage entities are included in at least one storage system. The method further includes determining a first storage entity that includes a corresponding instance of a first bootable OS image of the requested second computing system. The method further includes initiating the requested second computing system based, at least in part, on the instance of the bootable OS image of the first storage entity.
    Type: Application
    Filed: July 30, 2017
    Publication date: December 28, 2017
    Inventors: Sudhir Chandrasekhar, Syed A. Rehman
  • Publication number: 20170371681
    Abstract: Systems and methods for using distributed Universal Serial Bus (USB) host drivers are disclosed. In one aspect, USB packet processing that was historically done on an application processor is moved to a distributed USB driver running in parallel on a low-power processor such as a digital signal processor (DSP). While a DSP is particularly contemplated, other processors may also be used. Further, a communication path is provided from the low-power processor to USB hardware that bypasses the application processor. Bypassing the application processor in this fashion allows the application processor to remain in a sleep mode for longer periods of time instead of processing digital data received from the low-power processor or the USB hardware. Further, by bypassing the application processor, latency is reduced, which improves the listener experience.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 28, 2017
    Inventors: Ameya Kulkarni, Andrew Cheung, Jay Yu Jae Choi, Daniel Hyongkyu Kim, Hemant Kumar, Vamsi Krishna Samavedam
  • Publication number: 20170371682
    Abstract: A printer driver and an advanced UI application are associated with each other during installation, and the advanced UI application is activated in a different process using a COM when the printer driver is called.
    Type: Application
    Filed: September 7, 2017
    Publication date: December 28, 2017
    Inventor: Akihiro Mitsui
  • Publication number: 20170371683
    Abstract: Methods and devices for provisioning a hyper-converged infrastructure of bare metal systems are disclosed herein. Two fabric elements are configured in a master-slave arrangement to ensure high availability. ONIE capable fabric elements may be pre-installed with an operating system as firmware to run open network operating systems, such as Linux. The Linux operating system includes a KVM hypervisor to run virtual machines. An operating system of the virtual machines can access an external network by creating a bridge between switch management ports and a virtual network interface. New node elements may be added by connecting the network ports of the new node element to the fabric elements and booting the new node element in a network/PXE boot mode. The new node element obtains an IP address from a DHCP server and boots an image downloaded from a PXE server.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 28, 2017
    Inventors: Kishore K.R. DEVIREDDY, John J. Glen, Venkatanarasimhan K. RAMAKRISHNAN, Justin R. UNGER
  • Publication number: 20170371684
    Abstract: A pin control method and device are provided. The method may be applied to a first chip and the first chip includes: a sleep pin connected with a wakeup pin on a second chip, a Request To Send (RTS) pin connected with a Clear To Send (CTS) pin on the second chip, a Receive Data (RXD) pin connected with a Transmit Data (TXD) pin on the second chip. The method includes: receiving, by the sleep pin, a data sending signal sent by the second chip; setting the RTS pin into an effective state according to the data sending signal; receiving, by the RXD pin, data sent by the second chip, the RXD pin being in the effective state when the RTS pin is in the effective state; receiving, by the sleep pin, a transmission completion signal sent by the second chip; setting the RTS pin into an ineffective state according to the transmission completion signal; and determining, according to a current running condition, whether to enter a sleep state.
    Type: Application
    Filed: June 27, 2017
    Publication date: December 28, 2017
    Inventors: Kangxi TAN, Li HE, Jun ZHANG
  • Publication number: 20170371685
    Abstract: The present invention has an object of providing a user interface execution apparatus and a user interface designing apparatus which can estimate the maximum size of a storage area for storing data to be prefetched when a user interface is designed and can present updated data to the user even when the prefetched data is updated after the prefetch. A user interface execution apparatus in the present invention includes a processor to execute a program; and a memory to store the program which, when executed by the processor, performs processes of: transitioning a state of the user interface execution apparatus; issuing a prefetch request for data; storing the data; generating the code from an interface definition and a state transition definition; and selecting, before transitioning the state, data to be prefetched based on a difference between a data obtaining interface to be used in a state before the transitioning and a data obtaining interface to be used in a state after the transitioning.
    Type: Application
    Filed: February 27, 2015
    Publication date: December 28, 2017
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kohei TANAKA, Yoshiaki KITAMURA, Akira TOYOOKA, Mitsuo SHIMOTANI, Yukio GOTO
  • Publication number: 20170371686
    Abstract: An information processing device may read, from a shared storing area, first identification information indicating K pieces of first applications that are already installed. The information processing device may display first screen on the display. The information processing device may cause an operating system to display the K pieces of first images in the first screen. Each of K pieces of link information may be associated with a corresponding one of the K pieces of first images. When any one of the K pieces of first images receives an input operation, the operating system may activate the corresponding first application indicated by the link information associated with the first image that receives the input operation.
    Type: Application
    Filed: June 22, 2017
    Publication date: December 28, 2017
    Inventors: Takeshi SHIOTANI, Susumu FUJIWARA
  • Publication number: 20170371687
    Abstract: Techniques are disclosed for providing dynamic globalization enablement for developing an application during software development. A globalization development operation information system (GDOIS) retrieves source code for the application, which is assigned to support specified globalization features. The GDOIS evaluates the source code for each of the plurality of specified globalization features. Upon determining that the source code does not include at least a first specified globalization feature, the GDOIS identifies an application programming interface (API) associated with the feature. The GDOIS inserts source code associated with the API into the source code for the application.
    Type: Application
    Filed: January 24, 2017
    Publication date: December 28, 2017
    Inventors: Syed HAIDERZAIDI, Su LIU, Boyi By TZEN, Cheng XU
  • Publication number: 20170371688
    Abstract: An electronic device and method are disclosed. The electronic device includes a communication unit, a display, a memory and a processor. The processor implements the method, including analyzing activity of an application to identify at least one function of the application added, deleted or altered by an update to the application, and controlling the display to display at least one item selectable to provide additional information corresponding to the identified at least one new function.
    Type: Application
    Filed: May 30, 2017
    Publication date: December 28, 2017
    Inventors: Joohyun KIM, Hyoungjoon PARK
  • Publication number: 20170371689
    Abstract: Various embodiments are generally directed to the provision and use of various hardware and software components of a computing device to monitor the state of layered virtual machine (VM) monitoring software components. An apparatus includes a first processor element; and logic to receive an indication that a first timer has reached an end of a first period of time, monitor execution of a VMM (virtual machine monitor) watcher by a second processor element, determine whether the second processor element completes execution of the VMM watcher to verify integrity of a VMM before a second timer reaches an end of a second period of time, and transmit an indication of the determination to a computing device. Other embodiments are described and claimed.
    Type: Application
    Filed: July 31, 2017
    Publication date: December 28, 2017
    Applicant: INTEL CORPORATION
    Inventors: MAHESH S. NATU, SHAMANNA M. DATTA
  • Publication number: 20170371690
    Abstract: Computing systems, database systems, and related methods are provided for supporting dynamic validation workflows. One exemplary method involves a server of a database system receiving a graphical representation of a validation process from a client device coupled to a network, converting the graphical representation of the validation process into validation code, and storing the validation code at the database system in association with a database object type. Thereafter, the validation process is performed with respect to an instance of the database object type using the validation code in response to an action with respect to the instance of the database object type in a database of the database system. The action triggering the validation process can be based on user-configurable triggering criteria, and the validation process may generate user-configurable notifications based on one or more field values of the database object instance.
    Type: Application
    Filed: September 11, 2017
    Publication date: December 28, 2017
    Applicant: salesforce.com, inc.
    Inventor: SAMUEL WILLIAM BAILEY
  • Publication number: 20170371691
    Abstract: A hypervisor-exchange process includes: suspending, by an “old” hypervisor, resident virtual machines; exchanging the old hypervisor for a new hypervisor, and resuming, by the new hypervisor, the resident virtual machines. The suspending can include “in-memory” suspension of the virtual machines until the virtual machines are resumed by the new hypervisor. Thus, there is no need to load the virtual machines from storage prior to the resuming. As a result, any interruption of the virtual machines is minimized. In some embodiments, the resident virtual machines are migrated onto one or more host virtual machines to reduce the number of virtual machines being suspended.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 28, 2017
    Applicant: VMware, Inc.
    Inventors: Mukund Gunti, Vishnu Sekhar, Rajesh Venkatasubramanian
  • Publication number: 20170371692
    Abstract: Systems and methods for Virtual Network Function (VNF) service chain optimization include, responsive to a request, determining placement for one or more VNFs in a VNF service chain based on a lowest cost determination; configuring at least one programmable region of acceleration hardware for at least one VNF of the one or more VNFs; and activating the VNF service chain. The lowest cost determination can be based on a service chain cost model that assigns costs based on connectivity between switching elements and between hops between sites. The activating can include a Make-Before-Break (MBB) operation in a network to minimize service interruption of the VNF service chain.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 28, 2017
    Inventors: Matthew W. CONNOLLY, Aung HTAY
  • Publication number: 20170371693
    Abstract: One example relates to a computer system that includes a plurality of host computers each executing a hypervisor. The computer system further includes a virtualization manager having an application programming interface (API) configured to manage the hypervisor on each of the plurality of host computers, the virtualization manager configured to create a virtual container host within a resource pool that spans the plurality of host computers. The computer system further includes a plurality of container virtual machines (VMs) in the virtual container host configured to consume resources in the resource pool. The computer system further includes a daemon appliance executing in the virtual container host configured to invoke the API of the virtualization manager to manage the plurality of container VMs in response to commands from one or more clients.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventors: Benjamin J. CORRIE, George HICKEN, Aaron SWEEMER, Zee YANG
  • Publication number: 20170371694
    Abstract: An accelerated processing unit includes a first processing unit configured to implement one or more virtual machines and a second processing unit configured to implement one or more acceleration modules. The one or more virtual machines are configured to provide information identifying a task or data to the one or more acceleration modules via first queues. The one or more acceleration modules are configured to provide information identifying results of an operation performed on the task or data to the one or more virtual machines via one or more second queues.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Inventor: Seong Hwan Kim
  • Publication number: 20170371695
    Abstract: Examples may include techniques for persistent memory virtualization. Persistent memory maintained at one or more memory devices coupled with a host computing device may be allocated and assigned to a virtual machine (VM) hosted by the host computing device. The allocated persistent memory based on a file based virtual memory to be used by the VM. An extended page table (EPT) may be generated to map physical memory pages of the one or more memory devices to virtual logical blocks of the file based virtual memory. Elements of the VM then enumerate a presence of the assigned allocated persistent memory, create a virtual disk abstraction for the file based virtual memory and use the EPT to directly access the assigned allocated persistent memory.
    Type: Application
    Filed: June 27, 2016
    Publication date: December 28, 2017
    Applicant: Intel Corporation
    Inventors: Vivekananthan Sanjeepan, Leena K. Puthiyedath, Chandan Apsangi, Nikhil Talpallikar, Abinash K. Barik
  • Publication number: 20170371696
    Abstract: A method for migrating a virtual machine (VM) includes establishing a first connection to a first cloud computing system executing a first VM, and establishing a second connection to a second cloud computing system managed by a second cloud provider, which is different form the first cloud provider. The method further includes instantiating a second VM designated as a destination VM in the second cloud computing system, and installing a migration agent on each of the first VM and the second VM. The migration agents execute a migration process of the first VM to the second VM by (1) iteratively copying guest data from the first VM to the second VM until a switchover criteria of the migration operation is met, and (2) copying a remainder of guest data from the first VM to the second VM when the switchover criteria is met.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Nathan L. PRZIBOROWSKI, Gabriel TARASUK-LEVIN, Arunachalam RAMANATHAN, Prachetaa RAGHAVAN, Benjamin Yun LIANG, Haripriya RAJAGOPAL, Longhao SHU
  • Publication number: 20170371697
    Abstract: A test system for testing a particular computer of a particular computer system in a test network includes: a simulation server configured to emulate a test object; and a control entity for controlling the simulation server, wherein the control entity is configured to instruct the simulation server to generate a virtual test object for emulating the test object, and to instruct a test entity to test the virtual test object generated by the simulation server.
    Type: Application
    Filed: December 4, 2015
    Publication date: December 28, 2017
    Inventors: Markus Eggert, Daniel Hauenstein