Abstract: A parallel execution method, system, and non-transitory computer readable medium not maintaining a cache coherence, include creating a continuum, the continuum being a construct that holds data structures, giving a view to the continuum, the view being a descriptor that provides access rights and properties for the continuum, and performing a task associated with an execution sequence, the task holding the view to the continuum that the execution sequence is accessing.

Abstract: A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries, where each entry stores a memory block in association with a virtual address and a code representing at least one page size of a memory page on which the memory block is located. The managing includes: receiving a translation lookaside buffer invalidation instruction for invalidating at least one translation lookaside buffer entry in the translation lookaside buffer, where the translation lookaside buffer invalidation instruction includes at least one invalid virtual address; comparing selected bits of the invalid virtual address with selected bits of each of a plurality of virtual addresses associated with respective entries in the virtual-address cache module, based on the codes; and invalidating one or more entries in the virtual-address cache module based on the comparing.

Abstract: Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value; mapping the logical address to a first physical address identical to an interval value when the logical address is identical to the round value; mapping the logical address to a second physical address corresponding to a value obtained by subtracting the round value from the logical address when the logical address is different from the round value; and adjusting a mapping value of the logical address to the second physical address to a value obtained by subtracting one from the second physical address when the second physical address is less than or equal to the interval value.

Abstract: An information processing apparatus includes a memory and a processor coupled to the memory. The memory is configured to store device connection information indicating a connection destination device coupled to a first device among a plurality of devices included in a communication network. The processor is configured to: search physical address learning information of the connection destination device in preference to physical address learning information of search target devices other than the connection destination device on basis of the device connection information. The physical address learning information of a specific device includes physical addresses learned for every port of the specific device. The search target devices are the plurality of devices other than the first device. The processor is configured to: obtain a connection destination port coupled to a first port of the first device on basis of a result of the search.

Abstract: One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a physical memory, and the microcontroller is configured to perform one or more virtual memory operations associated with the physical memory and the page table. In operation, the microcontroller receives a page fault generated by the MMU in response to an invalid memory access via a virtual memory address. To remedy such a page fault, the microcontroller performs actions to map the virtual memory address to an appropriate location in the physical memory. By contrast, in prior-art systems, a fault handler would typically remedy the page fault. Advantageously, because the microcontroller executes these tasks locally with respect to the MMU and the physical memory, latency associated with remedying page faults may be decreased. Consequently, overall system performance may be increased.

Abstract: An apparatus and method for efficient guest EPT manipulation. For example, one embodiment of a apparatus comprises: a hypervisor to create extended page table (EPT) mappings between a guest physical address (GPA) space and a host physical address (HPA) space; the hypervisor to create an EPT edit table and populate the EPT edit table with information related to permitted mappings between the GPA space and HPA space; a guest to read the EPT edit table to determine information related to the permitted mappings between the GPA space and HPA space, the guest to use the information to map one or more pages in the GPA space to one or more pages in the HPA space.

Abstract: A method for writing multiple copies into a storage device includes receiving a first write data request that includes an identity (ID) of a first logical storage unit, target data, and a logical block address (LBA) of the first logical storage unit, determining that data stored in storage space corresponding to the LBA of the first logical storage unit is not accessed by another data access request, writing the target data into the storage space corresponding to the LBA of the first logical storage unit, generating a second write data request that includes an ID of a second logical storage unit, the target data, and an LBA of the second logical storage unit, and writing the target data into storage space corresponding to the LBA of the second logical storage unit.

Abstract: A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus may also be used in the areas of near-memory and in-memory computing, where near-memory or in-memory compute units may need to share a host CPU's virtual address space. Metadata is associated with page table entries (PTEs) and mechanisms use the metadata to limit the number of processing elements that participate in a TLB shootdown operation.

Abstract: A method and apparatus of a device that reads and writes a plurality of counters is described. In an exemplary embodiment, a device receives plurality labels that correspond to the plurality of counters. The plurality of counters is stored in a shared memory table in the shared memory of the device. In addition, a writer writes counter data for each of the plurality of counters to the shared memory table. For each of the plurality of labels, the device performs a lookup of that label for a memory reference to a corresponding counter that is one of the plurality of counters and retrieves the memory reference for the corresponding counter. The device further reads the counter data for plurality of counters using the plurality of memory references. The device additionally sends the counter data to the client.

Abstract: The present embodiments provide a cache data determining method and apparatus, and pertain to the field of computer technologies. The method includes: acquiring a data identifier of read cache miss data; selecting, based on the acquired data identifier, a data identifier of to-be-determined data; recording data identifiers by groups; collecting statistics on quantities of occurrence times, in each group, of the data identifiers; and selecting target to-be-determined data according to the quantities of occurrence times, and determining the target to-be-determined data as cache miss data to be written into a cache memory. Data identifiers are recorded by groups, and after statistics on quantities of occurrence times, in each group, of the data identifiers is collected, target to-be-determined data is selected according to the quantities of occurrence times, and the target to-be-determined data is determined as cache miss data to be written into a cache memory.

Abstract: In one example in accordance with the present disclosure, a method may include retrieving, at a memory management unit (MMU), encrypted data from a memory via direct memory access and determining, at the MMU, a peripheral that is the intended recipient of the encrypted data. The method may also include accessing an application key used for transmission between an application and the peripheral, wherein the application key originates from the application and decrypting, at the MMU, the encrypted data using the application key and transmitting the decrypted data to the peripheral.

Abstract: Encrypted memory access using page table attributes is disclosed. One example is a memory system including a memory controller at a memory interface. The memory controller includes an encryptor to control a plurality of memory access keys respectively associated with memory regions, where each memory region is allocated to a respective client, and an access manager to receive an access request from a client, the access request including a client access key to access a memory element. The access manager looks up a memory access key from a page table attribute associated with a physical address of the memory element, and determines if the access request is valid by comparing the client access key with the memory access key associated with the memory region that includes the memory element. Based on the determination and a mode of operation, the access manager provides a response to the access request.

Abstract: The present application discloses a method and a system for transmitting data. A method embodiment comprises: acquiring a most recent shared memory block index of a shared memory segment by a data receiver, the shared memory segment being used by a data transmitter and the data receiver to transmit data; deciding whether the most recent shared memory block index is consistent with a shared memory block index corresponding to data recently read by the data receiver; and determining, according to the decision, whether to read the data in the shared memory block corresponding to the most recent shared memory block index.

Abstract: A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be analyzed by a state machine engine as the device. The state machine engine includes configurable elements configured to analyze the at least a portion of a data stream and to selectively output the result of the analysis. Additionally, the instruction buffer is configured to receive the indications as part of a direct memory access (DMA) transfer.

Abstract: A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC comprises a first memory controller, a second memory controller, and a symmetric memory channel interleaver. The first memory controller is electrically coupled to a first DRAM module via a first memory bus. The second memory controller is electrically coupled to a second DRAM module and a third DRAM module via a second memory bus. The symmetric memory channel interleaver is configured to uniformly distribute DRAM traffic to the first memory controller and the second memory controller. The first memory controller provides a first interleaved channel to the first DRAM module via the first memory bus. The second memory controller provides a second interleaved channel to the second DRAM module via upper address bits on the second memory bus.

Abstract: A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.

Abstract: Embodiments presented herein provide for hot swappable connections to various storage devices. In one embodiment, a storage controller includes an interface operable to connect to at least one of a storage device and a midplane connected to a plurality of Non Volatile Memory Express (NVMe) storage devices. The storage controller also includes a processor operable to detect when the interface is connected to the mid-plane, to determine that the NVMe storage devices each have a x4 NVMe connection, and to communicate sideband signaling, including a reference clock, to the NVMe storage devices through the midplane via Inter-Integrated Circuit (I2C) upon determining that the NVMe storage devices each have a x4 NVMe connection.

Abstract: Aspects of the disclosure provide an integrated circuit (IC) chip that includes interface circuits and a control circuit. The interface circuits is configured to interface the IC chip to buses that couple the IC chip with a memory chip, to drive signals onto the buses for transmission to the memory chip and to receive signals that are transmitted on the buses from the memory chip. The control circuit is configured to receive a ratio change of transmission rates for command signals and data signals, control the interface circuits to transmit information signals to the memory chip to inform the ratio change, configure the interface circuits according to the ratio change, and allow the interface circuits to start transmit/receive signals according to the ratio change at a time.

Abstract: A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in response to the processor executing the program instructions to perform issuing, via an operating system running on the computing system, a command indicating a request to perform an I/O transaction requiring a translation entry. A host bridge monitors a total data length of the address translation entry to be transferred during the I/O transaction. An address translation entry is selected from an address translation table, loaded into the address translation cache, and data corresponding to the I/O transaction is transferred using the selected address translation entry. The host bridge automatically purges the selected address translation entry from the address translation cache in response to determining the transferred amount of data matches the total data length for the address translation entry.

Abstract: A semiconductor apparatus may include an interface circuit. The interface circuit may sense level variations of a first signal and a second signal. The interface circuit may generate first and second output signals by variably delaying the first and second signals depending on a sensing result. The interface circuit may transmit the first and second output signals to first and second signal transmission lines which are adjacent to each other.

Abstract: One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and generates a plurality of pattern detected signals. Any pattern detection logic receives the plurality of pattern detected signals and generates a plurality of any pattern detected signals. Sequence detection logic receives the plurality of pattern detected signals and generates a plurality of sequence detected signals. Another embodiment relates to a method of data detection and event capture. Another embodiment relates to an integrated circuit having a first data detection and event capture circuit in a receiver circuit and a second data detection and event capture circuit in a transmitter circuit. Other embodiments and features are also disclosed.

Abstract: A control method for a first device of an inter-integrated circuit (I2C) system including a microcontroller unit (MCU), includes receiving a first indication from the MCU of the I2C system, wherein the first indication configures the first device from a slave mode to a master mode; polling the first device itself for status information of the first device when the first device is in the master mode; determining whether the status information of the first device matches a target status after polling; and determining to perform a parameter adjustment on a second device of the I2C system when determining that the status information of the first device matches the target status.

Abstract: A data storage device includes a case and a connector housed within the case. The connector includes a first connection interface having a plurality of connection fingers and a second connection interface having a plurality of springs. The case is positionable within a data storage device port such that the data storage device is completely disposed within the data storage device port when used.

Abstract: A device and method for communication among vehicle components operating on different electronic vehicle bus communication protocols is disclosed. The current invention is specifically designed with the capabilities and reliability required for permanent integration of an incompatible device into a vehicle bus network. This allows for installation and permanent integration of incompatible devices onto new and advanced vehicles which are manufactured using the latest electronic vehicle bus communication protocols.

Abstract: Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated by a first processor for accessing a memory page in a memory system of a second processor. The access tracking unit determines whether a cache memory includes an entry for the memory page. If so, then the access tracking unit increments an associated access counter. Otherwise, the access tracking unit attempts to find an unused entry in the cache memory that is available for allocation. If so, then the access tracking unit associates the second entry with the memory page, and sets an access counter associated with the second entry to an initial value. Otherwise, the access tracking unit selects a valid entry in the cache memory; clears an associated valid bit; associates the entry with the memory page; and initializes an associated access counter.

Abstract: An apparatus includes a pass-through module that includes connector pins to connect with at least one active motherboard connector and to separately connect with at least one routing motherboard connector. A routing function on the pass-through module redirects a set of bidirectional lanes from the connector pins connected to the active motherboard connector to the connector pins connected to the routing motherboard connector to enable a connection of the set of bidirectional lanes to at least one other motherboard connector via the routing motherboard connector.

Abstract: A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads, each of which capable of being coupled to a bus line of one segment of the analog bus as well as to at least one digital bus line, and where the analog bus is capable of being used to connect a pair of the pads to each other.

Abstract: A solid state drive (SSD) apparatus includes a plurality of solid state drives. The SSD apparatus also includes a channel-interleaved interface operably coupled to the plurality of solid state drives, the channel-interleaved interface configured to generate interleaved commands including a first command sent on a first channel-interleaved with a second command sent on a second channel in bursts. Additionally, the SSD includes a Peripheral Component Interconnect Express (PCIe) bridge operably coupled to the channel-interleaved interface.

Abstract: A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a second variable resistor coupled to the clock wire, an analog to digital converter (ADC), and a controller. The data wire is configured to transmit a data signal between a battery and an instrument powered by the battery. The clock wire is configured to transmit a clock signal between a battery and an instrument. The ADC is configured to sample the data signal and the clock signal at a substantially higher frequency than a frequency of the clock signal. The controller is configured to control a resistance of the first variable resistor and a resistance of the second variable resistor based on the digitally sampled data signal and the digitally sampled clock signal.

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Abstract: A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor executing an operating system and a recipient control unit is described. The method may include issuing, by a processor, a Synchronous I/O command to the recipient control unit; receiving, with the processor, a DMA read request from the recipient control unit; converting, with the processor, the DMA read response to write a data record into memory of the recipient control unit; issuing the DMA read request to the recipient control unit, wherein the DMA read request comprises an echo read portion comprising at least one byte of information at the end of the data record written; receiving, by the processor, a DMA write confirmation comprising the echo read portion of the record; and writing the echo read portion to a status area.

Abstract: An example system on a chip (SoC) includes a processor, a cache, and a main memory. The processor can receive a data packet from an electronic device via an interface device, the data packet comprising data for an offload processing task, where the data packet is in a standard link protocol format, the standard link protocol format comprising at least one of an offload protocol identification (ID) field, a tag field, a returned data length field, a flag field, a reserved field, a length field, or a data field. The processor can process the offload processing task to obtain result data. The processor can send the result data to the electronic device.

Abstract: Systems, methods, and apparatus for communication over to serial bus in accordance with an I3C protocol are described. A method performed at a master device includes causing a line driver to enter a high-impedance mode of operation, and receiving data from the serial bus. When a data line of the serial bus is in a high voltage state while a last bit of a data byte is being transmitted, the line may be configured for an open-drain mode of operation, and transmitting a START condition on the serial bus while the last bit of the data byte is being transmitted.

Abstract: A multi-protocol retimer apparatus and method for using the same are disclosed. In one embodiment, an apparatus for performing retiming between first and second devices according to a plurality of protocols comprises: a receiver operable to receive data; a transmitter to transmit data; a first data path coupled to the receiver and the transmitter and operable to transfer data received from the receiver to the transmitter during protocol specific training, where the first data path comprises control circuitry to control protocol specific training of one or both of the transmitter and receiver in response to an indication of one protocol of the plurality of protocols; and a second data path coupled to the receiver and the transmitter, the second data path having a lower latency than the first data path and for use in transferring data received from the receiver to the transmitter after protocol specific training.

Abstract: Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field broadband bus architecture system including a bus controller and at least one bus terminal, the bus controller is connected with the bus terminal over a two-wire data transfer network, and the method includes steps of: electing one of the bus controller and the bus terminal as a best master clock; determining whether an IP address of the device of the best master clock is the same as an IP address of the bus controller; if so, then determining the bus controller as a master device of clock synchronization, and transmitting by the bus controller a synchronization message to the bus terminal for clock synchronization; and otherwise, returning to the step of electing one of the bus controller and the bus terminal as the best master clock.

Abstract: A calculator's input interface includes a knob projecting above the top face of the casing. The knob is provided to allow numbers to be input manually. It is arranged to be able to be switched selectively into a plurality of active positions by tilting it in corresponding directions from an idle position. Each direction corresponds to a different digit to be entered in the calculator. The top face of the casing also has a plurality of first keys associated respectively with mathematical operators, the first keys being positioned relative to the knob in such a way that the ends of the fingers of a user's hand can each be located facing one of the first keys when the palm of the hand is turned downwards and the hollow of the hand covers the end of the knob.

Abstract: A memory system includes a plurality of memory channels, each of the plurality of memory channels includes a plurality of memory dies and a die processor, each of the plurality of memory dies includes a plurality of memory blocks; and a memory controller including a monarch processor, coupled to the plurality of memory channels, wherein the die processor on each of the plurality of memory channels is configured in parallel to process to find last written data within at least a predetermined block of the plurality of memory dies; and provide information regarding the last written data to the monarch processor, the monarch processor determines which boot record to be used to identify firmware images based on the information.

Abstract: A method of managing remote direct memory access (RDMA) to a virtual computing instance includes suspending locally initiated RDMA operations of the virtual computing instance executing on a first host prior to a migration of the virtual computing instance to a second host. The first host includes a first hypervisor and the second host includes a second hypervisor. The method further includes requesting a peer to suspend remotely initiated RDMA operations that target the virtual computing instance through a first channel, establishing after the migration, a second channel between the peer and the second hypervisor that supports execution of the virtual computing instance on the second host, configuring a virtual object of the second hypervisor on the second host to use the second channel for the locally initiated RDMA operations, and requesting the peer to resume the remotely initiated RDMA operations using the second channel.

Abstract: A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator tools implemented on specialized computing equipment may be used to specify desired parameters for the processor architecture, including the data word size of one or more data paths, the instruction word size, and a set of instruction formats. The processor generator tools may also be used to determine the appropriate amount of pipelining that is required for each data path to satisfy performance criteria. The processor generator tools can also be used to analyze the processor architecture and to provide options for mitigating potential structural and data hazards.

Abstract: A method of correlating satellite position data with terrestrial features may include: Using a geometric snapping algorithm to correlate the satellite position data and terrestrial survey data and snap the satellite position data to the terrestrial features; determining whether the satellite position data can be snapped to unique terrestrial features; and using a hybrid space-time snapping algorithm to correlate the satellite position data and terrestrial survey data and snap the satellite position data to unique terrestrial features when the satellite position data cannot be snapped to unique terrestrial features.

Abstract: A processor of an information processing apparatus generates an extended image by adding pixels to outside of a target image. The processor generates an integral image. A value of each element of the integral image is a sum of pixel values of first pixels of the extended image. The first pixels are included in a direction toward an origin of the extended image from a pixel corresponding to the element of the integral image. The processor generates a partial-sum matrix for each pixel of a reduced image using the integral image. A value of each element of the partial-sum matrix is a sum of pixel values of second pixels of the extended image. The second pixels are included in an area corresponding to the element of the partial-sum matrix. The processor performs a convolution operation on the partial-sum matrix using the filter matrix.

Abstract: A system and method for efficient sparse matrix processing are provided in one embodiment. A compressed representation of a sparse matrix, the sparse matrix including one or more non-zero entries in one or more of a plurality of portions of the matrix, is obtained by at least one server including one or more streaming multiprocessors, each of the streaming multiprocessors including one or more graphics processing unit (GPU) processor cores. Each of the portions are assigned into one of a plurality of partitions based on a number of the non-zero entries in that portion. For each of the partitions, a predefined number of the GPU processor cores are assigned for processing each of the portions assigned to that partition based on the numbers of the non-zero entries in the portions assigned to that partition. For each of the partitions, each of the portions associated with that partition are processed.

Abstract: Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted to an output sample with a second frequency. A sample rate conversion circuit is provided which provides an enhanced transposed farrow structure that enables an optimised trade-off between noise levels and computational complexity. Each output sample is derived by convolution of a continuous time interpolation kernel with a continuous time step function representing the input sample stream. In a sample rate conversion structure, there is a trade-off between the quality and the computational complexity. The quality is defined as a ratio between the (wanted) signal power and the (unwanted) noise power. The computational complexity may be defined as the average number of arithmetic operations that are required to generate one output sample. A higher computational complexity will generally lead to a higher power consumption and larger footprint.

Abstract: A method of providing transformed target points for integrating a component into an assembly includes collecting a set of component target points, collecting a set of assembly target points, identifying target points common to the set of component target points and the set of assembly target points; performing a specified number of Monte Carlo transformations of selected ones of the common target points to yield a set of transformed target points and vectors and an associated uncertainty value for each transformed target point and vector, and using certain ones of the transformed target points for integrating the component into the assembly based on the associated uncertainty value for each of the transformed target points.

Abstract: A browser renders web site views dynamically, based on previously consumed content items. When the browser loads a new web site which contains, among other object, content items, those content items which are duplicative of previously consumed content items are suppressed when the web site view is rendered in the browser. Content items that are related to previously consumed content items can be prioritized in the rendered view of the web site.

Abstract: An information processing apparatus includes an archive file generation unit and a deriving unit. The archive file generation unit generates multiple archive files each including one or more pieces of document data and information regarding one or more processing functions. The one or more pieces of document data are each associated with the one or more processing functions. The information indicates one or more processes to be executed on the one or more pieces of document data. The deriving unit derives, from the multiple generated archive files, a common processing function among the processing functions that is common to the archive files and a piece of document data among the pieces of document data that is associated with the common processing function.

Abstract: A method, device and terminal for implementing regional screen capture are described. The method includes: capturing a full content of a current screen interface according to a screen capture instruction and generating a picture; parsing layout information of the current screen interface, and mark various controls in the generated picture by using the acquired layout information; determining a capture region according to a control selected based on a mark, and capturing the content displayed on one or more determined capture regions; when the capture is required, capturing the full content of the current screen interface and generating picture data; parsing the layout information of the current screen interface, and marking various controls on the generated picture according to the acquired layout information; and determining the capture region according to the selected controls.

Abstract: A method, apparatus, and system are provided for displaying a graphical representation of at least a portion of a file by interfacing with a graphical interface relating to the file. A request for viewing a file content is received. A window for viewing a graphical representation of at least a portion of the content of a file is provided.

Abstract: Methods for optimizing a scale and position of a document in response to a user input is provided are provided. In one aspect, a method includes receiving an initial input request to scale a document to display a target portion of the document, and identifying at least one relevant portion of content at or near the target portion of the document. The method also includes adjusting a position and scale of the document while receiving the initial input request to an optimal position and to an optimal scale for viewing the at least one relevant portion. Systems and machine-readable media are also provided.

Abstract: Autotagging a template of a reporting workbook is provided. The template of the reporting workbook is received. The template is in a first format type. User specified selection of portions of the template are received. The portions are associated with at least two dimensions of the reporting workbook. A user specified type is received for a tag. A modification of the template is created by automatically generating a tag in a predetermined field of each of the portions based on the user specified type. A version of the reporting workbook is generated based on the modification of the template, wherein the version is in a second format type.