Patents Issued in April 24, 2018
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Patent number: 9954072Abstract: A silicon-carbide semiconductor device that relaxes field intensity in a gate insulating film, and that has a low ON-resistance. The silicon-carbide semiconductor device includes: an n-type silicon-carbide substrate; a drift layer formed on a topside of the n-type silicon-carbide substrate; a trench formed in the drift layer and that includes therein a gate insulating film and a gate electrode; a p-type high-concentration well region formed parallel to the trench with a spacing therefrom and that has a depth larger than that of the trench; and a p-type body region formed to have a depth that gradually increases when nearing from a position upward from the bottom end of the trench by approximately the thickness of the gate insulating film at the bottom of the trench toward the lower end of the p-type high-concentration well region.Type: GrantFiled: September 5, 2013Date of Patent: April 24, 2018Assignee: Mitsubishi Electric CorporationInventors: Rina Tanaka, Yasuhiro Kagawa, Shiro Hino, Naruhisa Miura, Masayuki Imaizumi
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Patent number: 9954073Abstract: A method for manufacturing a SiC semiconductor device includes: forming recesses to be separated from each other on a cross section in parallel to a surface of the substrate by partially removing a top portion of the drift layer with etching using a mask after arranging the mask on a front surface of a drift layer; forming electric field relaxation layers having the second conductivity type to be separated from each other on the cross section by ion-implanting a second conductivity type impurity on a bottom of each recess using the mask; and forming a channel layer by forming a second conductivity type layer on the front surface of the drift layer including a front surface of each electric field relaxation layer in a respective recess.Type: GrantFiled: January 14, 2015Date of Patent: April 24, 2018Assignee: DENSO CORPORATIONInventors: Nozomu Akagi, Jun Sakakibara, Shoji Mizuno, Yuichi Takeuchi
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Patent number: 9954074Abstract: An insulated gate bipolar transistor and a manufacturing method therefor. The insulated gate bipolar transistor comprises a semiconductor substrate (1) of a first conductive type, which is provided with a first major surface (1S1) and a second major surface (1S2), wherein the semiconductor substrate (1) comprises a primitive cell area (2) and a terminal protection area (4) which is located outside the primitive cell area; a first semiconductor layer (5) of a first conductive type which is formed at the side of the first major surface of the semiconductor substrate (1), wherein the doping concentration of the first semiconductor layer (5) is higher than the doping concentration of the semiconductor substrate (1); and an insulated gate transistor unit which is formed at the side of the first major surface of the first semiconductor layer (5) in the primitive cell area, wherein the insulated gate transistor unit is conducted, a channel of a first conductive type is formed.Type: GrantFiled: July 22, 2014Date of Patent: April 24, 2018Assignee: CSMC TECHNOLOGIES FAB1 CO., LTD.Inventors: Shengrong Zhong, Xiaoshe Deng, Genyi Wang, Dongfei Zhou
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Patent number: 9954075Abstract: Memory devices and methods of making memory devices are shown. Methods and configurations as shown provide folded and vertical memory devices for increased memory density. Methods provided reduce a need for manufacturing methods such as deep dopant implants.Type: GrantFiled: October 3, 2016Date of Patent: April 24, 2018Assignee: Micron Technology, Inc.Inventors: Sanh D. Tang, John K. Zahurak, Michael P. Violette
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Patent number: 9954076Abstract: A semiconductor device includes first and second FETs including first and second channel regions, respectively. The first and second FETs include first and second gate structures, respectively. The first and second gate structures include first and second gate dielectric layers formed over the first and second channel regions and first and second gate electrode layers formed over the first and second gate dielectric layers. The first and second gate structures are aligned along a first direction. The first gate structure and the second gate structure are separated by a separation plug made of an insulating material. A width of the separation plug in a second direction perpendicular to the first direction is smaller than a width of the first gate structure in the second direction, when viewed in plan view.Type: GrantFiled: April 13, 2017Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Hao Yu, Sheng-chen Wang, Sai-Hooi Yeong
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Patent number: 9954077Abstract: A method comprises etching away an upper portion of a substrate to form a trench between two adjacent isolation regions, wherein the substrate has a first crystal orientation and is formed of a first semiconductor material, growing a first semiconductor region in the trench over the substrate, wherein the first semiconductor region is formed of a second semiconductor material and an upper portion of the first semiconductor region has a second crystal orientation and growing a second semiconductor region over the first semiconductor region, wherein the second semiconductor region is formed of a third semiconductor material.Type: GrantFiled: August 31, 2015Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Georgios Vellianitis
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Patent number: 9954078Abstract: A method of manufacturing a super junction MOSFET, which includes a parallel pn layer including a plurality of pn junctions and in which an n-type drift region and a p-type partition region interposed between the pn junctions are alternately arranged and contact each other, a MOS gate structure on the surface of the parallel pn layer, and an n-type buffer layer in contact with an opposite main surface. The impurity concentration of the buffer layer is equal to or less than that of the n-type drift region. At least one of the p-type partition regions in the parallel pn layer is replaced with an n? region with a lower impurity concentration than the n-type drift region.Type: GrantFiled: June 19, 2017Date of Patent: April 24, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takahiro Tamura, Yasuhiko Onishi
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Patent number: 9954079Abstract: Methods form an electronic semiconductor device that includes a body having a first side and a second side opposite to one another and including a first structural region facing the second side, and a second structural region extending over the first structural region and facing the first side. A body region extends in the second structural region at the first side. A source region extends inside the body region and a lightly-doped drain region faces the first side of the body. A gate electrode is formed over the body region. A trench dielectric region extends through the second structural region in a first trench conductive region immediately adjacent to the trench dielectric region. A second trench conductive region is in electrical contact with the body region and source region. An electrical contact on the body is in electrical contact with the drain region through the first structural region.Type: GrantFiled: December 9, 2015Date of Patent: April 24, 2018Assignee: STMicroelectronics S.r.l.Inventors: Salvatore Cascino, Leonardo Gervasi, Antonello Santangelo
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Patent number: 9954080Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the second transistor is overlaying the first transistor, where the first transistor controls the supply of a ground or a power signal to the third transistor, and where the first transistor, the second transistor and the third transistor are aligned to each other with less than 100 nm misalignment.Type: GrantFiled: June 14, 2017Date of Patent: April 24, 2018Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist
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Patent number: 9954081Abstract: A substrate is patterned to form trenches and a semiconductor fin between the trenches. Insulators are formed in the trenches and a first dielectric layer is formed to cover the semiconductor fin and the insulators. A dummy gate strip is formed on the first dielectric layer. Spacers are formed on sidewalls of the dummy gate strip. The dummy gate strip and the first dielectric layer underneath are removed until sidewalls of the spacers, a portion of the semiconductor fin and portions of the insulators are exposed. A second dielectric layer is conformally formed to cover the sidewalls of the spacers, the exposed portion of the semiconductor fin and the exposed portions of the insulators, wherein a thickness of the first dielectric layer is smaller than a thickness of the second dielectric layer. A gate is formed on the second dielectric layer and between the spacers.Type: GrantFiled: December 15, 2015Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
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Patent number: 9954082Abstract: A method of fabricating an embedded nonvolatile memory device is disclosed. A semiconductor substrate having thereon a fin body protruding from an isolation layer is provided. A charge storage layer crossing the fin body is formed. An inter-layer dielectric layer is deposited on the semiconductor substrate. The inter-layer dielectric layer is polished to expose a top surface of the charge storage layer. The charge storage layer is then recess etched and cut into separate charge storage structures. A high-k dielectric layer is formed on the charge storage structures. A word line is formed on the high-k dielectric layer.Type: GrantFiled: May 17, 2017Date of Patent: April 24, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hao-Ming Lee, Sheng-Hao Lin, Tzyy-Ming Cheng
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Patent number: 9954083Abstract: A method of introducing strain in a channel region of a FinFET device includes forming a fin structure on a substrate, the fin structure having a lower portion comprising a sacrificial layer and an upper portion comprising a strained semiconductor layer; and removing a portion of the sacrificial layer corresponding to a channel region of the FinFET device so as to release the upper portion of the fin structure from the substrate in the channel region.Type: GrantFiled: August 20, 2015Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim
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Patent number: 9954084Abstract: In a transistor including an oxide semiconductor film, a metal oxide film for preventing electrification which is in contact with the oxide semiconductor film and covers a source electrode and a drain electrode is formed. Then, oxygen is introduced (added) to the oxide semiconductor film through the metal oxide film and heat treatment is performed. Through these steps of oxygen introduction and heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, so that the oxide semiconductor film is highly purified. Further, by providing the metal oxide film, generation of a parasitic channel on a back channel side of the oxide semiconductor film can be prevented in the transistor.Type: GrantFiled: August 1, 2016Date of Patent: April 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 9954085Abstract: A tunnel field-effect transistor device includes a p-type GaN source layer, an ntype GaN drain layer, and an interlayer interfaced between the source-layer and the drain layer. These devices employ polarization engineering in GaN/InN heterojunctions to achieve appreciable interband tunneling current densities. In one example, the interlayer includes an Indium Nitride (InN) layer. In one example, the interlayer includes a graded Indium gallium nitride layer and an InN layer. In one example, the interlayer may include a graded Indium gallium nitride (InxGa1-xN) layer and an Indium gallium nitride (InGaN) layer. In one example, the tunnel field-effect transistor device includes an in-line configuration. In one example, the tunnel field-effect transistor device includes a side-wall configuration. In one example, the tunnel field-effect transistor device includes a nanowire cylindrical gate-all-around geometry to achieve a high degree of gate electrostatic control.Type: GrantFiled: June 27, 2016Date of Patent: April 24, 2018Assignee: University of Notre Dame due LacInventors: Patrick Fay, Lina Cao, Debdeep Jena, Wenjun Li
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Patent number: 9954086Abstract: A semiconductor device of the present invention is structured such that in a surface layer of a first principal surface of a semiconductor substrate, an n-type drift layer, a p-type base layer, a p-type floating layer, an n-type emitter layer, an emitter electrode, and a trench in which a gate electrode is embedded with a gate insulating film is disposed therebetween are formed from a front surface side. Further, in a surface layer of a second principal surface of the semiconductor substrate, a p-type collector layer and a collector electrode contacting the-type collector layer are formed, and in a direction from the p-type collector layer toward a surface, an n-type selenium-doped field stop layer and an n-type proton doped field stop layer are formed, whereby IGBT turn OFF oscillation, oscillation at diode reverse recovery, and increases in leak voltage can be suppressed, and electrical loss can be reduced.Type: GrantFiled: June 6, 2016Date of Patent: April 24, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Yuichi Onozawa
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Patent number: 9954087Abstract: In a group III nitride-type field effect transistor, the present invention reduces a leak current component by conduction of residual carriers in a buffer layer, and achieves improvement in a break-down voltage, and enhances a carrier confinement effect (carrier confinement) of a channel to improve pinch-off characteristics (to suppress a short channel effect). For example, when applying the present invention to a GaN-type field effect transistor, besides GaN of a channel layer, a composition-modulated (composition-gradient) AlGaN layer in which aluminum composition reduces toward a top gradually or stepwise is used as a buffer layer (hetero buffer).Type: GrantFiled: August 27, 2014Date of Patent: April 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Takashi Inoue, Tatsuo Nakayama, Yuji Ando, Yasuhiro Murase, Kazuki Ota, Hironobu Miyamoto, Katsumi Yamanoguchi, Naotaka Kuroda, Akio Wakejima, Yasuhiro Okamoto
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Patent number: 9954088Abstract: There is provided a method for fabricating a semiconductor device having the following structure, and comprising the steps of growing a nucleation layer on a substrate; depositing a binary layer over the nucleation layer; and annealing the binary layer to form a first contact area and a second contact area on the substrate, wherein the annealed binary layer comprises a group 14 element selected from Si, Ge or their combination thereof, and the annealed binary layer in the first and second contact areas are capable of providing a lower contact resistance for a current to flow in the device. This method serves to provide an intermediate layer which enables the fabrication process to become CMOS compatible.Type: GrantFiled: October 20, 2014Date of Patent: April 24, 2018Assignee: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCHInventors: Lakshmi Kanta Bera, Surani Bin Dolmanan, Manippady Krishna Kumar, Rasanayagam Sivasayan Kajen, Sudhiranjan Tripathy
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Patent number: 9954089Abstract: There are disclosed herein various implementations of a semiconductor component including a protrusion propagation body. The semiconductor component includes a substrate, a III-Nitride intermediate stack including the protrusion propagation body situated over the substrate, a III-Nitride buffer layer situated over the group III-V intermediate stack, and a III-Nitride device fabricated over the group III-V buffer layer. The protrusion propagation body includes at least a protrusion generating layer and two or more protrusion spreading multilayers.Type: GrantFiled: June 20, 2016Date of Patent: April 24, 2018Assignee: Infineon Technologies Americas Corp.Inventors: Chan Kyung Choi, Mihir Tungare, Peter Wook Kim
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Patent number: 9954090Abstract: A monolithically integrated device includes a substrate, a first set of Group III nitride epitaxial layers grown for a first HFET on a first region of the substrate, and a second set of Group III nitride epitaxial layers for a second HFET grown on a second region of the substrate.Type: GrantFiled: May 6, 2016Date of Patent: April 24, 2018Assignee: HRL Laboratories, LLCInventors: David F. Brown, Keisuke Shinohara, Miroslav Micovic, Andrea Corrion
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Patent number: 9954091Abstract: A compound semiconductor device includes: a substrate; a channel layer over the substrate; a carrier supply layer over the channel layer; a gate electrode, a source electrode and a drain electrode above the channel layer and the carrier supply layer; and an insulating film that covers the carrier supply layer between the source electrode and the drain electrode. The insulating film includes: a first region that contains anion under the gate electrode; and a second region on the source electrode side or on the drain electrode side of the first region, an anion concentration in the second region being lower than an anion concentration in the first region.Type: GrantFiled: October 10, 2016Date of Patent: April 24, 2018Assignee: FUJITSU LIMITEDInventor: Motonobu Sato
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Patent number: 9954092Abstract: A semiconductor device according to an embodiment includes a nitride semiconductor layer and an insulating layer including an oxide film or an oxynitride film that contacts with the nitride semiconductor layer. The oxide film or the oxynitride film includes at least one impurity selected from the group consisting of boron (B), gallium (Ga), aluminum (Al), and indium (In) and carbon (C). A first peak of a concentration distribution of the at least one impurity in the insulating layer is present in the oxide film or the oxynitride film. A second peak of a concentration distribution of carbon in the insulating layer is present in the oxide film or the oxynitride film. A distance between the first peak and the nitride semiconductor layer is equal to or less than 5 nm, and a distance between the second peak and the nitride semiconductor layer is equal to or less than 5 nm.Type: GrantFiled: February 23, 2017Date of Patent: April 24, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Tatsuo Shimizu, Hisashi Saito
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Patent number: 9954093Abstract: A semiconductor device is manufactured by: i) forming a mask on a process surface of a semiconductor layer, elongated openings of the mask exposing part of the semiconductor layer and extending along a first lateral direction; ii) implanting dopants of a first conductivity type into the semiconductor layer based on tilt angle ?1 between an ion beam direction and a process surface normal and based on twist angle ?1 between the first lateral direction and a projection of the ion beam direction on the process surface; iii) implanting dopants of a second conductivity type into the semiconductor layer based on tilt angle ?2 between an ion beam direction and the process surface normal and based on twist angle ?2 between the first lateral direction and a projection of the ion beam direction on the process surface; and repeating i) to iii) at least one time.Type: GrantFiled: June 28, 2017Date of Patent: April 24, 2018Assignee: Infineon Technologies Austria AGInventor: Hans Weber
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Patent number: 9954094Abstract: In order to improve the performance of a semiconductor device, a p type impurity is ion implanted into an area of an n type semiconductor film that is epitaxially grown over a p type semiconductor substrate, and the p type impurity is not ion implanted into an area of the n type semiconductor film, which is adjacent to the area in which the p type impurity is ion implanted. In this way, a p? type drift layer comprised of the area in which the p type impurity is introduced, as well as an n? type semiconductor region comprised of the area in which the p type impurity is not introduced are formed.Type: GrantFiled: January 28, 2016Date of Patent: April 24, 2018Assignee: Renesas Electronics CorporationInventors: Kinya Ohtani, Yasuhiro Nishimura
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Patent number: 9954095Abstract: To provide a semiconductor device less affected by noise without making a manufacturing process more complicated and increasing a chip area. The device has a semiconductor substrate having first and second surfaces, a first-conductivity-type drain region on the second surface side in the semiconductor substrate, a first-conductivity-type drift region on the first surface side of a substrate region, a second-conductivity-type base region on the first surface side of the drift region, a first-conductivity-type source region on the first surface of the semiconductor substrate sandwiching a base region between the source and drift regions, a gate electrode opposite to and insulated from the base region, a wiring on the first main surface electrically coupled to the source region, and a first conductive film on the first main surface, opposite to and insulated from the wiring, and electrically coupled to the substrate region.Type: GrantFiled: January 8, 2017Date of Patent: April 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Taro Moriya, Hiroyoshi Kudou, Satoshi Uchiya
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Patent number: 9954096Abstract: A switching device includes a semiconductor substrate; a trench; a conductor layer extending in a longitudinal direction of the trench so as to be in contact with a bottom surface of the trench; a bottom insulating layer covering an upper surface of the conductor layer; a gate insulating layer covering a side surface of the trench; and a gate electrode disposed in the trench. The semiconductor substrate includes a first semiconductor region of a first conductivity type, a body region of a second conductivity type, a second semiconductor region of the first conductivity type, a bottom semiconductor region of the second conductivity type extending in the longitudinal direction so as to be in contact with the conductor layer, and a connection semiconductor region of the second conductivity type connected to the body region and to the bottom semiconductor region.Type: GrantFiled: July 31, 2017Date of Patent: April 24, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Hirokazu Fujiwara, Yuichi Takeuchi, Narumasa Soejima
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Patent number: 9954097Abstract: The present disclosure relates to a transistor device having a field plate, and a method of formation. In some embodiments, the transistor device has a gate electrode disposed over a substrate between a source region and a drain region. One or more dielectric layers laterally extend from over the gate electrode to a location between the gate electrode and the drain region. A field plate is located within an inter-level dielectric (ILD) layer overlying the substrate. The field plate laterally extends from over the gate electrode to over the location and vertically extends from the one or more dielectric layers to a top surface of the ILD layer. A conductive contact is arranged over the drain region and is surrounded by the ILD layer. The conductive contact extends to the top surface of the ILD layer.Type: GrantFiled: February 3, 2017Date of Patent: April 24, 2018Assignee: Taiwan Seminconductor Manufacturing Co., Ltd.Inventors: Hsueh-Liang Chou, Dah-Chuen Ho, Hui-Ting Lu, Po-Chih Su, Pei-Lun Wang, Yu-Chang Jong
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Patent number: 9954098Abstract: A semiconductor structure and a method of manufacturing the semiconductor structure are provided. The semiconductor structure includes at least a substrate, an isolated structure, a gate, a source, a drain, a deep well, and a body well. The deep well extends under the isolated structure, and the body well is formed in the deep well between the gate and the isolated structure, wherein the body well has a convex region extending under the isolated structure. The deep well has a drive-in region outside the convex region of the body well, and the drive-in region has a lower doping concentration than remainder of the deep well.Type: GrantFiled: April 26, 2017Date of Patent: April 24, 2018Assignee: MACRONIX International Co., Ltd.Inventor: Yu-Jui Chang
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Patent number: 9954099Abstract: A transistor structure including a gate, a first dielectric layer, a first contact and a second contact is provided. The gate is disposed on a substrate. The first dielectric layer is disposed on the substrate. The first dielectric layer covers a portion of a top surface of the gate. The first contact is electrically connected to the gate. The second contact is disposed on the first dielectric layer. The second contact is electrically connected with the first contact.Type: GrantFiled: June 23, 2017Date of Patent: April 24, 2018Assignee: United Microelectronics Corp.Inventors: Cheng-Hsun Chung, Shih-Teng Huang, Tien-Shang Kuo
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Patent number: 9954100Abstract: A method includes forming a gate spacer along sidewalls of a gate structure, forming a source region and a drain region on opposite sides of the gate structure, wherein a sidewall of the source region is vertically aligned with a first sidewall of the gate spacer, depositing a dielectric layer over the substrate, depositing a conductive layer over the dielectric layer, patterning the dielectric layer and the conductive layer to form a field plate, wherein the dielectric layer comprises a horizontal portion extending from the second drain/source region to a second sidewall of the gate spacer and a vertical portion formed along the second sidewall of the gate spacer, forming a plurality of metal silicide layers by applying a salicide process to the conductive layer, the gate structure, the first drain/source region and the second drain/source region and forming contact plugs over the plurality of metal silicide layers.Type: GrantFiled: March 24, 2016Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Chyi Liu, Pei-Lun Wang, Yuan-Tai Tseng, Yu-Hsing Chang, Shih-Chang Liu
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Patent number: 9954101Abstract: A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch stop layer of a second semiconductor material present within the first of the source region and the drain region. A channel semiconductor material is present atop the first of the source region and the drain region. A second of the source and the drain region is present atop the channel semiconductor material. The semiconductor device may be a vertically orientated fin field effect transistor or a vertically orientated tunnel field effect transistor.Type: GrantFiled: June 15, 2016Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huiming Bu, Liying Jiang, Siyuranga O. Koswatta, Junli Wang
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Patent number: 9954102Abstract: A semiconductor structure is provided that includes a vertical transport field effect transistor located on sidewall surfaces of a semiconductor fin. The semiconductor structure further includes an abrupt junction that is located between a bottom source/drain extension region and a sidewall surface of a lower portion of the semiconductor fin. The bottom source/drain extension region is present in a gap that is located adjacent the lower portion of the semiconductor fin and atop a mesa portion of a base semiconductor substrate.Type: GrantFiled: April 20, 2017Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Shogo Mochizuki, Alexander Reznicek
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Patent number: 9954103Abstract: A bilayer of silicon dioxide and silicon nitride is formed on exposed surfaces of at least one semiconductor fin having a bottom source/drain region located at the footprint, and on each side, of the at least one semiconductor fin. An upper surface of each horizontal portion of the silicon nitride layer is then carbonized, and thereafter non-carbonized vertical portions of the silicon nitride layer are removed. Next, the carbonized portions of the silicon nitride layer are removed, and thereafter the vertical portions of the silicon dioxide layer are removed from sidewalls of the at least one semiconductor fin utilizing each remaining portion of the silicon nitride layer as an etch mask A bottom spacer structure is provided on each bottom source/drain region in which each bottom spacer structure includes a remaining portion of the silicon dioxide layer and the remaining portion of the silicon nitride layer.Type: GrantFiled: September 25, 2017Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Oleg Gluschenkov, Sanjay C. Mehta, Shogo Mochizuki, Alexander Reznicek
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Patent number: 9954104Abstract: An improved structure and methods of fabrication for finFET devices utilizing a cladding channel are disclosed. A staircase fin is formed where the fin comprises an upper portion of a first width and a lower portion of a second width, wherein the lower portion is wider than the upper portion. The narrower upper portion allows the cladding channel to be deposited and still have sufficient space for proper gate deposition, while the lower portion is wide to provide improved mechanical stability, which protects the fins during the subsequent processing steps.Type: GrantFiled: January 24, 2014Date of Patent: April 24, 2018Inventors: Ruilong Xie, Ajey Poovannummoottil Jacob
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Patent number: 9954105Abstract: A method includes providing a semiconductor substrate having first and second regions that are doped with first and second dopants respectively. The first and second dopants are of opposite types. The method further includes epitaxially growing a first semiconductor layer that is doped with a third dopant. The first and third dopants are of opposite types. The method further includes depositing a dielectric hard mask (HM) layer over the first semiconductor layer; patterning the dielectric HM layer to have an opening over the first region; extending the opening towards the semiconductor substrate; and epitaxially growing a second semiconductor layer in the opening. The second semiconductor layer is doped with a fourth dopant. The first and fourth dopants are of a same type. The method further includes removing the dielectric HM layer; and performing a first CMP process to planarize both the first and second semiconductor layers.Type: GrantFiled: September 18, 2017Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Kuo-Yin Lin, Teng-Chun Tsai, Po-Yu Lin
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Patent number: 9954106Abstract: A method of forming a semiconductor structure in which a III-V compound semiconductor channel fin portion is formed on a dielectric material is provided. The method includes forming a III-V material stack on a surface of a bulk semiconductor substrate. Patterning of the III-V material stack is then employed to provide a pre-fin structure that is located between, and in contact with, pre-pad structures. The pre-pad structures are used as an anchoring agent when a III-V compound semiconductor channel layer portion of the III-V material stack and of the pre-fin structure is suspended by removing a topmost III-V compound semiconductor buffer layer portion of the material stack from the pre-fin structure. A dielectric material is then formed within the gap provided by the suspending step and thereafter a fin cut process is employed.Type: GrantFiled: October 13, 2016Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Hemanth Jagannathan, Alexander Reznicek
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Patent number: 9954107Abstract: A semiconductor structure, such as a strained FinFETs, includes a strain relief buffer (SRB) layer isolated and separated from a source and a drain by a second spacer simultaneously formed with a first spacer upon the sidewalls of a gate structure. The second spacer limits the source and drain from contacting the SRB layer thereby limiting source drain junction leakage. Further, the second spacer limits source and drain punch through to the SRB layer underneath a channel. An etch partially removes a SRB layer portion 24 within a fin stack. The etch undercuts the source and drain forming a fin void without under cutting the channel. The second spacer is formed by depositing spacer material with the fin void.Type: GrantFiled: May 5, 2015Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Veeraraghavan S. Basker, Theodorus E. Standaert, Junli Wang
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Patent number: 9954108Abstract: A semiconductor device includes a silicon substrate, a fin shaped structure and a shallow trench isolation. The fin shaped structure includes a top portion which protrudes from a bottom surface of the fin shaped structure and the fin shaped structure is directly disposed on the silicon substrate. The bottom surface of the fin shaped structure covers an entire top surface of the silicon substrate. The fin shaped structure further includes a silicon germanium (SiGe) layer extending within the fin shaped structure and occupying the whole top portion of the shaped structure. The fin shaped structure is a semiconductor fin shaped structure, and the material of the silicon substrate is different from the material of the silicon germanium layer The shallow trench isolation is disposed on the top portion and the bottom surface of the fin shaped structure.Type: GrantFiled: March 14, 2017Date of Patent: April 24, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chung-Yi Chiu, Shih-Fang Hong, Chao-Hung Lin
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Patent number: 9954109Abstract: A vertical transistor includes a gate structure interposed between a proximate spacer doped with a first dopant-type and a distal spacer doped with the first dopant-type. The proximate spacer is formed on an upper surface of a semiconductor substrate. At least one channel region extends vertically from the proximate doping source layer to the distal doping source layer. A proximate S/D extension region is adjacent the proximate spacer and a distal S/D extension region is adjacent the distal spacer. The proximate and distal S/D extension regions include dopants that match the first dopant-type of the proximate and distal doping sources.Type: GrantFiled: May 5, 2016Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Ramachandra Divakaruni
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Patent number: 9954110Abstract: Provided is an EL display device which is provided with a power supply line driver circuit including a transistor having capability in supplying a large amount of current over an insulating substrate where a pixel portion is formed. An active matrix EL display device includes a plurality of pixels, a plurality of signal lines, a plurality of scan lines, and a plurality of power supply lines over an insulating substrate; a transistor formed using an oxide semiconductor with a field-effect mobility of at least higher than or equal to 80 cm2/Vs, preferably higher than or equal to 120 cm2/Vs over the insulating substrate; and a power supply line driver circuit including the transistor as a component.Type: GrantFiled: May 8, 2012Date of Patent: April 24, 2018Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventor: Jun Koyama
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Patent number: 9954111Abstract: Provided is a highly integrated semiconductor device, a semiconductor device with large storage capacity with respect to an area occupied by a capacitor, a semiconductor device capable of high-speed writing, a semiconductor device capable of high-speed reading, a semiconductor device with low power consumption, or a highly reliable semiconductor device. The semiconductor device includes a first transistor, a second transistor, and a capacitor. A conductor penetrates and connects the first transistor, the capacitor, and the second transistor. An insulator is provided on a side surface of the conductor that penetrates the capacitor.Type: GrantFiled: March 17, 2015Date of Patent: April 24, 2018Assignee: Semiconductor Energy Laboratory Co., LTD.Inventors: Shunpei Yamazaki, Hideomi Suzawa
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Patent number: 9954112Abstract: A semiconductor device includes a first oxide insulating layer over a first insulating layer, an oxide semiconductor layer over the first oxide insulating layer, a source electrode layer and a drain electrode layer over the oxide semiconductor layer, a second insulating layer over the source electrode layer and the drain electrode layer, a second oxide insulating layer over the oxide semiconductor layer, a gate insulating layer over the second oxide insulating layer, a gate electrode layer over the gate insulating layer, and a third insulating layer over the second insulating layer, the second oxide insulating layer, the gate insulating layer, and the gate electrode layer. A side surface portion of the second insulating layer is in contact with the second oxide insulating layer. The gate electrode layer includes a first region and a second region. The first region has a width larger than that of the second region.Type: GrantFiled: January 14, 2016Date of Patent: April 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshinobu Asami, Yutaka Okazaki, Satoru Okamoto, Shinya Sasagawa
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Patent number: 9954113Abstract: A transistor with favorable electrical characteristics is provided. A transistor with stable electrical characteristics is provided. A semiconductor device having a high degree of integration is provided. Side surfaces of an oxide semiconductor layer in which a channel is formed are covered with an oxide semiconductor layer, whereby impurity diffusion from the side surfaces of the oxide semiconductor into the inside can be prevented. A gate electrode is formed by a damascene process, whereby transistors can be miniaturized and formed at a high density.Type: GrantFiled: February 8, 2016Date of Patent: April 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Akihisa Shimomura, Satoru Okamoto, Yutaka Okazaki, Yoshinobu Asami, Hiroaki Honda, Takuya Tsurume
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Patent number: 9954114Abstract: The electrical characteristics of a transistor including an oxide semiconductor layer are varied by influence of an insulating film in contact with the oxide semiconductor layer, that is, by an interface state between the oxide semiconductor layer and the insulating film. A first oxide semiconductor layer S1, a second oxide semiconductor layer S2, and a third oxide semiconductor layer S3 are sequentially stacked, so that the oxide semiconductor layer through which carriers flow is separated from the gate insulating film containing silicon. The thickness of the first oxide semiconductor layer S1 is preferably smaller than those of the second oxide semiconductor layer S2 and the third oxide semiconductor layer S3, and is less than or equal to 10 nm, preferably less than or equal to 5 nm.Type: GrantFiled: September 27, 2016Date of Patent: April 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 9954115Abstract: A highly reliable semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device is manufactured with a high yield, so that high productivity is achieved. In a semiconductor device including a transistor in which a source electrode layer and a drain electrode layer are provided over and in contact with an oxide semiconductor film, entry of impurities and formation of oxygen vacancies in an end face portion of the oxide semiconductor film are suppressed. This can prevent fluctuation in the electric characteristics of the transistor which is caused by formation of a parasitic channel in the end face portion of the oxide semiconductor film.Type: GrantFiled: October 6, 2016Date of Patent: April 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Motoki Nakashima, Masahiro Takahashi
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Patent number: 9954116Abstract: Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.Type: GrantFiled: November 3, 2016Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
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Patent number: 9954117Abstract: A novel semiconductor device including an oxide semiconductor is provided. In particular, a planar semiconductor device including an oxide semiconductor is provided. A semiconductor device including an oxide semiconductor and having large on-state current is provided. The semiconductor device includes an oxide insulating film, an oxide semiconductor film over the oxide insulating film, a source electrode and a drain electrode in contact with the oxide semiconductor film, a gate insulating film between the source electrode and the drain electrode, and a gate electrode overlapping the oxide semiconductor film with the gate insulating film. The oxide semiconductor film includes a first region overlapped with the gate electrode and a second region not overlapped with the gate electrode, the source electrode, and the drain electrode. The first region and the second region have different impurity element concentrations.Type: GrantFiled: July 27, 2017Date of Patent: April 24, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Junichi Koezuka, Masami Jintyou, Yukinori Shima, Takashi Hamochi, Yasutaka Nakazawa, Shunpei Yamazaki
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Patent number: 9954118Abstract: The method comprises implanting a deep well of a first type of electrical conductivity provided for a drift region in a substrate of semiconductor material, the deep well of the first type comprising a periphery, implanting a deep well or a plurality of deep wells of a second type of electrical conductivity opposite to the first type of electrical conductivity at the periphery of the deep well of the first type, implanting shallow wells of the first type of electrical conductivity at the periphery of the deep well of the first type, the shallow wells of the first type extending into the deep well of the first type; and implanting shallow wells of the second type of electrical conductivity adjacent to the deep well of the first type between the shallow wells of the first type of electrical conductivity.Type: GrantFiled: August 16, 2017Date of Patent: April 24, 2018Assignee: AMS AGInventor: Martin Knaipp
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Patent number: 9954119Abstract: The present disclosure relates to a Zener diode including a Zener diode junction formed in a semiconductor substrate along a plane parallel to the surface of the substrate, and positioned between a an anode region having a first conductivity type and a cathode region having a second conductivity type, the cathode region extending from the surface of the substrate. A first conducting region is configured to generate a first electric field perpendicular to the plane of the Zener diode junction upon application of a first voltage to the first conducting region, and a second conducting region is configured to generate a second electric field along the plane of the Zener diode junction upon application of a second voltage to the second conducting region.Type: GrantFiled: January 10, 2017Date of Patent: April 24, 2018Assignee: STMICROELECTRONICS (ROUSSET) SASInventors: Roberto Simola, Pascal Fornara
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Patent number: 9954120Abstract: In a semiconductor device including a split gate type MONOS memory, and a trench capacitor element having an upper electrode partially embedded in trenches formed in the main surface of a semiconductor substrate, merged therein, the flatness of the top surface of the upper electrode embedded in the trench is improved. The polysilicon film formed over the semiconductor substrate to form a control gate electrode forming a memory cell of the MONOS memory is embedded in the trenches formed in the main surface of the semiconductor substrate in a capacitor element formation region, thereby to form the upper electrode including the polysilicon film in the trenches.Type: GrantFiled: July 27, 2017Date of Patent: April 24, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventor: Atsushi Amo
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Patent number: 9954121Abstract: Examples of the various techniques introduced here include, but not limited to, a mesa height adjustment approach during shallow trench isolation formation, a transistor via first approach, and a multiple absorption layer approach. As described further below, the techniques introduced herein include a variety of aspects that can individually and/or collectively resolve or mitigate one or more traditional limitations involved with manufacturing PDs and transistors on the same substrate, such as above discussed reliability, performance, and process temperature issues.Type: GrantFiled: November 16, 2016Date of Patent: April 24, 2018Assignee: Artilux Inc.Inventors: Szu-Lin Cheng, Shu-Lu Chen