Patents Issued in April 24, 2018
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Patent number: 9953870Abstract: A 3D integrated circuit device, including: a first transistor; a second transistor; and a third transistor, where the third transistor is overlaying the second transistor and the third transistor is controlled by a third control line, where the second transistor is overlaying the first transistor and the second transistor is controlled by a second control line, where the first transistor is part of a control circuit controlling the second control line and the third control line, and where the second transistor and the third transistor are self-aligned.Type: GrantFiled: April 16, 2017Date of Patent: April 24, 2018Assignee: MONOLITHIC 3D INC.Inventors: Zvi Or-Bach, Deepak C. Sekar, Brian Cronquist, Zeev Wurman
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Patent number: 9953871Abstract: A laser beam is applied to the front side of a wafer along division lines, to form grooves having a depth corresponding to a finished thickness of device chips. Molding resin is laid on the front side of the wafer and embedded in the grooves. A protective member is attached to a front side of the molding resin, and a back side of the wafer is ground to expose the grooves and to expose the molding resin embedded in the grooves on the back side of the wafer. The wafer is divided along the grooves by a cutting blade having a thickness smaller than the width of the grooves, a central portion in a width direction of the molding resin being exposed along the grooves, thereby dividing the wafer into individual device chips each having a periphery surrounded with the molding resin.Type: GrantFiled: November 2, 2016Date of Patent: April 24, 2018Assignee: DISCO CORPORATIONInventors: Tsubasa Obata, Yohei Yamashita
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Patent number: 9953872Abstract: Embodiments of the present invention provide a semiconductor structure having a strain relaxed buffer, and method of fabrication. A strain relaxed buffer is disposed on a semiconductor substrate. A silicon region and silicon germanium region are disposed adjacent to each other on the strain relaxed buffer. An additional region of silicon or silicon germanium provides quantum well isolation.Type: GrantFiled: September 8, 2017Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES INC.Inventor: David P. Brunco
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Patent number: 9953873Abstract: Chip structures and fabrication methods for forming such chip structures. A first device structure has a structural feature comprised of a first dielectric material and a second device structure has a structural feature comprised of a second dielectric material. A semiconductor layer has a first section adjacent to the structural feature of the first device structure and a second section adjacent to the structural feature of the second device structure. The first section of the semiconductor layer has a popped relationship relative to the structural feature comprised of the first dielectric material. The second section of the semiconductor layer includes a portion that has a pinned relationship relative to a portion of the structural feature comprised of the second dielectric material.Type: GrantFiled: May 24, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Bhupesh Chandra, Claude Ortolland, Gregory G. Freeman, Viorel Ontalus, Christopher D. Sheraw, Timothy J. McArdle, Paul Chang
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Patent number: 9953874Abstract: An embodiment is a method including forming a multi-layer stack over a substrate, the multi-layer stack including alternating first layers and second layers, patterning the multi-layer stack to form a fin, forming an isolation region surrounding the fin, an upper portion of the fin extending above a top surface of the isolation region, forming a gate stack on sidewalls and a top surface of the upper portion of the fin, the gate stack defining a channel region of the fin, and removing the first layers from the fin outside of the gate stack, where after the removing the first layers, the channel region of the fin includes both the first layers and the second layers.Type: GrantFiled: October 5, 2016Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Che-Cheng Chang, Chih-Han Lin, Horng-Huei Tseng
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Patent number: 9953875Abstract: A method of forming a semiconductor device includes forming fin regions on a substrate, forming a patterned polysilicon structure over the fin regions, and etching back portions of the fin regions to form recessed fin regions. The method further includes forming a merged epitaxial region on the recessed fin regions and forming a capping layer on the merged epitaxial region using an etching gas and a deposition gas. The forming of the capping layer may include epitaxially growing a material of the capping layer faster along a first crystal direction of the capping layer than a second crystal direction of the capping layer by adjusting a ratio of a concentration of a first element in the etching gas to a concentration of a second element in the deposition gas, the first and second elements being different from each other, the first and second crystal directions being different from each other.Type: GrantFiled: April 21, 2017Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANYInventors: Cheng-Wen Cheng, Chii-Horng Li, Lilly Su, Tuoh Bin Ng
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Patent number: 9953876Abstract: The present disclosure provides a method of forming a semiconductor device structure including forming a first gate stack comprising a first gate dielectric material and a first gate electrode material over a first active region in an upper portion of a substrate, forming a first spacer structure adjacent to the first gate stack, and forming first raised source/drain (RSD) regions at opposing sides of the first gate stack on the first active region in alignment with the first spacer structure. Herein, forming the first spacer structure includes forming a first spacer structure on sidewalls of the first gate stack, the first gate dielectric extending in between the first spacer and the upper surface portion, patterning the first gate dielectric material, and forming a second spacer over the first spacer and the patterned first gate dielectric material.Type: GrantFiled: September 30, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: Elliot John Smith, Hans-Juergen Thees
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Patent number: 9953877Abstract: A method of forming a semiconductor device includes: providing a first substrate, forming at least one transistor on a first surface of the first substrate; forming a first dielectric cap layer covering the first surface of the first substrate; forming a first interconnect structure on the first dielectric cap layer; providing a carrier substrate; bonding the carrier substrate to the first substrate through the first dielectric cap layer; and from a second surface of the first substrate opposite to the first surface, thinning the first substrate to a second depth.Type: GrantFiled: January 14, 2016Date of Patent: April 24, 2018Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Herb He Huang, Haiting Li, Jiguang Zhu, Clifford Ian Drowley
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Patent number: 9953878Abstract: A method of forming a semiconductor device is provided. The method includes forming a recess in a substrate and forming a first dielectric layer in the recess. A portion of the first dielectric layer is removed. A second dielectric layer is formed over the first dielectric layer. A gate structure is formed over the second dielectric layer.Type: GrantFiled: February 4, 2016Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Yu-Lien Huang, Tung Ying Lee, Pei-Yi Lin, Chun-Hsiang Fan, Sheng-Wen Yu, Neng-Kuo Chen, Ming-Huan Tsai
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Patent number: 9953879Abstract: A semiconductor structure includes a strain-relaxed semiconductor substrate, fins on the strain-relaxed semiconductor substrate, the fins each having a bottom inactive region and an exposed top active region. The semiconductor structure further includes a liner layer along sidewalls of the bottom inactive region and adjacent surface areas of the strain-relaxed semiconductor substrate, a densified local fill layer surrounding the bottom inactive regions of the plurality of fins, a densified global fill layer adjacent outer sidewalls of the densified local fill layer, and a hard mask layer separating the densified global fill layer from the substrate and the densified local fill layer, a lack of voids in the densified local fill layer resulting in the bottom inactive regions of the fins being substantially free of oxidation defects. A method to realize the structure is also disclosed, the method preventing oxidation defects in strain-relaxed fins by reducing local gap fill voids.Type: GrantFiled: October 3, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES INC.Inventors: Min Gyu Sung, Hoon Kim, Chanro Park, Ruilong Xie
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Patent number: 9953880Abstract: A method for fabricating semiconductor device includes the steps of: forming a fin-shaped structure on a substrate; forming a shallow trench isolation (STI) around the fin-shaped structure; forming a gate layer on the fin-shaped structure and the STI; removing part of the gate layer, part of the fin-shaped structure, and part of the STI to form a trench; and forming a dielectric layer into the trench to form a single diffusion break (SDB) structure.Type: GrantFiled: July 27, 2017Date of Patent: April 24, 2018Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chun-Hao Lin, Hsin-yu Chen, Shou-Wei Hsieh
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Patent number: 9953881Abstract: The present disclosure provides a method, which includes forming a first fin structure and a second fin structure over a substrate, which has a first trench positioned between the first and second fin structures. The method also includes forming a first dielectric layer within the first trench, recessing the first dielectric layer to expose a portion of the first fin structure, forming a first capping layer over the exposed portion of the first fin structure and the recessed first dielectric layer in the first trench, forming a second dielectric layer over the first capping layer in the first trench while the first capping layer covers the exposed portion of the first fin feature and removing the first capping layer from the first fin structure.Type: GrantFiled: July 20, 2015Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Ying-Keung Leung
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Patent number: 9953882Abstract: Methods for forming a NW with multiple devices having alternate channel materials and resulting devices are disclosed. Embodiments include forming a first stack of semiconductor layers including a first doped Si layer, a first channel layer, and a second doped Si layer, respectively, on a Si substrate; forming a second stack including a first doped SiGe layer, a second channel layer, and a second doped SiGe layer, respectively, on the first stack; forming a vertical nanowire structure by directional etching, along a three-dimensional plane, the second and first stacks, respectively, down to an upper surface of the Si substrate; forming lower S/D regions and a lower gate-stack surrounding the first stack; forming upper S/D regions and an upper gate-stack surrounding the second stack; and forming contacts to the lower S/D regions, a first gate electrode, an upper S/D region, an upper gate electrode, and the second doped SiGe layer.Type: GrantFiled: October 24, 2017Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES INC.Inventor: Ajey P. Jacob
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Patent number: 9953883Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on a substrate, the semiconductor layer including a first semiconductor material and a second semiconductor material, patterning the semiconductor layer to form a preliminary active pattern, oxidizing at least two sidewalls of the preliminary active pattern to form an oxide layer on each of the at least two sidewalls of the preliminary active pattern, at least two upper patterns and a semiconductor pattern being formed in the preliminary active pattern when the oxide layers are formed, the semiconductor pattern being disposed between the at least two upper patterns, and removing the semiconductor pattern to form an active pattern, the active pattern including the at least two upper patterns. A concentration of the second semiconductor material in each of the at least two upper patterns is higher than a concentration of the second semiconductor material in the semiconductor pattern.Type: GrantFiled: January 25, 2017Date of Patent: April 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Mirco Cantoro, Maria Toledano Luque, Yeoncheol Heo, Dong Il Bae
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Patent number: 9953884Abstract: In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region includes at least one fin including strained germanium. The n-type field effect transistor region also includes at least one fin including strained germanium.Type: GrantFiled: November 16, 2016Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Kangguo Cheng, Pouya Hashemi, Alexander Reznicek
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Patent number: 9953885Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate including a top surface; forming a first insulation region and a second insulation region in the semiconductor substrate; and recessing the first insulation region and the second insulation region. Top surfaces of remaining portions of the first insulation region and the second insulation region are flat surfaces or divot surfaces. A portion of the semiconductor substrate between and adjoining removed portions of the first insulation region and the second insulation region forms a fin.Type: GrantFiled: July 26, 2010Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng Yuan, Tsung-Lin Lee, Hung-Ming Chen, Chang-Yun Chang
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Patent number: 9953886Abstract: The present disclosure relates to semiconductor manufacturing, in particular to a real-time method for qualifying the etch rate for plasma etch processes. A method for testing a semiconductor plasma etch chamber may include: depositing a film on a substrate of a wafer, the wafer including a center region and an edge region; depositing photoresist on top of the film in a pattern that isolates the center region from the edge region of the wafer; and performing an etch process on the wafer that includes at least three process steps. The three process steps may include: etching the film in any areas without photoresist covering the areas until a first clear endpoint signal is achieved; performing an in-situ ash to remove any photoresist; and etching the film in any areas exposed by the removal of the photoresist until a second clear endpoint is achieved.Type: GrantFiled: August 19, 2016Date of Patent: April 24, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Justin Hiroki Sato, Brian Dee Hennes, Yannick Carll Kimmel
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Patent number: 9953887Abstract: In situ wafer metrology is conducted to reliably obtain deposition thickness for each successive layer in a multi-layer deposition. A wafer to be processed is positioned in a processing station of a deposition process tool, the process tool having a reflectometer metrology apparatus for optically determining thickness of a deposited layer on the wafer. Prior to commencing a deposition, the wafer is aligned in the processing station such that an optical metrology spot generated by the reflectometer metrology apparatus will align with an unpatterned central region of a die on a wafer during a deposition conducted on the wafer in the tool. Thereafter, the thickness of a deposited layer on the wafer is reliably measured and monitored in situ.Type: GrantFiled: April 15, 2016Date of Patent: April 24, 2018Assignee: LAM RESEARCH CORPORATIONInventors: Boaz Kenane, Edward Augustyniak
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Patent number: 9953888Abstract: An electromagnetic detection device is provided. The electromagnetic detection device includes an induction coil, a converter, and a controller. The induction coil is utilized to sense an RF signal and generate a sensing RF signal by electromagnetic induction of the induction coil which is proportional to the RF signal. The RF signal is transmitted to a shower head to perform a semiconductor process on a wafer for manufacturing an IC in association with the RF signal. The converter is utilized to convert the sensing RF signal into a DC signal. The controller is utilized to determine whether the semiconductor process is normal or abnormal according to the DC signal during the semiconductor process. The semiconductor process will be terminated when the semiconductor process is determined as abnormal.Type: GrantFiled: December 15, 2016Date of Patent: April 24, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Wei Fang, Yao-Fong Dai, Chih-Tung Lo, Ming-Hsien Tsai, Kai-Wen Wu
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Patent number: 9953889Abstract: Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of GATECNT-GATE via opens.Type: GrantFiled: September 30, 2016Date of Patent: April 24, 2018Assignee: PDF Solutions, Inc.Inventors: Stephen Lam, Dennis Ciplickas, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De, Kelvin Doong, Hans Eisenmann, Timothy Fiscus, Jonathan Haigh, Christopher Hess, John Kibarian, Sherry Lee, Marci Liao, Sheng-Che Lin, Hideki Matsuhashi, Kimon Michaels, Conor O'Sullivan, Markus Rauscher, Vyacheslav Rovner, Andrzej Strojwas, Marcin Strojwas, Carl Taylor, Rakesh Vallishayee, Larg Weiland, Nobuharu Yokoyama
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Patent number: 9953890Abstract: A semiconductor device includes an insulating substrate on which semiconductor elements are mounted and a surrounding case in which the insulating substrate is housed. Two terminal conductors, both ends of each of which are fixed in sidewalls of the surrounding case, are provided between the sidewalls, and connection terminals protruding toward the insulating substrate side are provided on the respective terminal conductors. The connection terminals and a conductive foil on the insulating substrate are soldered together. Insulating blocks for keeping the distance between the adjacent terminal conductors at a fixed distance or greater are provided in the vicinity of the central portion of the terminal conductor. The insulating blocks suppress the terminal conductor being deformed by being thermally expanded when soldering. Because of this, it is possible to stabilize solderability, and it is possible to prevent an occurrence of defective connection.Type: GrantFiled: March 6, 2015Date of Patent: April 24, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventor: Hideaki Takahashi
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Patent number: 9953891Abstract: A method includes coating a passivation layer overlying a semiconductor substrate and forming an interconnect layer overlying the passivation layer. The interconnect layer includes a line region and a landing pad region. The method further includes forming a metallic layer including tin on a surface of the interconnect layer using an immersion process, forming a protective layer on the metallic layer, and exposing a portion of the metallic layer on the landing pad region of the interconnect layer through the protective layer.Type: GrantFiled: July 23, 2015Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yi-Wen Wu, Zheng-Yi Lim, Ming-Che Ho, Chung-Shi Liu
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Patent number: 9953892Abstract: A structure includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with a top surface of the device die, and a cavity in the encapsulating material. The cavity penetrates through the encapsulating material.Type: GrantFiled: May 2, 2016Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hung-Yi Kuo, Chen-Hua Yu, Hao-Yi Tsai
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Patent number: 9953893Abstract: A method of producing a power electronic assembly and a power electronic assembly including a power electronic module incorporating multiple of semiconductor power electronic switch components, the power electronic module including a base plate with a bottom surface, the power electronic assembly includes further a cooling arrangement for cooling the power electronic module, the cooling arrangement including a cooling surface adapted to be attached against the bottom surface of the base plate of the power electronic module, wherein the power electronic assembly includes further a thermal interface material arranged between the bottom surface of the base plate of the power electronic module and the cooling surface of the cooling arrangement to transfer heat from the power electronic module to the cooling arrangement, the thermal interface material includes a metal foil and a solid lubricant coating.Type: GrantFiled: November 2, 2016Date of Patent: April 24, 2018Assignee: ABB Technology OyInventors: Jorma Manninen, Pirkka Myllykoski
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Patent number: 9953894Abstract: A semiconductor device including: a semiconductor element, a substrate having a first surface on which the semiconductor element is provided, and a second surface located opposite the first surface, a metal species provided on the second surface, and a plated metal portion provided at least in part on the second surface on the metal species. The semiconductor device further includes a first region where the plated metal portion is provided and a second region where the plated metal portion is not provided are alternately arranged at a peripheral portion of the second surface.Type: GrantFiled: March 1, 2017Date of Patent: April 24, 2018Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Shingo Masuko, Yoshiharu Takada, Kazuo Fujimura
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Patent number: 9953895Abstract: A method of manufacturing a heat pipe, including the steps of: forming in a substrate a cylindrical opening provided with a plurality of ring-shaped recessed radially extending around a central axis of the opening; arranging in the recesses separate ring-shaped strips made of a material catalyzing the growth of carbon nanotubes; and growing carbon nanotubes in the opening from said ring-shaped strips.Type: GrantFiled: March 10, 2015Date of Patent: April 24, 2018Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS (CROLLES 2) SASInventors: Pascal Ancey, Simon Gousseau, Olga Kokshagina
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Patent number: 9953896Abstract: The present application provides a heat dissipating module, a heat dissipating system and a circuit module. The heat dissipating module adapted to be used with a heat element. The heat dissipating module comprises a heat exchanger which has a heat exchanging zone contacted with the heat element; a securing structure; and a fluid driving unit which is communicated with the heat exchanger for guiding a working fluid into the heat exchanger and is secured to the heat exchanger by the securing structure, wherein the fluid driving unit and the second heat exchanger are separately installed and communicated with each other.Type: GrantFiled: April 7, 2016Date of Patent: April 24, 2018Assignee: COOLER MASTER TECHNOLOGY INC.Inventors: Chang-han Tsai, Shui-Fa Tsai
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Patent number: 9953897Abstract: A device comprises a first layer of a die. The first layer comprises a microchannel. The microchannel is partially filled with a liquid and partially filled with air. The die also comprises a second layer. The second layer of the die seals a top of the microchannel of the first layer.Type: GrantFiled: July 22, 2016Date of Patent: April 24, 2018Assignee: Hewlett Packard Enterprise Development LPInventors: Niru Kumari, Sergio Escobar-Vargas
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Patent number: 9953898Abstract: A flow channel member according to the present invention includes a ceramic substrate, a flow channel inside the ceramic substrate through which a fluid flows, and multiple protrusions on an outer surface of the substrate.Type: GrantFiled: May 25, 2015Date of Patent: April 24, 2018Assignee: KYOCERA CorporationInventors: Masayuki Moriyama, Yuusaku Ishimine, Kazuhiko Fujio, Keiichi Sekiguchi
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Patent number: 9953899Abstract: Embodiments of the present invention are directed to heat transfer arrays, cold plates including heat transfer arrays along with inlets and outlets, and thermal management systems including cold-plates, pumps and heat exchangers. These devices and systems may be used to provide cooling of semiconductor devices and particularly such devices that produce high heat concentrations. The heat transfer arrays may include microjets, microchannels, fins, and even integrated microjets and fins.Type: GrantFiled: September 30, 2016Date of Patent: April 24, 2018Assignee: Microfabrica Inc.Inventors: Richard T. Chen, Will J. Tan
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Patent number: 9953900Abstract: Device structures involving a conductor-filled via or trench, methods of forming such device structures, and methods of operating such device structures. A doped region is formed in the substrate. An opening, such as a via or trench, is formed that extends through the doped region and into a portion of the substrate beneath the doped region. A conductive plug in formed in the opening to provide the conductor-filled via or trench. The opening is positioned and dimensioned relative to a position and dimensions of the doped region to divide the doped region into a first section and a second section that is disconnected from the first section by the opening.Type: GrantFiled: March 29, 2016Date of Patent: April 24, 2018Assignee: GLOBALFOUNDRIES Inc.Inventors: John M. Safran, Sami Rosenblatt, Michael S. Cranmer, Chandrasekharan Kothandaraman
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Patent number: 9953901Abstract: A semiconductor light emitting device includes a semiconductor light source, a resin package surrounding the semiconductor light source, and a lead fixed to the resin package. The lead is provided with a die bonding pad for bonding the semiconductor light source, and with an exposed surface opposite to the die bonding pad The exposed surface is surrounded by the resin package in the in-plane direction of the exposed surface.Type: GrantFiled: March 13, 2017Date of Patent: April 24, 2018Assignee: ROHM CO., LTD.Inventors: Masahiko Kobayakawa, Kazuhiro Mireba, Shintaro Yasuda, Junichi Itai, Taisuke Okada
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Patent number: 9953902Abstract: A semiconductor device includes first and second conductive layers on a substrate and separated from each other. A first semiconductor chip is mounted on the first conductive layer and has a first electrode on a side opposite the first conductive layer. A second semiconductor chip is mounted on the first conductive layer and has a second electrode on a side opposite the first conductive layer. A first metal member is mounted on the first electrode. A second metal member is mounted on the second electrode. A metal plate has a first portion disposed on the first and second metal members, and a second portion connected to the second conductive layer. The metal plate electrically connects the first and second electrodes to the second conductive layer through the first and second metal members.Type: GrantFiled: August 29, 2016Date of Patent: April 24, 2018Assignee: Kabushiki Kaisha ToshibaInventors: Shigeaki Hayase, Hiroshi Matsuyama
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Patent number: 9953903Abstract: Consistent with an example embodiment, there is a method for preparing an integrated circuit (IC) device having enhanced heat dissipation. The method comprises providing a lead frame array, of a first thickness, with a plurality of die placement areas each die placement area with bond pad landings, the bond bad landings situated about a die placement area on one or multiple sides, the bond pad landings having upper surfaces and opposite lower surfaces, placing a heat sink assembly of a second thickness, having at least two mounting tabs of the first thickness, in each die placement area and attaching the at least two mounting tabs onto corresponding bond pad landings serving as anchor pads, die bonding a device die on the heat sink device assembly, conductively bonding device die bond pads to corresponding bond pad landings, and encapsulating the wire bonded device die, heat sink assembly and lead frame array in a molding compound.Type: GrantFiled: July 22, 2015Date of Patent: April 24, 2018Assignee: NXP B.V.Inventors: Leonardus Antonius Elisabeth van Gemert, Tonny Kamphuis, Rintje van der Meulen, Emil Casey Israel
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Patent number: 9953904Abstract: An electronic component package that includes a heat spreader with a die pad. An electronic component is attached to each side of the die pad where each electronic component includes conductive terminals on a side facing away from the die pad. Conductive terminals of the top electronic component are wirebonded to conductive surfaces of a package substrate and conductive terminals of the bottom electronic component are physically and electrically attached to conductive surfaces of the package substrate. The heat spreader structure includes tie structures that extend in a direction away from the second electronic component.Type: GrantFiled: October 25, 2016Date of Patent: April 24, 2018Assignee: NXP USA, INC.Inventors: Navas Khan Oratti Kalandar, Akhilesh Kumar Singh, Nishant Lakhera
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Patent number: 9953905Abstract: A semiconductor device includes a substrate, a semiconductor element, a terminal and a solder outflow prevention part. The semiconductor element is fixed on one side of the substrate via a first solder layer. The terminal that is fixed on the one side of the substrate via a second solder layer. The solder outflow prevention part is formed between the semiconductor element and the terminal in the one side of the substrate and is configured to prevent the first solder layer and the second solder layer from outflowing. A distance between the solder outflow prevention part and the semiconductor element is longer than a thickness of the first solder layer.Type: GrantFiled: November 11, 2014Date of Patent: April 24, 2018Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takuya Kadoguchi, Takanori Kawashima
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Patent number: 9953906Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate which has a plurality of element regions and of which an element surface is covered by insulating film, the substrate is divided into element chips by exposing the substrate to a first plasma, element chips having first surface, second surface, and side surface are held spaced from each other on carrier, insulating film is in a state of being exposed, recessed portions are formed by retreating insulating film by exposing element chips to second plasma for ashing, and then recessed portions are covered by protection films by third plasma for formation of the protection film, thereby suppressing creep-up of the conductive material to side surface in the mounting step.Type: GrantFiled: January 18, 2017Date of Patent: April 24, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara
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Patent number: 9953907Abstract: A method of forming a PoP device comprises placing an adhesive layer on a carrier substrate, coupling a plurality of chip packages to the adhesive layer on the carrier substrate, placing a bonding layer on the chip packages, and coupling a plurality of chips to the bonding layer on the chip packages. The method further comprises injecting a molding compound to encapsulate the chip packages and the chips on the carrier substrate, grinding the molding compound to expose a plurality of connecting elements of the chips and a plurality of second connecting elements of the chip packages, forming a redistribution layer (RDL) on the molding compound and the exposed connecting elements and second connecting elements, forming a ball grid array (BGA) on the RDL, and de-bonding the carrier substrate.Type: GrantFiled: January 29, 2013Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Chuan Chang, Jing-Cheng Lin, Nai-Wei Liu, Wan-Ting Shih
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Patent number: 9953908Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.Type: GrantFiled: October 30, 2015Date of Patent: April 24, 2018Assignee: International Business Machines CorporationInventors: Eric P. Lewandowski, Jae-Woong Nah, Peter J. Sorce
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Patent number: 9953909Abstract: Embodiments herein may relate to an electronic device that includes a board. The electronic device may include a device physically coupled with the board by an anchoring pin. The electronic device may further include a plurality of ball grid array (BGA) solder joints coupled with the device. For example, the BGA solder joints may electrically and/or communicatively couple one or more pins of the device with the board. The BGA solder joints may have a shape that is different than the anchoring pin. Other embodiments may be described and/or claimed.Type: GrantFiled: July 18, 2016Date of Patent: April 24, 2018Assignee: Intel CorporationInventors: Zuyang Liang, Michael Garcia, Joshua D. Heppner, Srikant Nekkanty
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Patent number: 9953910Abstract: An electronic component includes a base insulative layer having first and second surfaces; an electronic device having first and second surfaces; at least one I/O contact located on the first surface of the electronic device; an adhesive layer disposed between the first surface of the electronic device and the second surface of the base insulative layer; a first metal layer disposed on the I/O contact; and a removable layer disposed between the first surface of the electronic device and the second surface of the base insulative layer, and located adjacent to the first metal layer. The base insulative layer secures to the electronic device through the first metal layer and removable layer. The first metal layer and removable layer can release the base insulative layer from the electronic device when the first metal layer and removable layer are exposed to a temperature higher than their softening points or melting points.Type: GrantFiled: April 2, 2008Date of Patent: April 24, 2018Assignee: General Electric CompanyInventors: Charles Gerard Woychik, Raymond Albert Fillion
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Patent number: 9953911Abstract: A method includes attaching a semiconductor structure on a carrier, depositing a molding compound layer over the carrier, wherein the semiconductor structure is embedded in the molding compound layer, exposing a first photo-sensitive material layer and a second photo-sensitive material layer to light, developing the first photo-sensitive material layer and the second photo-sensitive material layer to form an opening having a first portion in the first photo-sensitive material layer and a second portion in the second photo-sensitive material layer, wherein a width of the second portion is greater than a width of the first portion, filling the opening with a conductive material to form a via in the first photo-sensitive material layer and a redistribution layer in the second photo-sensitive material layer and forming a bump over the redistribution layer.Type: GrantFiled: July 1, 2016Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tzu-Wei Chiu, Sao-Ling Chiu
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Patent number: 9953912Abstract: Work pieces and methods of forming through holes in substrates are disclosed. In one embodiment, a method of forming a through hole in a substrate by drilling includes affixing an exit sacrificial cover layer to a laser beam exit surface of the substrate, positioning a laser beam in a predetermined location relative to the substrate and corresponding to a desired location for the through hole, and forming the through hole by repeatedly pulsing the laser beam into an entrance surface of the substrate and through a bulk of the substrate. The method further includes forming a hole in the exit sacrificial cover layer by repeatedly pulsing the laser beam into the through hole formed in the substrate such that the laser beam passes through the laser beam exit surface of the substrate and into the exit sacrificial cover layer.Type: GrantFiled: April 26, 2016Date of Patent: April 24, 2018Assignee: Corning IncorporatedInventor: Uta-Barbara Goers
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Patent number: 9953913Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through component coupled to the first side of the insulating substrate. The pass-through component includes an insulating core and at least one through-hole structure comprising a conductive body extending through the thickness of the insulating core. A metallization layer is formed on a second side of the insulating substrate and extends through at least one via in the insulating substrate to electrically couple at least one conductive pad on the top surface of the semiconductor device to the at least one through-hole structure. An insulating material surrounds the semiconductor device and the insulating core of the pass-through component.Type: GrantFiled: December 12, 2016Date of Patent: April 24, 2018Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Raymond Albert Fillion, Paul Alan McConnelee
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Patent number: 9953914Abstract: A method for making a microelectronic unit includes forming a plurality of wire bonds on a first surface in the form of a conductive bonding surface of a structure comprising a patternable metallic element. The wire bonds are formed having bases joined to the first surface and end surfaces remote from the first surface. The wire bonds have edge surfaces extending between the bases and the end surfaces. The method also includes forming a dielectric encapsulation layer over a portion of the first surface of the conductive layer and over portions of the wire bonds such that unencapsulated portions of the wire bonds are defined by end surfaces or portions of the edge surfaces that are unconvered by the encapsulation layer. The metallic element is patterned to form first conductive elements beneath the wire bonds and insulated from one another by portions of the encapsulation layer.Type: GrantFiled: February 11, 2016Date of Patent: April 24, 2018Assignee: Invensas CorporationInventor: Ilyas Mohammed
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Patent number: 9953915Abstract: An interconnect structure includes a first dielectric layer and a second dielectric layer each extending along a first axis to define a height and a second axis opposite the first axis to define a length. A capping layer is interposed between the first dielectric layer and the second dielectric layer. At least one electrically conductive feature is embedded in at least one of the first dielectric layer and the second dielectric layer. At least one electrically conductive via extends through the second dielectric layer and the capping layer. The via has an end that contacts the conductive feature. The end includes a flange having at least one portion extending laterally along the first axis to define a contact area between the via and the at least one conductive feature.Type: GrantFiled: November 30, 2016Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hsueh-Chung Chen, James J. Demarest, Sean Teehan, Chih-Chao Yang
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Patent number: 9953916Abstract: A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask includes first and second insulating layers and a metal layer in between the insulating layers; defining a trench pattern through the first insulating layer and metal layer, the trench pattern having a first width; defining a first via pattern in a lithographic mask over the trench pattern, the first via pattern having a second width that is larger than the first width; growing a metal capping layer on an exposed sidewall of the trench pattern to decrease the first width to a third width that defines a second via pattern; transferring the trench pattern into the ILD layer to form a trench; and transferring the second via pattern through the ILD layer and into the metal wiring layer to form a via.Type: GrantFiled: February 3, 2017Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Hsueh-Chung H. Chen, Hong He, Juntao Li, Chih-Chao Yang, Yunpeng Yin
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Patent number: 9953917Abstract: An electronics package includes an insulating substrate, a semiconductor device having a top surface coupled to a first side of the insulating substrate, and a pass-through structure coupled to the first side of the insulating substrate. The pass-through structure includes an insulating core, a resistor disposed proximate a top surface of the insulating core, and at least one through-hole structure forming at least one conductive pathway through a thickness of the insulating core. A patterned metallization layer is formed on a second side of the insulating substrate. The patterned metallization layer is electrically coupled to at least one first conductive pad of the semiconductor device and electrically couples at least one second conductive pad of the semiconductor device to a through-hole structure of the at least one through-hole structure through the resistor.Type: GrantFiled: December 12, 2016Date of Patent: April 24, 2018Assignee: General Electric CompanyInventors: Arun Virupaksha Gowda, Raymond Albert Fillion, Paul Alan McConnelee
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Patent number: 9953918Abstract: A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.Type: GrantFiled: January 11, 2017Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li
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Patent number: 9953919Abstract: An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.Type: GrantFiled: August 4, 2016Date of Patent: April 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Hyun-Min Choi