Abstract: Realization of an adequate hole accumulation layer and reduction in dark current are allowed to become mutually compatible. A solid-state imaging device 1 having a light-receiving portion 12 to photoelectrically convert incident light is characterized by including a film 21, which is disposed on a light-receiving surface 12s of the above-described light-receiving portion 12 and which lowers an interface state, and a film 22, which is disposed on the above-described film 21 to lower the interface state and which has a negative fixed charge, wherein a hole accumulation layer 23 is disposed on the light-receiving surface 12s side of the light-receiving portion 12.

Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.

Abstract: A solid-state imaging device includes a first substrate and a second substrate electrically connected to the first substrate. The first substrate includes a first semiconductor layer and one or more first wiring layers. The second substrate includes a second semiconductor layer and one or more second wiring layers. The first photoelectric conversion element overlaps any of the one or more first wiring layers at all positions on the first photoelectric conversion element in a planar view of the first substrate. The second photoelectric conversion element does not overlap any of the one or more first wiring layers at some positions on the second photoelectric conversion element in the planar view of the first substrate.

Abstract: The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.

Abstract: An image sensor having pixels that include two patterned semiconductor layers. The top patterned semiconductor layer contains the photoelectric elements of pixels having substantially 100% fill-factor. The bottom patterned semiconductor layer contains transistors for detecting, resetting, amplifying and transmitting signals charges received from the photoelectric elements. The top and bottom patterned semiconductor layers may be separated from each other by an interlayer insulating layer that may include metal interconnections for conducting signals between devices formed in the patterned semiconductor layers and from external devices.

Abstract: An imaging apparatus includes a pixel configured to generate a signal in accordance with an incident light by a photoelectric conversion; a differential amplifier including a first input terminal to which a voltage based on the signal from the pixel is input, and a second input terminal to which a reference voltage is input; a current supply unit configured to supply a bias current to the differential amplifier; and a comparing unit configured to compare the voltage of the first input terminal of the differential amplifier with a threshold voltage, and configured to output a control signal based on a comparison result to the current supply unit, and the current supply unit changes a magnitude of the bias current supplied to the differential amplifier in accordance with the control signal input from the comparing unit.

Abstract: A semiconductor device having a stacked structure formed by stacking a thinned first silicon substrate and a second silicon substrate supporting the first silicon substrate, wherein the first silicon substrate includes a first surface with a crystal surface orientation of (100) or (110) and a second surface opposite to the first surface, the second silicon substrate includes a third surface and a fourth surface that is opposite to the third surface and from which a silicon surface with a crystal surface orientation (111) is exposed, and wherein the semiconductor device is formed by etching silicon with a predetermined thickness in a direction from the first surface toward the second surface to make the first silicon substrate to be thinned, after bonding the first silicon substrate and the second silicon substrate in a state where the second surface and the third surface facing the second surface are bonded with each other.

Abstract: A light emitting device package includes a substrate for growth having a plurality of light-emitting windows, a plurality of semiconductor light-emitting units corresponding to the plurality of light-emitting windows, each semiconductor light-emitting unit having a first surface contacting the substrate for growth and a second surface opposite the first surface, and each semiconductor light-emitting unit having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer stacked on each other, a plurality of wavelength conversion units respectively disposed inside the plurality of light-emitting windows, each wavelength conversion unit is configured to provide light having a wavelength different from light emitted by the respective semiconductor light-emitting unit, a metal support layer disposed on at least one surface of each of the plurality of semiconductor light-emitting units and having a lateral surface coplanar with a lateral surface of the substra

Abstract: According to one embodiment, a resistance change memory includes a semiconductor layer having a first surface in a first direction and a second surface in a second direction crossing the first direction, extending in a third direction crossing the first and second directions, and having first and second portions, a gate electrode covering the first and second surfaces between the first and second portions, a first conductive line connected to the first portion, a resistance change element having first and second terminals, the first terminal connected to the second portion, a second conductive line connected to the second terminal, and a third conductive line connected to the gate electrode.

Abstract: A semiconductor apparatus includes a substrate, a first insulating layer on a logic region and a memory region of the substrate, a second insulating layer on the first insulating layer, a base insulating layer between the first insulating layer and second insulating layer over the logic region and the memory region, first interconnection structures passing the first insulating layer, second interconnection structures passing through the second insulating layer, a base interconnection structure passing through the base insulating layer over the logic region, and a variable resistance structure in the base insulating layer over the memory region. The variable resistance structure includes a lower electrode, a magnetoresistive device, and an upper electrode, which are sequentially stacked. The lower electrode and the upper electrode are electrically connected to one of the first interconnection structures and one of the second interconnection structures, respectively, over the memory region.

Abstract: A semiconductor device including a semiconductor substrate with a first surface and a second surface facing each other, the semiconductor substrate having an element region in which a transistor is provided on the first surface, and a separation region in which an element separating layer surrounding the element region is provided; a contact plug extending from the first surface to the second surface, in the element region of the semiconductor substrate; and an insulating film covering a periphery of the contact plug.

Abstract: A method for producing a memory device and semiconductor device includes forming pillar-shaped phase change layers and lower electrodes in two or more rows and two or more columns on a semiconductor substrate. A reset gate insulating film is formed that surrounds the pillar-shaped phase change layers and the lower electrodes, and a reset gate is formed that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns.

Abstract: A method for fabricating at least a portion of a complementary circuit, such as a complementary inverter circuit, includes fabricating a first sheet and a second sheet. Each of the sheets includes metal layers, a dielectric layer, and a semiconductor channel layer, configured so as to form a plurality of transistors of a respective polarity (i.e., P-type for one sheet, N-type for the other). The method also includes placing a layer of conductive material, such as anisotropic conducting glue (ACG) or anisotropic conducting foil (ACF), on the first sheet, and bonding at least a portion of the second sheet to the first sheet such that the conductive material is disposed between and in contact with the top-most metal layers of the first and second sheets. Separately fabricating the two sheets of different polarity may improve yields and/or decrease costs as compared to fabricating both polarities on a single substrate.

Abstract: An image sensor comprising: a first layer having a plurality of groups of photodiodes formed in a semiconductor substrate, each group representing a 2×2 array of photodiodes, with 2 first pixels configured to detect light of a first wavelength and 2 second pixels configured to detect light of a second wavelength, each first pixel positioned adjacent to the second pixels; and a second layer overlapping the first layer, the second layer is organic, having a plurality of organic photodiodes configured to detect light of a third wavelength, each organic photodiode positioned to partially overlap 2 first photodiodes and 2 second photodiodes of the first layer.

Abstract: An organic light-emitting diode (OLED) array substrate, a display device and a manufacturing method thereof are disclosed. The array substrate includes: a substrate and pixel units disposed on the substrate. Each pixel unit includes a plurality of subpixel units; each subpixel unit includes a composite electrode, an organic material functional layer and a first electrode sequentially disposed on the substrate; thicknesses of the composite electrodes of different subpixel units are different; and the composite electrode, the organic material functional layer and the first electrode in a same subpixel unit constitute a microcavity structure.

Abstract: A display device includes plural unit areas each of which includes low definition pixels as sub-pixels larger than a specified standard and high definition pixels as sub-pixels smaller than the specified standard and which are regularly arranged. The low definition pixels include a blue pixel and a red pixel, and the high definition pixels include a white pixel and a green pixel.

Abstract: The present disclosure discloses a display device, a method of manufacturing the same, a display method, and a wearable device. The display includes a first base substrate; a low-temperature polysilicon (LTPS) back plate formed on the first base substrate and provided with a switch control circuit; and a micro-electro-mechanical system (MEMS) microlens array formed at a non-display region of the first base substrate, wherein the MEMS microlens array is configured to reflect light emitted by a light-emitting structure at the display region, and the switch control circuit is configured to control the MEMS microlens array to be turned on and off; and the light-emitting structure formed at the display region of the first base substrate.

Abstract: An organic light-emitting device according to an embodiment of the present disclosure includes a first electrode, a second electrode opposite to the first electrode, a first light-emitter on the first electrode to emit first light of a first wavelength range, a second light-emitter between the first light-emitter and the second electrode, to emit second light of a second wavelength range, and a charge generation layer which includes a metal compound having a perovskite structure, is between the first light-emitter and the second light-emitter, and is to generate charges to provide to each of the first light-emitter and the second light-emitter.

Abstract: An organic light emitting display device can include a substrate; an anode electrode on the substrate; an organic emitting layer on the anode electrode; a cathode electrode on the organic emitting layer; an auxiliary electrode connected to the cathode electrode; a bank provided on either side of the auxiliary electrode; and a partition spaced apart from the bank and provided on the auxiliary electrode, in which the partition includes a plurality of first partitions provided on the auxiliary electrode and spaced apart from each other, and the partition further includes a second partition provided on the plurality of first partitions, and a width of an upper surface of the second partition is larger than a width of a lower surface of the second partition.

Abstract: Provided are an organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes a display substrate; a thin film transistor (TFT) on the display substrate; an organic light-emitting diode (OLED) electrically connected to the TFT and including a first electrode on sub-pixels of the display substrate, an intermediate layer on the first electrode, and a second electrode on the intermediate layer; a pixel-defining layer which includes an opening exposing at least a portion of the first electrode and defines each sub-pixel; and a sealing substrate covering the OLED, the intermediate layer including a plurality of stacked layers, and a cross-sectional width of the intermediate layer gradually decreasing in a direction perpendicular to the display substrate.

Abstract: An organic electroluminescence display device includes a substrate; a thin film transistor that is formed on the substrate; a light emitting region that has a lower electrode, a light emitting layer, and an upper electrode formed for each of a plurality of pixels arranged in a matrix shape on the thin film transistor; and a contact hole that is formed on the outside of the light emitting region in one corner portion of the pixel and connects the thin film transistor and the lower electrode for each pixel in a plan view. Only one pair of pixels of four pixels that share an intersection point of boundaries of the pixels arranged in the matrix shape, which are arranged in a diagonal manner have the contact holes at the corner portions having the intersection point.

Abstract: An organic light-emitting diode (OLED) display apparatus including a substrate, an insulation layer on the substrate, and an align mark formed of an insulation material, wherein an upper surface of the insulation layer contacts a lower surface of the align mark.

Abstract: The present disclosure relates to a flexible organic light emitting diode display having an edge bending structure. The organic light emitting diode display according to an embodiment includes a flexible plate including a display area, a non-display area surrounding the display area, and an edge bending area near the display area in the non-display area; a first line disposed in the non-display area on the flexible plate; a first buffer layer covering the first line; a second line on the first buffer layer in the non-display area; a second buffer layer covering the second line; gate elements disposed on the second buffer layer; an intermediate insulating layer covering the gate elements; data elements, and a connecting electrode connecting the first line to the second line on the intermediate insulating layer; and a plurality of trenches disposed at the edge bending area and penetrating the intermediate insulating layer, the second buffer layer and the first buffer layer.

Abstract: A display apparatus includes a first substrate including a channel-forming area, a second substrate facing the first substrate, a thin-film transistor disposed on the first substrate, a pixel electrode electrically connected to the thin-film transistor, a gate line disposed on the first substrate and electrically connected to the thin-film transistor, a data line electrically connected to the thin-film transistor and divided into at least two portions such that the channel-forming area is disposed between the two portions of the data line, and a connection portion electrically connecting the two portions of the data line to each other, in which the thin-film transistor includes a gate electrode branched from the gate line and overlapping the channel-forming area, a semiconductor pattern overlapping the gate electrode and contacting the two portions of the data line so that the channel-forming area is disposed in the semiconductor pattern, and a drain electrode electrically connected to the pixel electrode and

Abstract: Provided is an organic EL display device (electroluminescence device) including a TFT substrate (substrate) and an organic EL element (electroluminescence device) provided on the TFT substrate, wherein the organic EL display device includes a sealing layer that seals the organic EL element. The sealing layer is provided with a first, a second, and a third sealing film that are sequentially stacked from the organic EL element side, the first and third sealing films are each formed of an inorganic film, and the second sealing film is formed of an octamethylcyclotetrasiloxane film.

Abstract: A display apparatus including: a display region provided with a plurality of pixel portions; wires installed to the respective pixel portions within the display region from an outside of the display region for transmitting a signal to drive the respective pixel portions; connection pads provided on the outside of the display region and serving as input portions to provide the wires with a signal while electrically conducting with the wires; switch elements provided on the outside of the display region in a middle of the wires; and a light shielding covering portion shielding the switch elements from light and formed to cover the connection pads while electrically conducting with the connection pads.

Abstract: An organic light emitting display (OLED) device includes an organic light emitting diode having an anode and a cathode. The organic light emitting diode is configured to receive a reference voltage. A control transistor includes a first control electrode and a first semiconductor active layer. The control transistor is configured to receive a control signal. A driving transistor includes a second control electrode that is electrically connected to the control transistor, an input electrode that is configured to receive a power voltage, an output electrode that is electrically connected to the anode of the organic light emitting diode, and a second semiconductor active layer that includes a different material from that of the first semiconductor active layer. A shielding electrode is disposed on the second semiconductor active layer, overlapping the driving transistor, and configured to receive the power voltage.

Abstract: An organic light emitting display device includes: a substrate; a semiconductor on the substrate and including a switching channel of a switching transistor and a driving channel of a driving transistor, wherein the switching transistor and the driving transistor are spaced; a first insulating layer covering the semiconductor; a switching gate electrode on the first insulating layer and overlapped with the switching channel and a driving gate electrode on the first insulating layer and overlapped with the driving channel; a second insulating layer covering the switching gate electrode and the driving gate electrode; a data line on the second insulating layer and configured to transmit a data signal, a driving voltage line on the second insulating layer and configured to transmit a driving voltage; a passivation layer; a pixel electrode on the passivation layer; and a pixel connecting member on the passivation layer.

Abstract: The present invention relates to a circular display device including: a substrate (21) having a circular shape; a plurality of data lines (15) formed on the substrate; a plurality of gate lines (16) extending in a direction orthogonal to the plurality of data lines; a plurality of pixels (14) respectively formed at areas in which the plurality of data lines and the plurality of gate lines intersect; and a circular cover (25) that is air-tightly adhered to the substrate and covers the pixels. The cover has a driving integrated circuit (27) and a plurality of wiring patterns formed thereon, wherein the driving integrated circuit supplies scan signals and data signals to the plurality of pixels, and the wiring patterns extend and are drawn out from the driving integrated circuit. The respective plurality of wiring patterns are electrically connected to each of the plurality of data lines and the plurality of gate lines through connection wires (29).

Abstract: A resistive material is formed straddling over each semiconductor fin that extends upward from a surface of a substrate. The resistive material is then disconnected by removing the resistive material from atop each semiconductor fin. Remaining resistive material in the form of a U-shaped resistive material liner is present between each semiconductor fin. Contact structures are formed perpendicular to each semiconductor fin and contacting a portion of a first set of the semiconductor fins and a first set of the U-shaped resistive material liners.

Abstract: Methods of processing a substrate include: providing a substrate having a polymer dielectric layer, a metal pad formed within the polymer dielectric layer and a first metal layer formed atop the polymer dielectric layer; depositing a polymer layer atop the substrate; patterning the polymer layer to form a plurality of openings, wherein the plurality of openings comprises a first opening formed proximate the metal pad; depositing a first barrier layer atop the polymer layer; depositing a dielectric layer atop the first barrier layer; etching the dielectric layer and the first barrier layer from within the first opening and a field region of the polymer layer; depositing a second barrier layer atop the substrate; depositing a second metal layer atop the substrate wherein the second metal layer fills the plurality of openings; and etching the second metal layer from a portion of the field region of the polymer layer.

Abstract: A semiconductor device is provided as follows. A substrate includes an NMOS region and a PMOS region. A first trench and a second trench are disposed in the NMOS region. A first buffer layer is disposed in the first trench and the second trench. A stressor is disposed in the first trench and the second trench and disposed on the first buffer layer. A first channel region is disposed between the first trench and the second trench and disposed in the substrate. A first gate electrode is disposed on the first channel area. A third trench is disposed in the PMOS region. A second buffer layer is disposed in the third trench. A second channel area is disposed in the third trench, disposed on the second buffer layer, and has a different semiconductor layer from the substrate. A second gate electrode is disposed on the second channel area.

Abstract: A method of manufacturing a semiconductor device, including implanting hydrogen atoms from a second principal surface of a semiconductor substrate, forming a plurality of second semiconductor layers that each have a carrier concentration higher than that of the first semiconductor layer and that have carrier concentration peak values at different depths from the second principal surface of the semiconductor substrate, applying a heat treatment process to promote generation of donors from the hydrogen atoms, implanting an impurity from the second principal surface of the semiconductor substrate, forming a third semiconductor layer in the semiconductor substrate at the second principal surface thereof, and applying another heat treatment process to locally heat the semiconductor substrate, so as to reduce the carrier concentration at an interface between the third semiconductor layer and the second semiconductor layer adjacent to the third semiconductor layer.

Abstract: A fourth impurity region includes a first region facing a bottom portion of a trench and a part of a second impurity region and a second region facing the second impurity region. A first impurity region includes a third region in contact with a side surface of the trench, the second impurity region, the first region, and a second region and a fourth region which is located on a side of a second main surface relative to the third region, electrically connected to the third region, and lower in impurity concentration than the third region. A surface of the first region facing the second main surface is located on the side of the second main surface in a direction perpendicular to the second main surface relative to a surface of the second region facing the second main surface.

Abstract: A semiconductor device includes a layer having first and second surfaces and a first type first region, a second type second region in the layer between the first region and first surface, a first type third region in the layer between the second region and first surface, first and second gate electrodes, wherein the second region is between the first and second gate electrodes, a first field plate electrode between the second surface and first gate electrode, a second field plate electrode between the second surface and second gate electrode, a first film, at least a portion between the first field plate electrode and first region, a second film at least a portion between the second field plate electrode and first region, and a second type fourth region in the first region between the first and second films. A portion of the first region is between second and fourth regions.

Abstract: A semiconductor device includes a transistor cell region and a transition region. The transistor cell region includes a first portion of a super junction structure and a first contact structure electrically connecting a first load electrode with first source zones of transistor cells. The first source zones are formed on opposite sides of the first contact structure. The transition region directly adjoins to the transistor cell region and includes a second portion of the super junction structure and a second contact structure electrically connecting the first load electrode with a second source zone. The second source zone is formed only at a side of the second contact structure oriented to the transistor cell region.

Abstract: A semiconductor device having a high and stable operating voltage and a method of manufacturing the same, the semiconductor device including: a substrate having an active region including a channel region; a gate insulating layer that covers a top surface of the active region; a gate electrode that covers the gate insulating layer on the top surface of the active region; buried insulating patterns in the channel region of the active region at a lower side of the gate electrode and spaced apart from a top surface of the substrate; and a pair of source/drain regions in the substrate at both sides of each of the buried insulating patterns and extending from the top surface of the substrate to a level lower than that of each of the buried insulating patterns.

Abstract: A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner dielectric liner and an air gap are present. Collectively, each inner spacer and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.

Abstract: A semiconductor wafer is provided with a thick region extending along its outer circumferential surface and being greater in thickness than its central region. A main surface of the wafer includes a slope surface located between the central region and the thick region. The slope surface has an inner circumferential edge and an outer circumferential edge, and slopes such that the thickness of the wafer increases from the inner circumferential edges to the outer circumferential edge. The slope surface includes an inner circumferential portion including the inner circumferential edge, an outer circumferential portion including the outer circumferential edge and an intermediate portion located between the inner and the outer circumferential portions. At least one of slope angles of the inner and the outer circumferential portions is smaller than a slope angle of the intermediate portion.

Abstract: The present invention provides a method for aligning nanowires which can be used to fabricate devices comprising nanowires that has well-defined and controlled orientation independently on what substrate they are arranged on. The method comprises the steps of providing nanowires and applying an electrical field over the population of nanowires, whereby an electrical dipole moment of the nanowires makes them align along the electrical field. Preferably the nanowires are dispersed in a fluid during the steps of providing and aligning. When aligned, the nanowires can be fixated, preferably be deposition on a substrate. The electrical field can be utilized in the deposition. Pn-junctions or any net charge introduced in the nanowires may assist in the aligning and deposition process. The method is suitable for continuous processing, e.g. in a roll-to-roll process, on practically any substrate materials and not limited to substrates suitable for particle assisted growth.

Abstract: A semiconductor device includes an isolation pattern on a substrate, the isolation pattern having a lower insulating pattern on the substrate, and a spacer to cover side surfaces of the lower insulating pattern, a vertical structure through the isolation pattern to contact the substrate, the vertical structure having a first semiconductor layer on the substrate, a lower end of the first semiconductor layer being at a lower level than a lower surface of the isolation pattern, a second semiconductor layer on the first semiconductor layer, and a third semiconductor layer on the second semiconductor layer, and a gate electrode crossing the vertical structure and extending over the isolation pattern.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: A method of making a field-effect transistor device includes providing a substrate with a fin stack having: a first sacrificial material layer on the substrate, a first semiconductive material layer on the first sacrificial material layer, and a second sacrificial material layer on the first semiconductive material layer. The method includes inserting a dummy gate having a second thickness, a dummy void, and an outer end that is coplanar to the second face. The method includes inserting a first spacer having a first thickness and a first void, and having an outer end that is coplanar to the first face. The method includes etching the first sacrificial material layer in the second plane and the second sacrificial material layer in the fourth plane. The method includes removing, at least partially, the first spacer. The method also includes inserting a second spacer having the first thickness.

Abstract: In accordance with a method of forming a semiconductor device, an auxiliary structure is formed at a first surface of a silicon semiconductor body. A semiconductor layer is formed on the semiconductor body at the first surface. Semiconductor device elements are formed at the first surface. The semiconductor body is then removed from a second surface opposite to the first surface at least up to an edge of the auxiliary structure oriented to the second surface.

Abstract: Provided are semiconductor devices and fabricating methods thereof. The semiconductor device includes a field insulating layer formed in a substrate, an interlayer dielectric layer formed on the field insulating layer and including a trench exposing at least a portion of the field insulating layer, a deposition insulating layer formed in the trench to be disposed on the field insulating layer, a gate insulating layer formed the trench to be disposed on the deposition insulating layer, and a metal gate formed the trench on the gate insulating layer.

Abstract: A semiconductor device includes a gate structure on a substrate; a protection layer on the gate structure; a source/drain region adjacent to the gate structure; and an interconnect plug on the source/drain region. The gate structure includes a gate electrode including a top surface; and a sidewall spacer interfacing a sidewall of the gate electrode. The protection layer covers at least a first portion of the top surface and the sidewall spacer. The protection layer is interposed between the interconnect plug and the gate electrode.

Abstract: A method of forming a transistor having a gate electrode includes forming a sacrificial layer over a semiconductor substrate, forming a patterning layer over the sacrificial layer, patterning the patterning layer to form patterned structures, forming spacers adjacent to sidewalls of the patterned structures, removing the patterned structures, etching through the sacrificial layer using the spacers as an etching mask and etching into the semiconductor substrate, thereby forming trenches in the semiconductor substrate, and filling a conductive material in the trenches in the semiconductor substrate to form the gate electrode.

Abstract: A semiconductor device includes a source/drain region, a barrier layer, and an interlayer dielectric. The barrier layer surrounds the source/drain region. The interlayer dielectric surrounds the barrier layer. As such, the source/drain region can be protected by the barrier layer from oxidation during manufacturing of the semiconductor device, e.g., the formation of the interlayer dielectric.

Abstract: A thin film transistor, a manufacturing method thereof, and a display device are provided. The thin film transistor includes a gate electrode (21), an active layer (23), a source electrode (241) and a drain electrode (242). The source electrode (241) and the drain electrode (242) are formed of at least two materials, the forming materials of the source electrode (241) and the drain electrode (242) can create a cell reaction in a corresponding etching solution so as to be etched, and material of the active layer (23) is not corroded by the etching solution. With the thin film transistor and manufacturing method thereof according to embodiments of the invention, a problem that an active layer is liable to be corroded in an etching procedure of a source electrode and a drain electrode can be solved, and thus the thin film transistor device can be manufactured by using a back channel etch process.

Abstract: A method for preparing a TiAl alloy thin film, wherein a reaction chamber is provided, in which at least one substrate is placed; an aluminum precursor and a titanium precursor are introduced into the reaction chamber, wherein the aluminum precursor has a molecular structure of a structural formula (I); and the aluminum precursor and the titanium precursor are brought into contact with the substrate so that a titanium-aluminum alloy thin film is formed on the surface of the substrate by vapor deposition. The method solves the problem of poor step coverage ability and the problem of incomplete filling with regard to the small-size devices by the conventional methods. Meanwhile, the formation of titanium-aluminum alloy thin films with the aid of plasma is avoided so that the substrate is not damaged by plasma.