Patents Issued in April 24, 2018
  • Patent number: 9952766
    Abstract: A memory device capable of performing an overwrite operation, a memory system, and a method of operating the memory system are provided. The method includes receiving one or more write requests, a logical address and data corresponding to the one or more write requests; comparing a result of analyzing at least one of the received one or more write requests, logical address, and data with a threshold value; and writing data using a first update method or a second update method, based on a result of the comparison. When the first update method is selected, the data are written in a region indicated by a physical address corresponding to the logical address according to address mapping information. When the second update method is selected, information of the physical address corresponding to the logical address is changed, and the data are written in a region indicated by the changed physical address.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeong-Jae Woo, Kyoung-Il Bang, Sung-Yong Seo, Eun-Chu Oh, Moon-Sang Kwon, Han-Shin Shin
  • Patent number: 9952767
    Abstract: A consistency group is used as a basic unit of data management of storage containers served by a storage input/output (I/O) stack executing on one or more nodes of a cluster. The storage container may be a LUN embodied as parent volume (active volume), a snapshot (represented as an independent volume embodied as read-only copy of the active volume), and a clone (represented as another independent volume embodied as a read-write copy (clone) of the active volume). A consistency group (CG) is a set (i.e., collection) of objects, e.g., LUNs or other CGs (nested CG), which may be managed and operated upon collectively by an administrative command via a Storage Area Network administration layer (SAL) of the storage I/O stack.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 24, 2018
    Assignee: NetApp, Inc.
    Inventors: Ling Zheng, Ning Zhao, Radek Aster, Jeffrey S. Kimmel
  • Patent number: 9952768
    Abstract: In one aspect, a multiple mode data structure can be utilized by a storage management system to provide a host representation role in one mode, and represent both a host and a host port in another mode. In one embodiment, in a first mode, the data structure has an undefined host port name attribute and a defined host name attribute to represent a host identified by the defined host name attribute. In the first mode, the data structure is restricted from representing a host port in the storage management system when the host port name attribute is undefined. In a second, unrestricted mode, the multiple mode data structure can represent both a host as well as a host port when a host port name attribute is defined. In one embodiment, the multiple mode data structure can also represent a host cluster. Other aspects are described.
    Type: Grant
    Filed: October 19, 2015
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Joshua J. Crawford, Paul A. Jennas, II, Jason L. Peipelman, Matthew J. Ward
  • Patent number: 9952769
    Abstract: Operations of a variety of components of a storage system stack are redefined to make the system more efficient when the underlying media has a “multi-log” type interface such as the case with NAND flash SSD memory or shingled magnetic recording media. The responsibilities of components of the storage system stack are modified such that each responsibility is performed at the most efficient component (level of abstraction) of the storage stack.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: April 24, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC.
    Inventors: Anirudh Badam, Bikash Sharma, Laura Marie Caulfield, Badriddine Khessib, Suman Kumar Nath, Jian Huang
  • Patent number: 9952770
    Abstract: Embodiments of the present invention provide methods, systems, and computer program products for responding to recall operations based on a file migration time. In one embodiment, it is determined whether the number of recall requests (R) is equal to the number of storage drives in an idle state, and if the number of recall requests (R) is equal to the number of storage drives in an idle state, the storage drive(s) that are in the idle state are assigned as having the shortest time to complete a requested recall operation. The time to complete the requested recall operation (M) of the identified idle state storage drive(s) is set to zero.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Tohru Hasegawa, Masayuki Iwanaga, Yutaka Oishi
  • Patent number: 9952771
    Abstract: Example embodiments of the present invention relate to a method, a system, and a computer program product for compressing data in a data storage system. The method includes performing writes to the data storage system according to a first compression algorithm and determining to perform write commands according to a second compression algorithm. Subsequent writes may be performed to the data storage system according to the second compression algorithm.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: April 24, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Ron Bigman
  • Patent number: 9952772
    Abstract: The disclosed embodiments provide a system for detecting and managing inefficiency in local storage. During operation, the system obtains a first snapshot of data in local storage of a computer system, wherein the first snapshot comprises a first set of data elements in the local storage at a first time. Next, the system applies a compression technique to the first snapshot to obtain a first set of inefficiency metrics for the first set of data elements. The system then outputs the first set of inefficiency metrics with additional attributes of the data to improve management of inefficiency in the data.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 24, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John W. Nicol, Ritesh Maheshwari, Nicholas P. Baggott, Haricharan K. Ramachandra, Badrinath K. Sridharan
  • Patent number: 9952773
    Abstract: A method and system for determining a cause for low disk space with respect to a logical disk is provided. The method includes identifying software activities associated with a computing system linked to a file system comprised by a disk storage device. Representations for the software activities are identified with respect to the file system and associated objects are defined. The objects impact available free space on a logical disk of the disk storage device and each software activity is linked with an associated object. An amount of disk space of the logical disk occupied by each object is determined. An impact of each object is analyzed with respect to an amount of available free disk space and a specific cause(s) for the file system exceeding the available free space is determined.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventor: Christian S. Rashev
  • Patent number: 9952774
    Abstract: A method, hybrid server system, and computer program product, prefetch data. A set of prefetch requests associated with one or more given datasets residing on the server system are received from a set of accelerator systems. A set of data is prefetched from a memory system residing at the server system for at least one prefetch request in the set of prefetch requests. The set of data satisfies the at least one prefetch request. The set of data that has been prefetched is sent to at least one accelerator system, in the set of accelerator systems, associated with the at least one prefetch request.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Yuk Lung Chan, Rajaram B. Krishnamurthy, Carl Joseph Parris
  • Patent number: 9952775
    Abstract: A memory device for generating a mapping between one or more unusable columns and one or more backup columns within a memory. The memory includes a plurality of memory cells for storing data. The memory also includes a plurality of columns including a first subset of the plurality of memory cells. Each of the plurality of columns belongs to one of a plurality of data chunks. The memory further includes one or more backup columns including a second subset of the plurality of memory cells. The memory device also includes a controller communicatively coupled to the memory and configured to perform operations including identifying unusable columns, detecting a condition associated with each data chunk, and generating a mapping between the backup columns and the unusable columns based on the condition such that each of the backup columns is mapped to a different unusable column.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: April 24, 2018
    Assignee: SK Hynix Inc.
    Inventors: Yu Cai, Fan Zhang, Chenrong Xiong, June Lee, Jaesung Sim, HyungSeok Kim
  • Patent number: 9952776
    Abstract: Storage node blades in a data storage system utilize queue pairs associated with point-to-point links to perform RDMA transactions with memory components associated with other storage node blades. Higher quality of service queue pairs are used for system message transactions and lower quality of service queue pairs are used for remote direct memory access data. Postings to a relatively higher priority queue pair are reduced when a corresponding relatively lower priority queue pair between the same pair of storage nodes via the same switch is starved of bandwidth. Postings to the relatively higher priority queue pair are increased when bandwidth starvation is remediated.
    Type: Grant
    Filed: July 24, 2015
    Date of Patent: April 24, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Alesia Tringale, Sean Pollard, Julie Zhivich, Jerome Cartmell
  • Patent number: 9952777
    Abstract: A method of orchestrated shuffling of data in a non-uniform memory access device that includes a plurality of processing nodes that are connected by interconnects. The method includes running an application on a plurality of threads executing on the plurality of processing nodes. Data to be shuffled is identified from source threads running on source processing nodes among the processing nodes to target threads executing on target processing nodes among the processing nodes. The method further includes generating a plan for orchestrating the shuffling of the data among the all of the memory devices associated with the threads and for simultaneously transmitting data over different interconnects to a plurality of different target processing nodes from a plurality of different source processing nodes. The data is shuffled among all of the memory devices based on the plan.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: April 24, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yinan Li, Guy M. Lohman, Rene Mueller, Ippokratis Pandis, Vijayshankar Raman
  • Patent number: 9952778
    Abstract: A data processing technology is provided, and is applied to a partition management device. The partition management device stores a partition view, the partition view records a correspondence between an ID of a current partition and an address of a storage disk, and a total quantity of current partitions may be less than a total quantity of final partitions. By using the technology, data forwarding may be performed on key-value data by using a current partition, thereby reducing complexity of a partition view.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: April 24, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Xiong Luo
  • Patent number: 9952779
    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a link. The processor is configured to select at least first and second memory devices for writing, and to write at least first and second data units in sequence to the first memory device over the link, while avoiding writing to any of the other memory devices until transferal of the at least first and second data units over the link has been completed, to write at least one data unit to the second memory device after transferring the at least first and second data units to the first memory device, and, in response to verifying that the first memory device is ready to receive subsequent data, to write to the first memory device at least a third data unit.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: April 24, 2018
    Assignee: APPLE INC.
    Inventors: Yoni Labenski, Roman Gindin, Etai Zaltsman, Moti Altahan, Yoram Harel, Barak Baum
  • Patent number: 9952780
    Abstract: An input to read two or more data records stored to a tape medium on a tape drive is received. A starting point is determined. The starting point is a closest data record, of the two or more data records, to a current position of a tape head of the tape drive. A read order of the two or more data records is determined. The read order is determined using an algorithm and the determined starting point. The determined read order is sent to a host device. A first data record is determined. A first locate operation within the tape drive is performed. The first data record, of the two or more data records stored on the tape medium, based on the determined read order is read. The first data record, of the two or more data records stored on the tape medium, is sent to the host device.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kousei Kawamura, Koichi Masuda, Sosuke Matsui, Yutaka Oishi, Takahiro Tsuda
  • Patent number: 9952781
    Abstract: A storage controller identifies a storage location within a storage division that corresponds to a high error rate. In response, the storage controller may refresh data stored on the storage division by relocating data from the storage division and/or initializing (e.g., erasing) the storage division. In some embodiments, the storage division is selectively refreshed by relocating data from the storage location(s) having high error rates, while deferring a full relocation of other data from the storage division. The storage division may be selectively refreshed based on reliability characteristics of the storage division, such as the remaining data retention time calculated for the storage division.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: April 24, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Evan Orme, James G. Peterson
  • Patent number: 9952782
    Abstract: An architecture for accessing data between different virtual disk formats. A virtual machine may be migrated or cloned from a first server that uses a first virtual disk format to a second server using a second virtual disk format. In response to an I/O request from the virtual machine, a real-time mapper compares the virtual disk format used by the virtual machine with the virtual disk format of the virtual disk that the request is directed to. If the formats are different, a set of mapping metadata is used to map between data of the different virtual disk formats. Due to the mapping being performed in real time, the virtual machine is able to operate upon the virtual disk without the need to perform a potentially costly format conversion of the virtual disk or the underlying data.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: April 24, 2018
    Assignee: Nutanix, Inc.
    Inventors: Karthik Chandrasekaran, Binny Sher Gill
  • Patent number: 9952783
    Abstract: A data processing method and apparatus, and a shared storage device, where the method includes receiving, by a shared storage device, a copy-on-write request sent by another storage device, where the copy-on-write request includes data on which copy-on-write is to be performed and a logical unit identifier and snapshot time point of the data; storing the data; and searching, according to the logical unit identifier and snapshot time point of the data, a preset shared mapping table for a corresponding entry, and storing, in the corresponding entry, mapping entry information of the data, where the mapping entry information includes the logical unit identifier and snapshot time point of the data and a storage address that is of the data and in the shared storage device, which can improve efficiency of snapshot data processing.
    Type: Grant
    Filed: January 19, 2015
    Date of Patent: April 24, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Cheng Lu, Bin Yang, Ye Zou
  • Patent number: 9952784
    Abstract: Identical data is written to multiple nonvolatile memory chips connected to a memory bus by sending address information to a first nonvolatile memory chip and a second nonvolatile memory chip, selecting the first and second nonvolatile memory chips, while the first nonvolatile and second nonvolatile memory chips are both selected, sending user data over the memory bus to the first and second nonvolatile memory chips in parallel, and programming the user data in the first nonvolatile memory chip and the second nonvolatile memory chip in parallel.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: April 24, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Rohit Hassan Sathyanarayan, Vinay Sandeep
  • Patent number: 9952785
    Abstract: Embodiments of the present disclosure relate to a method, computer program product and a system for enabling non-volatile random access to data where in response to receiving data from a client, causing the data to be written into a memory of a primary virtual machine and a memory of a mirror virtual machine; and in response to the primary virtual machine losing the data, recovering the data based on data in the memory of the mirror virtual machine.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: April 24, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Kenny Honglin Qiao, Youbing Li, Colin Yong Zou
  • Patent number: 9952786
    Abstract: Write operations are scheduled for multiple nodes in a shared storage cluster that supports volume replication. Requests are received from nodes for allocation of space for write operations in a replication log. In response to a received request, the current capacity of the requesting node to manage a backlog can be determined. The amount of space in the replication log allocated to the node is then calibrated to the node's capacity, thereby preventing self-throttling. A separate priority can be assigned to each volume, and space in the replication log assigned to each volume based on its priority. Nodes can target synchronous and other latency sensitive operations to higher priority volumes. A single global queue can be maintained to schedule write operations for all nodes, thereby providing a fair scheduling. A separate local queue can be maintained for each node, thereby providing specific levels of preference to specific nodes.
    Type: Grant
    Filed: May 6, 2016
    Date of Patent: April 24, 2018
    Assignee: Veritas Technologies LLC
    Inventors: Suhas Dantkale, Satyendra Thakur, Kirubakaran Kaliannan, Prasad Vadlamannati
  • Patent number: 9952787
    Abstract: The disclosed embodiments provide a system for detecting and managing inefficiency in external services. During operation, the system obtains a snapshot of a data stream transmitted over an external service from a computer system at a first time. Next, the system applies a compression technique to the snapshot to obtain a set of inefficiency metrics for a set of data elements in the snapshot. The system then outputs the set of inefficiency metrics with additional attributes of the data stream to improve identification of inefficiency in the data stream.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: April 24, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: John W. Nicol, Ritesh Maheshwari, Nicholas P. Baggott, Haricharan K. Ramachandra, Badrinath K. Sridharan
  • Patent number: 9952788
    Abstract: One embodiment of the present invention discloses a shared non-volatile memory (“NVM”) system using a distributed flash translation layer (“FTL”) scheme capable of facilitating data storage between multiple hosts and NVM devices. A process of shared NVM system includes an NVM management module or memory controller able to receive a request from a host for reserving a write ownership. The write ownership allows a host to write information to a portion of storage space in an NVM device. Upon identifying availability of the write ownership associated with the NVM device in accordance with a set of predefined policy stored in the NVM management module, the request is granted to the host if the write ownership is available. The host is subsequently allowed to fetch the FTL snapshot from the NVM device for the write operation.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: April 24, 2018
    Assignee: CNEX Labs, INC.
    Inventor: Yiren Ronnie Huang
  • Patent number: 9952789
    Abstract: A memory system includes a nonvolatile memory module and a memory controller. The nonvolatile memory module includes a plurality of memory chips and a module controller disposed on a printed circuit board. The module controller controls operations of the plurality of memory chips. Each of the plurality of memory chips includes a plurality of nonvolatile memory cells and operates in an operation mode. The operation mode is either a memory mode or a storage mode. The memory controller performs a write operation and a read operation on the nonvolatile memory module, and performs a first error check and correction (ECC) operation on data communicated with the nonvolatile memory module. One of the module controller or the plurality of memory chips performs a second ECC operation on data stored in the plurality of memory chips based on the operation mode of the plurality of memory chips.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: April 24, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Kwang-Jin Lee
  • Patent number: 9952790
    Abstract: In one embodiment, a method includes receiving, at a first host, a security profile related to a first data socket descriptor indicating risk to data security of a second host. The method also includes, in response to the risk indicated by the security profile, performing by the first host, at least one action selected from a group of actions. The group of actions includes a cache flush on a cache of the first host according to a cache flush policy, cache locking on data stored in the cache of the first host, data redaction on data of a payload prior to being sent by the first host, memory locking of data stored in an in-memory database of the first host, and encryption of data stored in the in-memory database of the first host or encryption of selected data fields of a payload prior to being sent from the first host.
    Type: Grant
    Filed: June 13, 2016
    Date of Patent: April 24, 2018
    Assignee: AVOCADO SYSTEMS INC.
    Inventor: Keshav Govind Kamble
  • Patent number: 9952791
    Abstract: A memory card includes a first signal terminal configured to output a first signal; a second signal terminal configured to output a second signal, the first and second signals being complementary to each other; and a controller configured to drive the first and second signal terminals to have a negative state until a link connection is performed after power is supplied to the memory card. When a level of the first signal is greater than a level of the second signal, the first and second signal terminals are in a positive state, whereas when a level of the first signal is smaller than a level of the second signal, the first and second signal terminals are in the negative state.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: April 24, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Soonbok Jang, Sungho Seo, Sang-Hoon Lee
  • Patent number: 9952792
    Abstract: Methods, systems, and computer readable media for storage device workload detection using power consumption are disclosed. One aspect of the subject matter described herein includes a storage device. The storage device includes non-volatile storage. The storage device further includes a device controller for controlling access to the non-volatile storage. A power management controller separate from the device controller senses an indication of power used by at least one of the non-volatile storage and the device controller, compares the sensed indication of power to at least one threshold, and, in response to a predetermined relationship between the sensed indication of power and the at least one threshold, signals the device controller of a workload state of the storage device.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: April 24, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Gadi Vishne, Nir Amir, Judah Gamliel Hahn
  • Patent number: 9952793
    Abstract: A memory system may include: a memory device including a plurality of pages having a plurality of memory cells coupled to a plurality of word lines and suitable for storing read data and write data requested from a host, a plurality of memory blocks each including the pages, a plurality of planes each including the memory blocks, and a plurality of memory chips each including the planes; and a controller suitable for searching map data of the read data corresponding to a read command received from the host on a basis of a plurality of segments, triggering memory chips corresponding to the map data searched through the searches of the respective segments, reading data stored in the triggered memory chips, and transferring the read data to the host.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: April 24, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jeen Park
  • Patent number: 9952794
    Abstract: A storage device or storage system includes a transient compression layer that is established based on a level of finishedness of the capacity of the storage device or storage system. Data may be compressed and written to the transient compression layer until the capacity is sufficiently finished, after which the compressed data may be destaged and written to the capacity. The transient compression layer may be established on a hard disc media of the storage system or in a SSD of the storage system.
    Type: Grant
    Filed: June 27, 2016
    Date of Patent: April 24, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Andrew Michael Kowles
  • Patent number: 9952795
    Abstract: In a data storage system including a non-volatile random access memory (NVRAM) array, a page is a smallest granularity of the NVRAM array that can be accessed by read and write operations, and a memory block containing multiple pages is a smallest granularity of the NVRAM array that can be erased. Data are stored in the NVRAM array in page stripes distributed across multiple memory blocks. In response to detection of an error in a particular page of a particular block of the NVRAM array, only the particular page of the particular block is retired, such that at least two of the multiple memory blocks across which a particular one of the page stripes is distributed include differing numbers of active (non-retired) pages.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Charles J. Camp, Ioannis Koltsidas, Roman A. Pletka, Andrew D. Walls
  • Patent number: 9952796
    Abstract: Methods and systems for storing data in memory arrays are described. In one implementation, input bits are encoded into an intermediate binary array having multiple sub-arrays iteratively appended row-wise to the intermediate binary array. First sub-array is generated based on the input bits such that each row of the first sub-array has a number of 1's equal to a fraction of number of columns in the first sub-array, and based on a column balance coding such that the columns of the first sub-array have an equal number of 1's. At least one subsequent sub-array is generated based on a set of bits obtained from balancing termination indices for a previous sub-array and from diagonal bits of the intermediate binary array that are a part of the previous appended sub-array. The intermediate binary array is transformed to an encoded bit pattern. The encoded bit pattern is stored in the memory array.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 24, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Erik Ordentlich, Ron M. Roth
  • Patent number: 9952797
    Abstract: Presented herein are mass data storage networks, file system protocols, non-transitory machine readable devices, and methods for storing data blocks in mass data storage systems. Methods for storing data blocks in a file system are disclosed which include: receiving by storage controller of the data storage system a request to write a data file to a system storage module; determining whether the data file includes a sub-K data chunk that is less than approximately four kilobytes; identifying a packed block that stores a plurality of sub-K data chunks and has sufficient storage space available to store the sub-K data chunk; and placing, by the storage controller in the packed block, the sub-K data chunk and a corresponding data length and a respective offset identifying a location of the sub-K data chunk in the packed block.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: April 24, 2018
    Assignee: NETAPP, INC.
    Inventors: Manish Katiyar, Anathan Subramanian, Subramaniam Periyagaram
  • Patent number: 9952798
    Abstract: Methods, systems, and apparatus for allocating, by a source of one or more sources, a segment of a data file of a transient memory for exclusive access by the source, the transient memory being a distributed in-memory file system that supports remote direct memory access; writing, by the source, data from an initial partition to one or more blocks within the allocated segment of the data file, wherein a portion of the initial partition is written to a first block of the one or more blocks; publishing, by the source, the segment of the data file of the transient memory to be accessible for reading by one or more sinks; and reading by a particular sink of the one or more sinks, a particular block of the published segment of the data file of the transient memory, wherein the particular block is associated with the particular sink.
    Type: Grant
    Filed: August 12, 2016
    Date of Patent: April 24, 2018
    Assignee: Google Inc.
    Inventors: Hossein Ahmadi, Matthew B. Tolton, Michael Entin
  • Patent number: 9952799
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 24, 2018
    Assignee: Cavium, Inc.
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 9952800
    Abstract: Embodiments of the present invention relate to multiple parallel lookups using a pool of shared memories by proper configuration of interconnection networks. The number of shared memories reserved for each lookup is reconfigurable based on the memory capacity needed by that lookup. The shared memories are grouped into homogeneous tiles. Each lookup is allocated a set of tiles based on the memory capacity needed by that lookup. The tiles allocated for each lookup do not overlap with other lookups such that all lookups can be performed in parallel without collision. Each lookup is reconfigurable to be either hash-based or direct-access. The interconnection networks are programmed based on how the tiles are allocated for each lookup.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: April 24, 2018
    Assignee: Cavium, Inc.
    Inventors: Anh T. Tran, Gerald Schmidt, Tsahi Daniel, Saurabh Shrivastava
  • Patent number: 9952801
    Abstract: Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: April 24, 2018
    Assignee: Intel Corporation
    Inventors: Raj K. Ramanujan, Jun Zhu, Mohamed Arafa, Woojong Han, Jordan A. Horwich
  • Patent number: 9952802
    Abstract: A method of erasing volatile memory requiring refreshment using refresh circuitry to maintain data storage, the method comprising controlling the refresh circuitry for preventing refreshment of the memory upon occurrence of a predefined event which would require erasure of data stored in the memory by a previous user, process, application or service. A computer readable medium encoded with processor executable instructions for execution by a processing unit for controlling a refresh circuitry connected to a volatile memory for preventing refreshment of the memory at the predefined event. A refresh circuitry adapted to be connected to a volatile memory requiring refreshment using the refresh circuitry to maintain data storage, the refresh circuitry being adapted to prevent the refreshment of the memory at the occurrence of the predefined event. A volatile memory comprising a refresh circuitry adapted to prevent the refreshment of the memory at the occurrence of the predefined event.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: April 24, 2018
    Assignee: KHALIFA UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Khaled Hamed Salah, Baker Shehadah Mohammad, Mahmoud Abdullah Al-Qutayri, Bushra Abbas Mohammed Essa Albelooshi
  • Patent number: 9952803
    Abstract: Described are techniques for configuring data storage. Criteria identifying limits is received for a plurality of storage tiers for one or more logical devices. The storage tiers include a first storage tier and one or more other storage tiers where the first storage tier is higher performing than the other storage tiers. First processing is performed to determine a first set of data portions of the logical devices to be stored on physical devices of the first storage tier subject to limits included in said criteria. First processing includes determining scores for data portions of the logical devices. Each score is calculated using one or more metrics including a first metric weighted based on an expected I/O size. The data portions are ranked in accordance with the scores. The first set of data portions stored in the first storage tier is selected based on the score ranking.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: April 24, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Sean C. Dolan, Hui Wang, Owen Martin, Marik Marshak, Dan Aharoni, Alexandr Veprinsky, Xiaomei Liu
  • Patent number: 9952804
    Abstract: In an approach for resolving terminated transactions in a transactional memory environment, a processor initiates a hardware transaction in a computing environment, wherein the hardware transaction accesses a memory location, and wherein the hardware transaction includes a transaction begin indicator and a transaction end indicator. A processor detects a conflicting access of the memory location while executing the hardware transaction. A processor aborts the hardware transaction based on the conflicting access of the memory location. Hardware determines that the conflicting access of the memory location is a transient condition. A processor reinitiates the hardware transaction.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventors: Jonathan D. Bradbury, Michael Karl Gschwind, Maged M. Michael, Valentina Salapura, Eric M. Schwarz, Chung-Lung K. Shum, Timothy J. Slegel
  • Patent number: 9952805
    Abstract: A processor receives a command from a server computer to designate a plurality of addresses related to a plurality of logical storage areas, and write a plurality of write data to the logical storage areas. The processor receives the write data and writes it to storage areas different from storage areas in which a plurality of holding data are stored in a first memory. When the processor determines that the write data are written to the first memory, the processor transmits a success response to a host computer. When the write data satisfy a predetermined condition, the processor writes the write data in the first memory to a plurality of first device storage areas. When it is determined that at least a part of the data is not written to the first memory, the processor transmits a failure response to the host computer.
    Type: Grant
    Filed: September 11, 2014
    Date of Patent: April 24, 2018
    Assignee: HITACHI, LTD.
    Inventors: Takashi Nagao, Tomohiro Kawaguchi, Yoshinori Oohira
  • Patent number: 9952806
    Abstract: A mapping table loading method and a memory storage apparatus are provided. The method includes: receiving a plurality of first read commands comprising a plurality of first logical units; executing a first logical-physical mapping table pre-loading operation to read a plurality of mapping information corresponding to the first logical units in a logical-physical mapping table from a rewritable non-volatile memory module to a first buffer area of a buffer memory according to a first executing sequence of the first read commands if the first logical units are not continuous logical addresses; and reading data belonging to the first logical units from physical erasing units to the first buffer area according to the mapping information of the first logical units, and replacing the mapping information of the first logical units in the first buffer area by the data belonging to the first logical units.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: April 24, 2018
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Hao-Zhi Lee, Qi-Ao Zhu, Chong Peng, Hui Xie
  • Patent number: 9952807
    Abstract: A method, system, and computer program product for identifying the location of a Virtual Machine File System (VMFS) of a Virtual Machine (VM) on one or more LUNs on a storage medium, replicating the one or more LUNs storing the VMFS, and exposing the replicated one or more LUNs.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: April 24, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Sunil Kumar
  • Patent number: 9952808
    Abstract: Embodiments of the invention relate to intra-block organized storage placement. One embodiment includes obtaining a file in a file system. The file is separated into multiple blocks. The multiple blocks are separated into at least two correlated sub-blocks. Intra-file block organized storage placement on different memory devices is determined for the at least two correlated sub-blocks in a file system metadata layout.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: April 24, 2018
    Assignee: International Business Machines Corporation
    Inventor: Rini Kaushik
  • Patent number: 9952809
    Abstract: A data handling system having a physical storage device and a storage controller responsible for provisioning, managing, and servicing logical unit numbers (LUNs) with self-destruction properties on the physical storage device is disclosed. For a given LUN, the storage controller creates a profile including self-destruction properties, such as a LUN destruction date, and associates the profile with the LUN. The profiles may be independent of file format and content of any associated data and the LUN destruction date may be a function of the last access date of the associated data. The storage controller monitors the LUN destruction date associated with each LUN and determines the last access date of any associated data. The storage controller marks a LUN having a past-due LUN destruction date, notifies a user of an approaching LUN destruction date, and destroys any past-due LUNs.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: April 24, 2018
    Assignee: DELL PRODUCTS, L.P.
    Inventor: Parind Shah
  • Patent number: 9952810
    Abstract: An information processing system includes a plurality of information processing apparatuses and a storage apparatus that stores user identification information of a user in association with identification information of at least one of the information processing apparatuses that stores bibliographic information of output data associated with the user.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: April 24, 2018
    Assignee: Ricoh Company, Ltd.
    Inventor: Hironori Hakozaki
  • Patent number: 9952811
    Abstract: The invention provides an alternative applications programming interface (API) for a software application to interface with and to control the operation of a variety of one or more specialty devices, including specialty printing devices. The alternative API provides a superset of control functionality relative to an API that would typically be provided by a specialty device driver. In some embodiments, this alternative API is provided via a specialty device module (SDM) or a specialty printing module (SPM) that is remotely accessible to a software application via a computer network. The SDM or SPM can provide for interface and control of specialty devices that would otherwise be un-accessible to a software application via a specialty device driver, and can provide such locally or remotely accessible functionality to the software application, without necessarily requiring employment of a specialty device driver.
    Type: Grant
    Filed: June 15, 2015
    Date of Patent: April 24, 2018
    Inventor: Majid Amani
  • Patent number: 9952812
    Abstract: A method and system for controlling digital printing of a secret file is provided in this invention. The method comprises: obtaining a source file to be printed; importing the source file into a secret file library; generating a printing job for the source file and adding the printing job into a job list; writing printing control information of the source file into a standard file; after the printing is started, extracting page dot matrix data of the source file from the secret file library, and processing the page dot matrix data according to the printing control information; and transmitting the processed page dot matrix data to a numerical control device. Control management may be effectively realized throughout the printing process of the secret file, and the source file and the standard file cannot be copied without some professional skills in the printing process.
    Type: Grant
    Filed: December 6, 2013
    Date of Patent: April 24, 2018
    Assignees: Peking University Founder Group Co., LTD., Founder Information Industry Holdings Co., LTD., Beijing Founder Electronics Co., LTD.
    Inventor: Xingxin Sun
  • Patent number: 9952813
    Abstract: Provided is a non-transitory computer-readable storage medium storing a print control program which, when being executed by a processor of a print control apparatus, causes the print control apparatus to perform the following processing. The processing includes, obtaining specific information about a document file or an image processing apparatus; determining whether to conduct or skip an analysis of a file structure of the document file, on a basis of the specific information; and conducting or skipping the analysis in accordance with a result of the determining. The processing further includes, converting the document file into variable print data in response to receiving a result of the analysis; on conducting the analysis, outputting the variable print data to the image processing apparatus; and on skipping the analysis, outputting the document file to the image processing apparatus.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 24, 2018
    Assignee: KONICA MINOLTA, INC.
    Inventor: Kunihiko Sugimoto
  • Patent number: 9952814
    Abstract: An information processing apparatus includes a non-contact antenna that communicates with a communication counterpart via a non-contact communication and circuitry that generates a location guide image indicating a location of the non-contact antenna in the information processing apparatus and the location guide image including an ellipse placed at a portion of a display screen corresponding to the location of the non-contact antenna.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: April 24, 2018
    Assignee: Ricoh Company, Ltd.
    Inventors: Takuya Hirotani, Tomoe Kitaguchi
  • Patent number: 9952815
    Abstract: An image generation-output control apparatus provided in an image forming apparatus communicable with a server that controls a plurality of processes in an image processing system includes a first image processing unit, a second image processing unit, a job receiver to update an initial command information received from the server to a specific command information, a part of the initial command information updated to the specific command information processable at the second image processing unit and not processable at the first image processing unit, and a job controller to cause the first image processing unit to generate first image drawing information based on output target image information received from the server and the initial command information that is not updated, and further cause the second image processing unit to generate second image drawing information based on the specific command information and the output target image information received from the server.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: April 24, 2018
    Assignee: RICOH COMPANY, LTD.
    Inventor: Junpei Kuroiwa