Abstract: According to one embodiment, a method for controlling a nonvolatile memory includes allocating a first system block to a physical block included in one of the first and second parallel operation elements. The first system block is used by a first CPU controlling the nonvolatile memory but is not used by a second CPU controlling the nonvolatile memory. The method includes allocating a second system block to a physical block included in the other of the first and second parallel operation elements. The second system block is used by the second CPU but is not used by the first CPU.

Abstract: Techniques for distributed cache management are provided. A server having backend resource includes a global cache and a global cache agent. Individual clients each have client cache agents and client caches. When data items associated with the backend resources are added, modified, or deleted in the client caches, the client cache agents report the changes to the global cache agent. The global cache agent records the changes and notifies the other client cache agents to update a status of the changes within their client caches. When the changes are committed to the backend resource each of the statuses in each of the caches are updated accordingly.

Abstract: There are disclosed techniques for use in managing data storage in a data storage system which comprise a data storage device and a cache memory. In one example, a method comprises the following steps. An I/O request is received and a durability requirement of the I/O request data associated with the I/O request is determined. Based on the durability requirement of the I/O request data, the I/O request data is classified. The classified I/O request data is stored in the cache memory.

Abstract: A method for allocating cache for a disk array includes monitoring an I/O distribution of the disk array in a predetermined time period, determining a garbage collection state of the disk array, the garbage collection state allows the disk array to perform a garbage collection and prevents the disk array to perform the garbage collection, and determining an allocation of the cache based on the I/O distribution and the garbage collection state.

Abstract: Systems and methods that aggregate memory capacity of multiple computers into a single unified cache, via a layering arrangement. Such layering arrangement is scalable to a plurality of machines and includes a data manager component, an object manager component and a distributed object manager component, which can be implemented in a modular fashion. Moreover, the layering arrangement can provide for an explicit cache tier (e.g., cache-aside architecture) that applications are aware about, wherein decision are made explicitly which objects to put/remove in such applications (as opposed to an implicit cache wherein application do not know the existence of the cache).

Abstract: Loading data from a computer memory system is disclosed. A memory system is provided, wherein some or all data stored in the memory system is organized as one or more pointer-linked data structures. One or more iterator registers are provided. A first pointer chain is loaded, having two or more pointers leading to a first element of a selected pointer-linked data structure to a selected iterator register. A second pointer chain is loaded, having two or more pointers leading to a second element of the selected pointer-linked data structure to the selected iterator register. The loading of the second pointer chain reuses portions of the first pointer chain that are common with the second pointer chain. Modifying data stored in a computer memory system is disclosed. A memory system is provided. One or more iterator registers are provided, wherein the iterator registers each include two or more pointer fields for storing two or more pointers that form a pointer chain leading to a data element.

Abstract: A method and apparatus for reducing write-backs to memory is disclosed herein. The method includes determining whether a read/write request entering a lower level cache is a cache line containing modified data, and responsive to determining that the read/write request is not a cache line containing modified data, manipulating age information of the cache line to reduce a number of write-backs to memory.

Abstract: A dual-server based storage system maintains a first cache and a first non-volatile storage (NVS) in a first server, and a second cache and a second NVS in a second server, where data in the first cache is also written in the second NVS and data in the second cache is also written in the first NVS. In response to a failure of the first server, a determination is made as to whether space exists in the second NVS to accommodate the data stored in the second cache. In response to determining that space exists in the second NVS to accommodate the data stored in the second cache, the data is transferred from the second cache to the second NVS.

Abstract: According to an example, memory traffic including memory access commands is routed between compute nodes and memory nodes in a memory network. Other traffic is also routed in the memory network. The other traffic may include input/output traffic between the compute nodes and peripherals connected to the memory network.

Abstract: A computer allows non-cacheable loads or stores in a hardware transactional memory environment. Transactional loads or stores, by a processor, are monitored in a cache for TX conflicts. The processor accepts a request to execute a transactional execution (TX) transaction. Based on processor execution of a cacheable load or store instruction for loading or storing first memory data of the transaction, the computer can perform a cache miss operation on the cache. Based on processor execution of a non-cacheable load instruction for loading second memory data of the transaction, the computer can not-perform the cache miss operation on the cache based on a cache line associated with the second memory data being not-cached, and load an address of the second memory data into a non-cache-monitor. The TX transaction can be aborted based on the non-cache monitor detecting a memory conflict from another processor.

Abstract: A method for managing a parallel cache hierarchy in a processing unit. The method including receiving an instruction that includes a cache operations modifier that identifies a level of the parallel cache hierarchy in which to cache data associated with the instruction; and implementing a cache replacement policy based on the cache operations modifier.

Abstract: Systems, methods and or devices are used to enable improving mixed random performance in low queue depth workloads in a storage device (e.g., comprising a plurality of non-volatile memory units, such as one or more flash memory devices). In one aspect, the method includes (1) maintaining a write cache corresponding to write commands from a host, (2) determining a workload in accordance with commands from the host, (3) in accordance with a determination that the workload is a non-qualifying workload, scheduling a regular flush of the write cache, and (4) in accordance with a determination that the workload is a qualifying workload, scheduling an optimized flush of the write cache.

Abstract: Systems and methods for a direct memory access (DMA) operation are provided. The method includes receiving a host memory address by a device coupled to a computing device; storing the host memory address at a device memory by a DMA engine; receiving a packet at the device for the computing device; instructing the DMA engine by a device processor to retrieve the host memory address from the device memory; retrieving the host memory address by the DMA engine without the device processor reading the host memory address; and transferring the packet to the computing device by a DMA operation.

Abstract: Systems and methods for deferring registration for Direct Memory Access (DMA) operations. An example method may comprise: receiving a memory region registration request identifying a memory region for a direct memory access (DMA) operation; generating a local key for the memory region; receiving a DMA work request referencing the local key; and responsive to determining that an amount of pinned memory is below a threshold, registering the memory region for DMA transfer.

Abstract: A method includes reading memory pages from a non-volatile memory that holds at least first memory pages having a first bit significance and second memory pages having a second bit significance, different from the first bit significance. At least some of the read memory pages are cached in a cache memory. One or more of the cached memory pages are selected for eviction from the cache memory, in accordance with a selection criterion that gives eviction preference to the memory pages of the second bit significance over the memory pages of the first bit significance. The selected memory pages are evicted from the cache memory.

Abstract: Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote ready lists indicate tracks eligible to demote from the cache. In response to determining that a number of free cache segments in the cache is below a free cache segment threshold, a determination is made of a number of demote threads to invoke on processors based on the number of free cache segments and the free cache segment threshold. The determined number of demote threads are invoked to demote tracks in the cache indicated in the demote ready lists, wherein each invoked demote thread processes one of the demote ready lists to select tracks to demote from the cache to free cache segments in the cache.

Abstract: Systems comprising a processor, a memory controller, and a flash memory. The flash memory comprises a programmable intelligent search memory (PRISM).

Abstract: A mechanism for managing storage block of a data volume is disclosed. A method includes determining, by a processing device, whether a current data is to be written into an entirety of a storage block of a data volume of an operating system. The method also includes deleting, by the processing device, all of previously written data on the storage block before writing the current data into the storage block in response to determining that the current data is not to be written into the entirety of the storage block. The current data is different from the previously written data.

Abstract: A method and a system in which a second device provides a service along with an external device via a first device is provided. The method includes, when a service connection to at least one external device has failed, searching for the first device that will relay service data for the external device, transmitting a relay request signal to the first device, and transmitting the service data for the external device to the first device, wherein the transmitted service data is converted by the first device, and wherein the converted service data is provided to the external device.

Abstract: Techniques for transmitted data through a USB port using a PCIe protocol are described herein. In one example, an apparatus includes a host controller, a root port, a multiplexor coupled to the host controller and the root port and a power delivery module. The power delivery module and the multiplexor can transmit and receive a request via a multimode input/output (I/O) interface and the power delivery module can detect a presence of an external device in response to the external device being coupled to the multimode I/O interface. The power delivery module can also send a first request to the external device to discover a vendor identifier of the external device, send a second request to discover at least one alternate mode supported by the external device, and send a third request to enable data transfer via the protocol.

Abstract: An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

Abstract: In a virtualized computer system in which a guest operating system runs on a virtual machine of a virtualized computer system, a computer-implemented method of providing the guest operating system with direct access to a hardware device coupled to the virtualized computer system via a communication interface, the method including: (a) obtaining first configuration register information corresponding to the hardware device, the hardware device connected to the virtualized computer system via the communication interface; (b) creating a passthrough device by copying at least part of the first configuration register information to generate second configuration register information corresponding to the passthrough device; and (c) enabling the guest operating system to directly access the hardware device corresponding to the passthrough device by providing access to the second configuration register information of the passthrough device.

Abstract: Embodiments of input/output hub unit are disclosed for aggregating interrupts received from multiple endpoint devices. The input/output hub may include an interface unit and one or more communication units. Each communication unit may be configured to receive messages from a corresponding endpoint device. The interface unit may be configured to update a first pointer within a first data structure responsive to a request from a given one of the communication units. The interface unit may be further configured to stored data in a second data structure responsive to updating the first pointer, reading a second pointer and the first pointer, and sending an interrupt responsive to a determination that the first and second pointers are equal.

Abstract: A method is provided for handling interrupts in a processor, the interrupts including regular interrupts having a range of priorities and a pseudo non-maskable interrupt (PNMI) that is of a higher priority than any of the regular interrupts. The method includes obtaining an interrupt vector corresponding to a received interrupt, and if the received interrupt is a PNMI, executing a PNMI interrupt handler. If the received interrupt is a regular interrupt, the method further comprises reading a mask flag that indicates whether regular interrupts are enabled in an interrupt controller and further: if the mask flag indicates that regular interrupts are enabled, enabling interrupts in the processor so that a PNMI can be received while handling the regular interrupt, executing, a regular interrupt handler, and disabling interrupts in the processor; and if the mask flag indicates that regular interrupts are disabled, saving the interrupt vector for subsequent handling.

Abstract: In an embodiment of the invention, a method comprises: fetching a first set of descriptors from a memory device and writing the first set of descriptors to a buffer; retrieving the first set of descriptors from the buffer and processing the first set of descriptors to permit a Direct Memory Access (DMA) operation; and if space is available in the buffer, fetching a second set of descriptors from the memory device and writing the second set of descriptors to the buffer during or after the processing of the first set of descriptors.

Abstract: In certain information handling system environments, physical devices connected to a client are redirected to a server or other information handling system. Each of these physical devices will use and occupy network bandwidth. Physical devices may be virtualized so that other users of remote systems may access and use the physical devices. Transaction requests associated with physical devices located at one or more client devices from applications may be reduced by determining if the transaction requests are certain types of commands, and if so then under certain conditions handling the transaction request at the server as opposed to transmitting all such transaction requests to the client device. Optimization of transaction requests associated with redirected devices provides efficiencies for a network.

Abstract: The present disclosure pertains to a wired network which includes a master device and a plurality of slave devices coupled to the master device by a wired connection. The master device includes control logic to determine whether information is to be sent to a slave device. In addition, the master device includes a transmitter to drive a logic level for a predetermined amount of time to address the slave device in response to the control logic to determine whether information is to be sent to a slave device.

Abstract: An integrated multimedia system and a control method are provided, in which, when a USB port is reset during a misrecognition and malfunction of a USB connected to a port of an integrated multimedia terminal integrally provided with an SD slot, an SD slot is prevented from being reset to improve the stability and quality of an AVN system. The system includes an integrated multimedia terminal including a USB port for electrical connection of a USB and an SD slot for electrical connection of an SD card. An audio video navigation (AVN) controller detects the SD card and the USB, obtains data of the SD card and the USB and is connected to the integrated multimedia terminal. A hub electrically connects the SD slot and the USB port to the AVN controller and an auxiliary controller operates the USB port in response to a control signal transmitted via the hub.

Abstract: A master device has a slave port and a redundant slave port for communicating with slaves according to a network protocol, e.g. EtherCAT, via data packets including a circulating bit. The slaves are arranged in a sequence starting at the slave port, and are connected via a communication medium. A respective slave in the sequence detects whether the connection to its processing receiver is lost, and, if so, internally transfers any data packets from its forwarding arrangement to its processing arrangement, while setting the circulating bit. The master device has a switcher unit coupled to the redundant slave port and a last slave in the sequence. The switcher unit transfers data packets from the switcher receiver to the switcher transmitter, and detects whether a circulating bit is set. If so, the unit switches off said transferring and switches on a connection between the redundant slave port and the switcher for transferring replicated packets to the sequence.

Abstract: In some embodiments, the present disclosure provides techniques for concurrently exchanging USB 2.0 information, SuperSpeed information, and four lanes of DisplayPort information via a single USB Type-C connection. In some embodiments, this may be accomplished in part by multiplexing signals such as the USB 2.0 signals and the DisplayPort AUX signal to fewer than a standard number of conductors in order to free up other conductors for the third and fourth lanes of DisplayPort information. In some embodiments, a standard USB Type-C receptacle, plug, and cable are used. In some embodiments, a modified receptacle, plug, and/or cable are provided.

Abstract: A method for improving a data transmission speed and an electronic device implementing the same are provided. The electronic device includes a USB connection unit configured to be connectable to an external electronic device and including designated data reception channels and data transmission channels, a switch unit configured to switch an electrical connection between the data reception channels and data transmission channels, and a control unit configured to confirm device attribute information of the external electronic device that is connected through the USB connection unit and to control the switch unit to switch the electrical connection so that at least one data reception channel functions as a data transmission channel if the connected external electronic device is a display device.

Abstract: A Thunderbolt sharing console includes a high speed switch electrically coupled to at least one Thunderbolt host, a MCU coupled to the high speed switch, and a Thunderbolt interface chip coupled to the high speed switch, wherein the MCU can be used to control the high speed switch for determining which one of the at least one Thunderbolt host is coupled to the Thunderbolt interface chip.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to manage cache memory in multi-cache environments. A disclosed apparatus includes a remote cache manager to identify a remote cache memory communicatively connected to a bus, a delegation manager to constrain the remote cache memory to share data with a host cache memory via the bus, and a lock manager to synchronize the host cache memory and the remote cache memory with a common lock state.

Abstract: A device comprising: a bus master, including a bi-directional data and clock lines, configured to produce a select signal output for enabling data transmission on the bi-directional data line to first/second different data busses supporting multiple slave devices configured to receive/transmit data over a respective data bus and to receive a clock signal from the bus master from the clock line; and a de-multiplexer including an input, first and second outputs and a control input, the input coupled to the bi-directional data line of the bus master, first/second outputs of the de-multiplexer coupled to first/second data busses, respectively, and the control input configured to receive the select signal from the bus master that is configured to communicate to a first slave device when the select signal is in a first state, and a second different slave device when the select signal is in a second different state.

Abstract: Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.

Abstract: An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a replica radial distribution element, a bit lag control element, and a synchronous lag receiver. The replica radial distribution element is configured to receive a lag pulse signal, and is configured to generate a replicated strobe signal, where the replica radial distribution network comprises replicated propagation path lengths, loads, and buffering of a radial distribution network for a strobe. The bit lag control element is configured to measure the time between assertion of the lag pulse signal and assertion of the replicated strobe signal when an update signal is asserted, and is configured to generate a first value on a lag bus that indicates the time.

Abstract: A data processing system is disclosed that includes machines having an in-line accelerator and a general purpose instruction-based general purpose instruction-based processor. In one example, a machine comprises storage to store data and an Input/output (I/O) processing unit coupled to the storage. The I/O processing unit includes an in-line accelerator that is configured for in-line stream processing of distributed multi stage dataflow based computations. For a first stage of operations, the in-line accelerator is configured to read data from the storage, to perform computations on the data, and to shuffle a result of the computations to generate a first set of shuffled data. The in-line accelerator performs the first stage of operations with buffer less computations.

Abstract: A data processing system with a main board and balcony boards. The data processing system includes a mainboard, at least one processor module, and at least one memory module. The system has at least one balcony board carrying at least one of the processor modules and at least one of the memory modules. The processor module has a first pin area for connecting to the balcony board and a second pin area for connecting to the mainboard, such that the balcony board is attached to the mainboard in a fixed position. The balcony board has an opening through which the processor module is plugged in a socket attached to the mainboard. The mainboard has an opening through which the processor module is plugged in a socket attached to the balcony board. A mainboard and a balcony board for a data processing system is also provided.

Abstract: Methods and structure for devices that implement multiple versions of the Serial Attached Small Computer System Interface (SAS) protocol. One exemplary embodiment comprises a SAS device that includes at least one physical link (PHY) that supports a specified generation of SAS protocols, and at least one PHY that supports a different generation of SAS protocols and that does not support the specified generation of SAS protocols. The SAs device also includes an Input/Output (I/O) processor able to select a PHY to service a SAS connection, based on the generation of SAS protocols supported by the PHY.

Abstract: Methods, systems, and computer storage mediums including a computer program product for managing data in a computing network are provided. One method includes registering a plurality of buffers with a work queue in a server and assigning ownership to each of the plurality of buffers to a different working thread in a plurality of working threads. The method further includes continuously polling, by a polling thread, the work queue to determine when work requests are received by the work queue, upon receipt of each work request, determining which buffer among the plurality of buffers each work request is associated, and performing each work request on each respective associated buffer by a working thread among the plurality of working threads that owns each respective associated buffer. One system includes a processor for performing the above method and one computer storage medium includes computer code for performing the above method.

Abstract: Methods, systems and program products for generating content from a user-created template. Embodiments of the invention may provide an interface configured to allow users to create templates, where the templates further include a user-specified formatting. Embodiments may receive a template created by a user using the provided interface, and responsive to receiving the template, may retrieve data associated with the variable fields in the received template. Embodiments may generate new content based on the received template and the retrieved data, where the generated new content is formatted according to the user-specified formatting in the received template.

Abstract: Determining relationships between graphical elements in a fixed format document is provided. Graphical element sizes and their relative positions may be analyzed to determine whether two or more graphical elements should be aggregated together or whether the graphical elements should belong to different graphical groups. Graphs and figures comprising objects that are absolutely positioned may be detected, as well as objects where inter-element positions need to be preserved from regular document flow. Additionally, background objects may be differentiated from regular text flow when the objects overlap with text.

Abstract: System and methods for displaying one or more assets on a client device based on device characteristics are provided. Code is transmitted to a client device. The code, when executed by the client device, causes a processor of the client device to determine a first device characteristic of the client device. A first layout may be selected based on the first device characteristic. The layout may include one or more cards. Each card may correspond to one or more assets. Each card may be modified based on a corresponding card characteristic. One or more assets may be requested. The assets may be displayed on the first client device. The code may be transmitted to another client device, which may select a different layout based on a different device characteristic.

Abstract: Page layout of content items from a variety of sources is performed. A content processing system queues content items, such as user-generated blogs, tweets, social networking status updates and other postings, received from a variety of sources. Each content item comprises one or more assets from one or more asset types. The asset types include text, images, and video. A page builder retrieves items from the queue and determines the item's size constraints. A template is selected from a template database to use as a layout for the items on a page; each template has a number of slots into which content can be placed. A layout module lays out the items into the slots of the selected template based on the respective size and aspect ratio constraints of the items, in order to build a page to serve to a client device.

Abstract: Systems and associated processes for generating user pagination preference data and using that data to generate and/or present network pages are described herein. These systems and processes can dynamically collect data representing a user's preference respecting specific layout determination factors, and can store this data in association with the user. The systems and processes can also make use of that data to provide the user with a personalized user interface which will provide the user with a page layout tailored to that specific user's browsing habits. Moreover, data representing the attributes of the requested content or the user device may further contribute to generating a page layout which optimally displays the requested content to the user. Accordingly, user pagination preference data can potentially both present a more satisfying user interface and elicit more item purchases than existing pagination systems in some embodiments.

Abstract: A method for marking web content. The method includes rendering first content on a web browser of a client device, and capturing a snapshot of the first content as rendered according to settings of the web browser. The method also includes receiving markup in association with the snapshot, and generating marked up content comprising the snapshot and the markup. The method also includes storing the marked up content for later access.

Abstract: Systems, devices and methods operative for identifying a reference within a figure and an identifier in a text associated with the figure, the reference referring to an element depicted in the figure, the reference corresponding to the identifier, the identifier identifying the element in the text, placing the identifier on the figure at a distance from the reference, the identifier visually associated with the reference upon the placing, the placing of the identifier on the figure is irrespective of the distance between the identifier and the reference.

Abstract: Providing interaction to an application with a collection of information stored in a Document Object Model is disclosed. The collection is maintained in the Document Object Model. A virtualization layer provides one or more collection interfaces to the collection. An indication of an interaction of the application with the collection is received. The collection interfaces include a safety buffer and the interaction of the application with the safety buffer triggers a functionality of the virtualization layer.

Abstract: A document file is displayed on a display device. A first display unit, which is a unit in which the document file is displayed, is divided into a plurality of areas. From the plurality of areas obtained by dividing the first display unit, a first target area viewed by a viewer is identified. In response to the first target area being displayed on the display device shifting from the first display unit to a second display unit, a decision is made whether to use setting information from the display area when the first target area identified by the identification means is displayed, based on a structure of the first display unit and a structure of the second display unit.

Abstract: A method, computer program product, and system for composition and declaration of tiled images in a style sheet. Embodiments commence upon identifying a collection of one or more computer-readable instances of individual style sheets, and identifying a corresponding collection of computer-readable objects comprising input images, wherein an individual style sheet includes references to the input images. The collection of one or more computer-readable instances of individual style sheets are used to determine a set of referenced images, which set of images are assembled into a tiled image. References to the images found in the set of images are modified or replaced such that the statements in the style sheets reference the tiled image rather than individual input images. One or more modified style sheets are output to be used in lieu of the unmodified style sheets.