Abstract: A data storage device may employ a suspension that positions a transducing head proximal a data storage medium. The suspension can consist of an active fiber composite that spans a portion of a loadbeam. The active fiber composite can be configured with at least one active fiber contacting a supporting layer.

Abstract: A slider for use in a disk drive, the slider including a slider body having a leading surface and an opposite trailing surface, wherein the trailing surface includes portions with extensions or depressions. The extensions or depressions include a slider bond pad.

Abstract: A heat-assisted magnetic recording (HAMR) write apparatus includes a laser for providing energy and resides in proximity to a media during use. The HAMR write apparatus includes a write pole that writes to a region of the media, coil(s) for energizing the write pole and a waveguide optically coupled with the laser. The waveguide includes at least one multi-mode interference (MMI) device. The MMI device has at least one input, a plurality of outputs, a propagation section and a multi-mode interference (MMI) section. Energy from the laser propagates through the propagation section before the MMI section. The propagation section expands the energy from the laser to a plurality of modes. A first portion of the outputs is output from the propagation section. The MMI section is between the propagation section and a second portion of the plurality of outputs.

Abstract: Techniques for verifying a magnetic tape are disclosed. The techniques include obtaining a position signal generated by reading a magnetic tape using a stationary tape head. Next, a simulated current for adjusting a position of the tape head to follow a track on the magnetic tape is updated using the position signal. The simulated current is then compared to one or more saturation limits to generate a verification result for a servo pattern on the magnetic tape, wherein the verification result classifies the magnetic tape as usable or unusable. Finally, the verification result is outputted for use in managing subsequent use of the magnetic tape.

Abstract: A repeatable runout (RRO) is accurately compensated for while moving a magnetic head radially across a disk surface. An iterative learning control algorithm is employed to determine appropriate feed-forward coefficients for an RRO compensation signal for each of a plurality of radial locations across the disk surface. The feed-forward coefficients are determined by performing multiple iterations of continuously moving the magnetic head across the disk surface along a target path while measuring a position error signal that indicates the radial error between the magnetic head and the target path. With each iteration, the iterative learning control algorithm computes new feed-forward coefficients for each of the plurality of radial locations, where the new feed-forward coefficients are selected to reduce the measured position error signal when employed to move the magnetic head along the target path.

Abstract: A storage device disclosed herein includes a transducer head with a proximity sensor that generates head-disc proximity signals, a digitizer configured to convert the analog proximity signals from the proximity sensor to digitized sample data, a discrete wavelet transformation (DWT) module configured to analyze the digitized sample data by performing an enhanced DWT on the digitized sample data to generate DWT coefficients, and a modal filter configured to determine dominant head-disc interference (HDI) modes for a transducer head by analyzing the DWT coefficients.

Abstract: A data storage device is disclosed comprising a disk, a head for accessing the disk, and a sensor for generating an alternating sensor signal. The sensor is disconnected from an input of a sensing circuit and while the sensor is disconnected an alternating calibration signal is injected into the input of the sensing circuit, wherein the alternating calibration signal comprises a predetermined offset and amplitude. A response of the sensing circuit to the alternating calibration signal is evaluated to detect at least one of an offset and a gain of the sensing circuit.

Abstract: A system, according to one embodiment, includes: a main pole; and a trailing shield. A first distance D1 is defined in a track direction between the trailing shield and a pole tip region of the main pole; and a second distance D2 is defined in the track direction between the trailing shield and a second region of the main pole located behind the pole tip region, where D2 is greater than D1. Other systems, and methods are described in additional embodiments.

Abstract: In one embodiment, an apparatus includes an accessor configured to transport data storage cartridges in a library environment, and a bracket configured to receive a wireless image capture device therein where the bracket is positioned to orient the wireless image capture device to capture images while the accessor is transporting data storage cartridges. In another embodiment, a method for mounting a wireless capture device to an accessor to capture images of an operation in a data storage library includes mounting a bracket to the accessor, where the accessor is configured to transport data storage cartridges in a library environment, where the bracket is configured to receive a wireless image capture device therein. The bracket is mounted in a position to orient the wireless image capture device to capture images while the accessor is transporting data storage cartridges.

Abstract: The present disclosure relates to a storage and transfer apparatus for mass transfer of a plurality of data discs to trays of a plurality stacked disc drives. The storage and transfer apparatus may store a plurality of discs with the disc hold pins retracted and the telescopic sections collapsed over each other. In such a configuration, the stored discs may lie in contact with each other. The storage and transfer apparatus may transfer the plurality of discs to the trays of the plurality of stacked disc drives with the discs holding pins extended and the telescopic sections extended relative to each other.

Abstract: Various embodiments provide a Gray code detector that is not designed to look for a specific defect signature, but rather looks for wedges that are in error or close to being in error, as determined through a probabilistic analysis that considers the mean and sigma of a minimum Viterbi Metric Margin (minVMM) distribution of a servo wedge relative to a defined threshold for a Wedge Error Rate (WER).

Abstract: Images may be extracted from a video. The images may be grouped into image groups. Numbers and types of classified visuals within the images may be detected. Individual types of classified visuals may correspond to individual classification weights. Image classification weights for the images may be determined based on the numbers and the types of classified visuals and the individual classification weights. Interest weights for the images may be determined based on the image classification weights and the sizes of the image groups to which the individual images belong. An interest curve may be generated based on the interest weights. A retime curve may be generated based on the interest curve. Time lapse images to be included in the time lapse video may be determined based on the images and the retime curve. The time lapse video may be generated based on the time lapse images.

Abstract: The present invention relates to a mobile terminal capable of capturing videos, and a method of controlling the same. The mobile terminal includes a display unit capable of outputting a first video captured in response to a preset user input, and outputting a timeline of the first video in a camera preview mode, a camera capable of capturing a second video consecutive to the first video, in response to a preset user input, and a controller capable of storing the first video and the second video as one full video, and outputting a timeline of the full video, which a timeline of the second video follows the timeline of the first video, in the camera preview mode.

Abstract: Systems and procedures for transforming video into a condensed visual representation. An example procedure may include receiving video comprised of a plurality of frames. For each frame, the example procedure may create a first representation, reduced in one dimension, wherein a visual property of each pixel of the first representation is assigned by aggregating a visual property of the pixels of the frame having the same position in the unreduced dimension. The example procedure may further form a condensed visual representation including the first representations aligned along the reduced dimension according to an order of the frames in the video.

Abstract: A system for providing sensory effects according to an embodiment of the present invention comprises an apparatus for providing vestibular rehabilitation videos configured to correct playback time of sensory effect metadata included in a plurality of integrated files based on start time of transport stream, and generate transport stream including the sensory effect metadata; and a gateway configured to receive the transport stream from the apparatus for providing vestibular rehabilitation videos, extract audio data, video data and the sensory effect metadata from the transport stream, transmit the audio data and the video data to a video player, and transmit the sensory effect metadata to an apparatus for providing sensory effects based on the corrected playback time.

Abstract: A method for manufacturing gaskets is described herein that includes cutting at least one hole in a first material, wherein the at least one hole corresponds to a first geometric shape. The method can also include wrapping the first material in a conductive material to produce a conductive material wrapped gasket. Additionally, the method can include producing a die-cut gasket by cutting a pattern from the conductive material wrapped gasket, the pattern to be cut from portions of the conductive material wrapped gasket corresponding to the at least one hole, wherein the pattern is to be based on a second geometric shape.

Abstract: A method of assembling a data storage device comprises forming an enclosure by overlapping each of a plurality of sidewalls of a cover with a corresponding sidewall of a base part, dispensing a liquid adhesive between the respective sidewalls of the cover and base part in such a quantity at each of a plurality of locations to promote capillary flow of the liquid adhesive to form a continuous film of liquid adhesive between the sidewalls, and curing the continuous film of liquid adhesive to form a hermetic seal between the cover and the base part. Embodiments may include surface treating the sidewall surface(s), which can help promote the capillary flow of the liquid adhesive. The hermetic seal provides for a lighter-than-air gas to be held therein.

Abstract: A semiconductor device and a method for fabricating the same are provided. The semiconductor device includes a substrate, a memory device, and a select transistor. The memory device is located on the substrate. The select transistor is located on the substrate and electrically connected to the memory device. The select transistor includes a select gate, a first dielectric layer, and a second dielectric layer. The select gate is located on the substrate. The first dielectric layer is adjacent to the second dielectric layer, and located between the select gate and the substrate. The first dielectric layer is closer to the memory device than the second dielectric layer. The thickness of the first dielectric layer is greater than the thickness of the second dielectric layer.

Abstract: A memory system of a high-speed operation can be realized by reducing an influence of reflection signals etc. caused by branching and impedance mismatching in various wirings between a memory controller and a memory module, and an influence due to transmission delays of data, command/address, and clocks in the memory module. To this end, a memory system comprises a memory controller and a memory module mounted with DRAMs. A buffer is mounted on the memory module. The buffer and the memory controller are connected to each other via data wiring, command/address wiring, and clock wiring. The DRAMs and the buffer on the memory module are connected to each other via internal data wiring, internal command/address wiring, and internal cock wiring. The data wiring, the command/address wiring, and the clock wiring may be connected to buffers of other memory modules in cascade.

Abstract: An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.

Abstract: A precharge control device includes a pulse generator, a bank address controller, and a precharge signal generator. The pulse generator generates a write precharge signal in response to a write burst end signal activated after a write burst operation and a read precharge signal in response to a read burst end signal activated after a read burst operation. The bank address controller generates a write address and a read address designating an address for the precharge operation in response to a write bank address and a read bank address. The precharge signal generator generates a precharge signal for performing the precharge operation in a bank selected in response to the write address when the write precharge signal is activated, or generates a precharge signal for performing the precharge operation in a bank selected in response to the read address when the read precharge signal is activated.

Abstract: A memory device may include the following elements: a first memory cell; a first word line for transmitting a first control signal to control an electrical connection in the first memory cell; a first bit line connected to the first memory cell; a first transistor, wherein a first terminal of the first transistor is connected to the first bit line; a second memory cell; a second word line for transmitting a second control signal to control an electrical connection in the second memory cell; a second bit line connected to the second memory cell; a second transistor, wherein a first terminal of the second transistor is connected to the second bit line; and a sense amplifier having a first input terminal connected to a second terminal of the first transistor and having a second input terminal connected to a second terminal of the second transistor.

Abstract: Embodiments include apparatuses, systems, and methods including a memory apparatus including a plurality of bit cells, wherein each of the plurality of bit cells correspond to a respective weight value and include a switch device that has a magnetic tunnel junction (MTJ) or other suitable resistive memory element to produce stochastic switching. In embodiments, the switch device may produce a switching output according to a stochastic switching probability of the switch device. In embodiments, a bit line or a source line passes a current across the MTJ for a switching time associated with the stochastic switching probability to produce the switching output which enables a determination of whether the respective weight value is to be updated. Other embodiments may also be described and claimed.

Abstract: According to one embodiment, a nonvolatile semiconductor memory includes a semiconductor substrate, a first substrate area in the semiconductor substrate, a first cell unit in the first substrate area, the first cell unit including a first memory cell and a first transistor, and the first transistor having a control terminal connected to a first word line, using the first substrate area as a channel and supplying a read current or a write current to the first memory cell, and a substrate potential setting circuit setting the first substrate area to a first substrate potential when the read current is supplied to the first memory cell, and setting the first substrate area to a second substrate potential different from the first substrate potential when the write current is supplied to the first memory cell.

Abstract: An in-plane SOT MRAM non-volatile memory cell has enhanced thermal stability due to coercive pinning provided by an adjacent antiferromagnetic layer that has a thickness that is less than a minimum critical thickness needed to provide exchange bias.

Abstract: Embodiments of the invention describe a dynamic random access memory (DRAM) device that may abort a self-refresh mode to improve the exit time from a DRAM low power state of self-refresh. During execution of a self-refresh mode, the DRAM device may receive a signal (e.g., a device enable signal) from a memory controller operatively coupled to the DRAM device. The DRAM device may abort the self-refresh mode in response to receiving the signal from the memory controller.

Abstract: A memory subsystem enables a refresh abort command. A memory controller can issue an abort for an in-process refresh command sent to a memory device. The refresh abort enables the memory controller to more precisely control the timing of operations executed by memory devices in the case where a refresh command causes refresh of multiple rows of memory. The memory controller can issue a refresh command during active operation of the memory device, which is active operation refresh as opposed to self-refresh when the memory device controls refreshing. The memory controller can then issue a refresh abort during the refresh, and prior to completion of the refresh. The memory controller thus has deterministic control over both the start of refresh as well as when the memory device can be made available for access.

Abstract: A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

Abstract: A semiconductor memory device may include: a memory cell region including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; and a refresh control block suitable for performing a first refresh operation onto the plurality of the word lines in response to a refresh signal, counting the number of active signals that are inputted between at least two neighboring refresh signals and when the counted number of the active signals is equal to or greater than a reference number, performing a second refresh operation onto a word line corresponding to a target address.

Abstract: A volatile resistive memory device includes a resistive memory element including a barrier material portion and a charge-modulated resistive memory material portion. The barrier material portion includes a material selected from germanium and a silicon-germanium alloy, and the charge-modulated resistive memory material portion includes a non-filamentary, electrically conductive metal oxide. The resistive memory device may be a volatile eDRAM device. In operation, reading a resistance state of the resistive memory element does not disturb the resistance state of the charge-modulated resistive memory material portion.

Abstract: A fine grained negative wordline scheme for SRAM memories is disclosed. The scheme includes a circuit having a static random access memory (SRAM) cell including at least a wordline coupled to a plurality of NFETs of a transistor array. The circuit further includes a wordline driver including a plurality of inverters coupled between a wordline group decode node, a power supply and the wordline. Overvoltage on the wordline driver and NFETs of the SRAM cell are eliminated by applying a power gating mode and lowering the power supply voltage.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a static random access memory assist circuit and methods of implementation and manufacture. The structure includes at least one static random access memory (SRAM) cell and a read assist circuit structured to apply a negative voltage to the at least one SRAM cell upon asserting of a wordline of the at least one SRAM cell.

Abstract: A data output circuit includes: a first data latch unit enabled in response to a first bank selection signal including clock information, for storing first lower bank data and first upper bank data in response to a first input control signal, and outputting lower preliminary output data and upper preliminary output data in response to an output control signal; a second data latch unit enabled in response to a second bank selection signal including clock information, for storing second lower bank data and second upper bank data in response to a second input control signal, and outputting the lower preliminary output data and the upper preliminary output data in response to the output control signal; and a data output unit for driving the lower preliminary output data to send rising output data, and synchronizing the upper preliminary output data with the clock to send falling output data.

Abstract: An SRAM with a first bitcell array having a first density and a first access speed, and a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed. The SRAM further includes a first set of wordline drivers coupled to the first bitcell array, a second set of wordline drivers coupled to the second bitcell array, and a row decoder coupled to both the first and second bitcell arrays.

Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, an internal processing circuit, and an error correction circuit. The control logic circuit generates an internal processing mode signal in response to a command from a memory controller. The internal processing circuit selectively performs the internal processing operation on a first set of data read from the memory cell array to output a processing result data, in response to the internal processing mode signal. The error correction circuit performs an error correction code (ECC) encoding on the processing result data to generate a second parity data and stores the processing result data and the second parity data in the memory cell array. The error correction circuit generates the second parity data by selecting the same ECC of a plurality of ECCs as a first ECC.

Abstract: Provided is a programming method of a nonvolatile memory device including a plurality of memory cells. The programming method of the nonvolatile memory device includes: programming a first set of memory cells of the plurality of memory cells to a target state based on a primary program voltage such that a threshold voltage distribution of the first set of memory cells is formed; grouping the first set of memory cells into a plurality of cell groups at least one cell group having a different threshold voltage distribution width from others, based on program speeds of the first set of memory cells; and reprogramming remaining cell groups other than a first cell group that is programmed to the target state among the plurality of cell groups, to the target state based on a plurality of secondary program voltages determined based on threshold voltage distribution widths of the plurality of cell groups.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.

Abstract: To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a resistive random access memory (ReRAM) array is provided. The ReRAM array includes a plurality of memory cells each comprising resistive memory material formed into a layer of a substrate, with resistance properties of the resistive memory material corresponding to data bits stored by the memory cells. The ReRAM array also includes a plurality of interconnect features each comprising conductive material between adjacent memory cells formed into the layer of the substrate, and gate portions coupled onto the memory cells and configured to individually alter the resistance properties of the resistive memory material of associated memory cells responsive to at least voltages applied to the gate portions.

Abstract: A device for determining an actual cell state of a resistive memory cell having a plurality M of programmable cell states comprising a sensing circuit, a settling circuit, a prebiasing circuit, and a resistor coupled in parallel to the resistive memory cell, wherein the resistor is configured to reduce an effective resistance seen by the prebiasing circuit. The sensing circuit is configured to sense a sensing voltage of the resistive memory cell and output a resultant value in response to the sensing voltage which is indicative for the actual cell state. The settling circuit is configured to settle the sensing voltage to a certain target voltage representing one of the M programmable cell states. The prebiasing circuit is configured to prebiase a bitline capacitance of the resistive memory cell such the sensing voltage is close to the certain target voltage.

Abstract: According to one embodiment, a memory device includes a sense amplifier including a first input node and a second input node, a first path including a memory cell to be selectively connected to the first input node, and a second path including a reference cell to be selectively connected to the second input node, and is configured to change an input value at the second input node in accordance with the state of the memory cell.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Abstract: According to one embodiment, a semiconductor memory device includes a cell transistor coupled to a word line, a sense amplifier configured to output data based on a state of the cell transistor in response to a first signal asserted; and a controller configured to apply a voltage of a magnitude continuously rising to the word line, and periodically assert the first signal after a lapse of any selected one of a first time and a second time from the start of rise of the magnitude of the voltage. The first time is different from the second time.

Abstract: Memory devices are shown that include a body region and a connecting region that is formed from a semiconductor with a lower band gap than the body region. Connecting region configurations can provide increased gate induced drain leakage during an erase operation. Configurations shown can provide a reliable bias to a body region for memory operations such as erasing, and containment of charge in the body region during a boost operation.

Abstract: Methods of operating a memory include applying a first voltage level to a first semiconductor material of a first conductivity type forming a channel region for a memory cell of a string of series-connected memory cells, wherein the first semiconductor material is electrically connected to a second semiconductor material of the first conductivity type through a first conductive material of a second conductivity type different than the first conductivity type, and wherein the second semiconductor material forms a channel region for a different memory cell of the string of series-connected memory cells; and applying a second voltage level, less than the first voltage level, to a control gate of the memory cell and applying a third voltage level, less than the second voltage level, to a control gate of the different memory cell while applying the first voltage level to the first semiconductor material.

Abstract: A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

Abstract: A semiconductor device includes a first circuit configured to generate a first voltage based on a first current, a second circuit that includes a first transistor of a first conductivity type having a first terminal, a second terminal, and a first gate, the second circuit configured to generate a second voltage based on a voltage difference between the first terminal and the second terminal, and a third circuit configured to compare the first voltage and the second voltage, and generate a third voltage for adjusting a substrate bias of the first transistor, based on the comparison result.

Abstract: According to one embodiment, A level shifter includes a first circuit configured to generate a first signal, the first signal being inverted and delayed signal of a second signal, a NAND circuit including a first input terminal and a second input terminal, the second signal being input to the first terminal, the first signal being input to the second terminal, a first transistor, a first voltage being applied to a first terminal of the first transistor, a second terminal of the first transistor being connected to a third input terminal of the NAND circuit, a third signal which inverts the second signal being applied to a gate of the first transistor, a second transistor, a second voltage being applied to a first terminal of the second transistor, the second voltage being higher than the first signal, a gate of the second transistor being connected to an output terminal, a third transistor, the second voltage being applied to a first terminal of the third transistor, a second terminal of the third transistor b

Abstract: According to one embodiment, there is provided a non-volatile semiconductor storage device including a non-volatile memory, a monitoring section, a determining section, and a notification processing section. The non-volatile memory includes a plurality of memory cells driven by word lines and a voltage generating section that generates a read voltage to be applied to the word lines. The monitoring section monitors a change in a threshold distribution of the plurality of memory cells upon performing a read processing to read data from the plurality of memory cells by applying the read voltage to the word lines. The determining section determines a degree of deterioration of the non-volatile memory in accordance with a monitoring result by the monitoring section. The notification processing section notifies a life of the non-volatile memory in accordance with a determining result by the determining section.

Abstract: Systems and methods for improving performance of a non-volatile memory by utilizing one or more tier select gate transistors between different portions of a NAND string are described. A first memory string tier may comprise a first set of memory cell transistors that may be programmed to store a first set of data and a second memory string tier may comprise a second set of memory cell transistors that are arranged above the first set of transistors and that may be programmed to store a second set of data. Between the first set of memory cell transistors and the second set of memory cell transistors may comprise a tier select gate transistor in series with the first set of memory cell transistors and the second set of memory cell transistors. The tier select gate transistor may comprise a programmable transistor or a non-programmable transistor.