Abstract: A thermal desorption apparatus is configured to detect a substance of interest in a sample, the apparatus comprising: a wand configured to support a swab and a detector comprising an analyser arranged to detect a substance of interest, wherein the wand is configured to couple to the detector such that thermal desorption of a sample from the swab provides a part of the sample to the analyser.

Abstract: An ion guide system includes an ion guide with pole rods, a device for laterally introducing an ion species, and a mass spectrometer for analyzing product ions of reactions between different ion species. The device is configured and positioned such that an RF field with at least two-fold rotational symmetry with respect to the axis is generated. The device includes shortened pole rods and/or further electrodes. The pole rods and the further electrodes have at least two-fold rotational symmetry. The symmetry of the RF field allows ions to travel straight ahead through the ion guide with no hindrance. Such arrangements are particularly suitable for bringing together largely loss-free positive and negative ion species for reacting them. The reactions may be used to fragment multiply charged biopolymer ions by electron transfer or to remove excess charges of multiply charged biopolymer ions.

Abstract: A system includes a sample selector device, a chromatographic column selectively connectable to the sample selector device, and a spectrometry analysis device selectively connectable to the sample selector device. The sample selector device is configured to supply multiple individual samples to the chromatographic column to separate components of the individual samples. The sample selector device is also configured to store the separated components of the individual samples. The sample selector device is further configured to supply the separated components of the individual samples to the spectrometry analysis device. In embodiments of the disclosure, the components of the individual samples can be chromatographically separated while the spectrometry analysis device is offline.

Abstract: An ionizing apparatus for ionizing a sample of gaseous fluid. The ionizing apparatus comprises an ionizer configured to provide reactant ions; an ion modifier configured to modify the reactant ions, and a reaction region arranged to receive the modified reactant ions and a sample and to combine the sample with the modified reactant ions to ionize the sample for analysis by a detector configured to identify a substance of interest in the sample.

Abstract: A lamp comprising an envelope (1) of quartz glass surrounding the light source of the lamp is described, wherein an electric conductor (8), for example, an electrode rod, is at least partly embedded in the quartz glass material of the envelope (1). At the conductor (8) is provided with protrusions (15) forming a brush-like structure at this surface. The protrusions (15) preferably have an average length of between 10 ?m and 35 ?m.

Abstract: An apparatus and system for plasma processing a substrate using RF power includes a chamber having walls for housing an electrostatic chuck (ESC) and a top electrode. The top electrode is oriented opposite the ESC to define a processing region. An inner line with a tubular shaped wall is defined within and is spaced apart from the walls of the chamber and is oriented to surround the processing region. The tubular shaped wall extends a height between a top and a bottom. The tubular shaped wall has functional openings for substrate access and facilities access and dummy openings oriented to define symmetry for selected ones of the functional openings. A plurality of straps are connected to the bottom of the tubular shaped wall of the inner liner and are electrically coupled to a ground ring within the chamber to provide an RF power return path during plasma processing.

Abstract: A method for cleaning a substrate includes supplying to a substrate a film-forming processing liquid which includes a volatile component and forms a film on the substrate, vaporizing the volatile component in the film-forming processing liquid such that the film-forming processing liquid solidifies or cures on the substrate and forms a processing film on the substrate, supplying to the substrate having the processing film a strip-processing liquid which strips the processing film from the substrate, and supplying to the processing film formed on the substrate a dissolving-processing liquid which dissolves the processing film after the supplying of the strip-processing liquid.

Abstract: A method of fabricating a semiconductor device including an interlayer insulating layer and interconnections is provided. An interlayer insulating layer is formed on a substrate. An opening is formed in the interlayer insulating layer. A degassing process is performed by irradiating the interlayer insulating layer having the opening with microwaves. A K-value recovery process is performed by irradiating the interlayer insulating layer having the opening with UV light. A conductive layer is formed in the opening. The degassing process and the K-value recovery process are performed as an in-situ process.

Abstract: A frame and a mask assembly having the same. The frame supports both ends of each unit mask, each unit mask applying a tensile force in a first direction. The frame includes a frame main body part forming an opening exposing the unit mask, and a first through hole formed by passing through the frame main body part.

Abstract: A semiconductor manufacturing method includes setting a relative position between first through holes of a first plate-shaped part and second through holes of a second plate-shaped part to a first relative position. The method includes supplying a first gas containing a component of the first film onto the semiconductor substrate in a reactor through the first through holes not closed with the second plate-shaped part, to form the first film on the semiconductor substrate. The method includes relatively moving the first plate-shaped part and the second plate-shaped part to change the relative position to a second relative position. The method includes supplying a second gas containing a component of the second film onto the semiconductor substrate through the first through holes not closed with the second plate-shaped part, to laminate the second film on the first film.

Abstract: A method of manufacturing a semiconductor device includes forming an oxide film containing a metal element on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: supplying a precursor containing a metal element and a halogen group to the substrate; and supplying an oxidant to the substrate. In the act of supplying the oxidant, a catalyst is supplied to the substrate together with the oxidant. In the act of supplying the precursor, the catalyst is not supplied to the substrate.

Abstract: Device structures for field-effect transistors and methods of forming device structures for a field-effect transistor. A first dielectric layer is formed on a semiconductor layer and nitrided. A nitrogen-enriched layer is formed at a first interface between the first dielectric layer and the semiconductor layer. Another nitrogen-enriched layer is formed at a second interface between the semiconductor layer and a second dielectric layer. Device structures may include field-effect transistors that include one, both, and/or neither of the nitrogen-enriched layers.

Abstract: An epitaxial base is provided. The epitaxial base includes a substrate and a carbon nanotube layer. The substrate has an epitaxial growth surface and defines a plurality of grooves and bulges on the epitaxial growth surface. The carbon nanotube layer covers the epitaxial growth surface, wherein a first part of the carbon nanotube layer is attached to top surfaces of the plurality of bulges, a second part of the carbon nanotube layer is attached to bottom surfaces of the plurality of grooves, the second part of the carbon nanotube layer is separated from the first part of the carbon nanotube layer, and side surfaces of the plurality of grooves are free of carbon nanotubes.

Abstract: Provided is a method for creating a mask blank that includes a capping layer and a shifter layer. The capping layer is optically compatible and process compatible with the shifter layer. The method may include providing a cleaned and polished mask substrate to a deposition tool and depositing, within the deposition tool, a shifter layer over a cleaned and polished mask substrate. The shifter layer may include each material of a set of materials in a first proportion. The method may also include depositing an additional layer over the shifter layer, the additional layer providing a capping layer over the shifter layer. The capping layer includes the materials in a second proportion unequal to the first proportion. The capping layer includes molybdenum, silicon, and nitride in a proportion that aids in detection by a residual gas analyzer. Also provided is also a mask blank structure incorporating the compatible capping layer.

Abstract: A method includes providing a structure having a dielectric layer, a 1st hardmask layer, a 2nd hardmask layer and a 1st mandrel layer disposed respectively thereon. A 1st mandrel plug is disposed in the 1st mandrel layer. A 2nd mandrel layer is disposed over the 1st mandrel layer. The 1st and 2nd mandrel layers are etched to form a plurality 1st mandrels, wherein the 1st mandrel plug extends entirely through a single 1st mandrel. The 1st mandrel plug is etched such that it is self-aligned with sidewalls of the single 1st mandrel. The 1st mandrels are utilized to form mandrel metal lines in the dielectric layer. The 1st mandrel plug is utilized to form a self-aligned mandrel continuity cut in a single mandrel metal line formed by the single 1st mandrel.

Abstract: A method of doping a substrate. The method may include implanting a dose of a helium species into the substrate through a surface of the substrate at an implant temperature of 300° C. or greater. The method may further include depositing a doping layer containing a dopant on the surface of the substrate, and annealing the substrate at an anneal temperature, the anneal temperature being greater than the implant temperature.

Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an anti-punch through implant (APT) region formed in the fin structure and a barrier layer formed on the APT region. The barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion. The FinFET device structure further includes an epitaxial layer formed on the barrier layer.

Abstract: A MOS transistor having a gate insulator including a dielectric of high permittivity and a conductive layer including a TiN layer, wherein the nitrogen composition in the TiN layer is sub-stoichiometric in its lower portion and progressively increases to a stoichiometric composition in its upper portion.

Abstract: In accordance with an embodiment, a substrate treatment apparatus includes a housing, a magnetic field generating portion and a microwave supply portion. The housing is configured to contain a substrate comprising a conductive layer and an insulating film in contact with the conductive layer. The magnetic field generating portion is configured to generate a magnetic field which penetrates the substrate. The microwave supply portion is configured to generate a microwave to heat the substrate, to apply the microwave to the substrate provided in the magnetic field in such a manner that the microwave is absorbed by unpaired electrons at an interface between the conductive layer and the insulating film or in the insulating film.

Abstract: This invention relates to an apparatus, system, and method for creating a high-k gate stack structure that includes a passivation layer. The passivation layer can be constructed from a deposition of silicon carbide. The silicon carbide provides robustness against oxidation, which can reduce the capacity of the stack. The silicon carbide is thermodynamically stable during the deposition process and results in a clean interface.

Abstract: A substrate processing method according to the present disclosure includes: a liquid processing process of supplying a processing liquid to a substrate having a surface on which a pattern having a plurality of convex portions is formed; a drying process of removing the processing liquid existing on the surface of the substrate dry the substrate, and a separating process of separating a sticking portion between adjacent ones of the convex portions after the drying process.

Abstract: Provided is a method of fabricating a semiconductor device including the following steps. A substrate is provided. A material layer having an opening is formed on the substrate. A first passivation material layer is formed on sidewalls of the opening and on the substrate. A treatment process is performed to the first passivation material layer to form a second passivation material layer. A first surface of the second passivation material layer and a second surface (at an inner side) of the second passivation material layer are differ in a property, and the first surface is located at a side of the second passivation material layer relatively away from the material layer.

Abstract: An embodiment of a method of forming a portion of a memory array includes forming a conductor with a concentration of germanium that decreases with an increasing thickness of the conductor, removing a portion of the conductor at a rate governed by the concentration of germanium to form a tapered first opening through the conductor, removing a sacrificial material below the conductor to form a second opening contiguous with the tapered first opening, and forming a semiconductor in the contiguous first and second openings, wherein a portion of the semiconductor pinches off within the first opening adjacent an upper surface of the conductor before the contiguous first and second openings are completely filled with the semiconductor.

Abstract: Apparatuses suitable for etching substrates at various pressure regimes are described herein. Apparatuses include a process chamber including a movable pedestal capable of being positioned at a raised position or a lowered position, showerhead, and optional plasma generator. Apparatuses may be suitable for etching non-volatile metals using a treatment while the movable pedestal is in the lowered position and a high pressure exposure to organic vapor while the movable pedestal is in the raised position.

Abstract: When a plating layer is formed on through holes in semiconductor packages, first and second stacked bodies are stacked with first and second cavities formed in the first and second stacked bodies facing the inner side and are bonded together by applying adhesive to peripheral regions so that the cavities of the first and second stacked bodies form sealed spaces, and the through holes are formed such that part of the first and second stacked bodies including the bonding surface remains. Then, the through holes are plated to form the plating layer, the peripheral regions are removed as cutting allowances, i.e., removal regions, and the first and second stacked bodies are divided into a plurality of pieces along dicing lines to form semiconductor packages.

Abstract: A method of manufacturing an electronic module includes providing a conductive strip and a dielectric material. The method includes coating the dielectric material and the conductive strip to form a layered structure having a conductive layer defined by the conductive strip and a dielectric layer defined by the dielectric material. The method includes applying a carrier strip to the layered structure. The method includes processing the conductive layer to form a circuit while the layered structure is on the carrier strip. The method includes removing the carrier strip from the layered structure. The method includes applying the layered structure with the circuit to an electronic module substrate.

Abstract: A method for fabricating a semiconductor chip is disclosed. In an embodiment, the method includes providing a carrier, providing a plurality of semiconductor chips, the semiconductor chips each including a first main face and a second main face opposite to the first main face and side faces connecting the first and second main faces, placing the semiconductor chips on the carrier with the second main faces facing the carrier, and applying an encapsulation material to the side faces of the semiconductor chips.

Abstract: A semiconductor structure includes a molding compound, a conductive plug, and a cover. The conductive plug is in the molding compound. The cover is over a top meeting joint between the conductive plug and the molding compound. The semiconductor structure further has a dielectric. The dielectric is on the cover and the molding compound.

Abstract: A substrate liquid processing apparatus of the present disclosure supplies a plurality of processing liquids from a processing liquid supplying unit in a switching manner to a substrate held on a substrate holding unit. An elevatable inner cup surrounds the substrate holding unit laterally and forms a first drain path that drains the first processing liquid. An outer cup surrounds the inner cup and forms a second drain path that drains the second processing liquid. A cover covers the outside of the outer cup, includes an eaves portion that extends inwardly from an upper side, and forms an exhaust path between the cover and the outer cup. The exhaust path is connected to the first drain path and the second drain path above inlets of the first drain path and the second drain path.

Abstract: Techniques for reducing particle contamination on a substrate are disclosed. In one particular exemplary embodiment, the technique may be realized with a platen having different regions, where the pressure levels in the regions may be substantially equal. For example, the platen may comprise a platen body comprising first and second recesses, the first recess defining a fluid region for holding fluid for maintaining a temperature of the substrate at a desired temperature, the second recess defining a first cavity for holding a ground circuit; a first via defined in the platen body, the first via having first and second openings, the first opening proximate to the fluid region and the second opening proximate to the first cavity, wherein pressure level of the fluid region may be maintained at a level that is substantially equal to pressure level of the first cavity.

Abstract: Provided is a substrate processing apparatus.

Abstract: Embodiments described herein relate to apparatus and methods of thermal processing. More specifically, apparatus and methods described herein relate to laser thermal treatment of semiconductor substrates by increasing the uniformity of energy distribution in an image at a surface of a substrate.

Abstract: A liquid processing apparatus of the present disclosure performs a liquid processing by supplying a processing liquid to a substrate that is rotating. A substrate holding unit configured to be rotatable around a vertical axis is provided with a holding surface to attract and hold a bottom surface of the substrate horizontally. A guide unit is formed integrally with the substrate holding unit, disposed around the substrate held in the substrate holding unit, and provided at a position equal to or lower than a height of a top surface of a periphery of the substrate. The guide unit includes a guide surface configured to guide the processing liquid. A rotary cup rotates integrally with the substrate holding unit, and guides the processing liquid towards the cup between the rotary cup and the guide unit.

Abstract: A substrate transport apparatus for detecting with high accuracy rubbing between a substrate held in a substrate holding tool, and a support which transports a substrate. The substrate transport apparatus includes: a stage for placing thereon the substrate holding tool; a substrate transport mechanism including the support for the substrate, and a back-and-forth movement mechanism for moving the support, the mechanism configured to transfer a substrate to/from the substrate holding tool; a lifting mechanism for moving the support up and down with respect to the substrate holding tool; a sound amplifying section for amplifying a contact sound generated by contact between a substrate held in the substrate holding tool and the support; and a detection section for detecting rubbing between a substrate and the support based on a detection signal from a vibration sensor which detects a solid-borne sound, propagating through the substrate holding tool, and outputs the detection signal.

Abstract: A method of adsorbing a target object on a mounting table is provided. The mounting table is provided within a processing vessel that partitions a depressurizable space in a processing apparatus which processes a processing target object within the space. Further, the processing apparatus serves as a plasma processing apparatus. The method includes mounting the target object on an electrostatic chuck of the mounting table; and applying three AC voltages having different phases to three electrodes of the electrostatic chuck, respectively.

Abstract: The invention relates to a process for transferring an active layer to a final substrate using a temporary substrate, the active layer comprises a first side having a three-dimensional surface topology, the process comprising: a first step of bonding the first side of the active layer to one side of the temporary substrate; a second step of bonding a second side of the active layer to the final substrate; and a third step of separating the active layer and the temporary substrate; the process being characterized in that the side of the temporary substrate possesses a surface topology complementary to the surface topology of the first side of the active layer, so that the surface topology of the temporary substrate encapsulates the surface topology of the first side of the active layer in the bonding first step.

Abstract: Provided is protective film-forming sheet (2) including: a protective film-forming film (1) having a light transmittance at a wavelength of 1064 nm of 55% or greater and a light transmittance at a wavelength of 550 nm of 20% or less; and a release sheet (21) which is laminated on one or both faces of the protective film-forming film (1). According to this protective film-forming sheet (2), it is possible to form a protective film which allows a workpiece such as a semiconductor wafer to have a modified layer disposed in advance therein by a laser so that the workpiece can be split through the application of force thereon, while preventing grinding marks on the workpiece or a product formed therefrom from being visible to the naked eye.

Abstract: Embodiments of the present invention provide methods for fabricating a semiconductor device with buried local interconnects. One method may include providing a semiconductor substrate with fins etched into the semiconductor substrate; forming a first set of spacers along the sides of the fins; depositing a tungsten film over the top surface of the substrate; etching the tungsten film to form a buried local interconnect; forming a set of gates and a second set of spacers; forming a source and drain region adjacent to the fins; depositing a first insulating material over the top surface of the substrate; and creating contact between the set of gates and the source and drain region using an upper buried local interconnect.

Abstract: To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film. The semiconductor device further has a first opening portion penetrating through the second insulating film and reaching the first insulating film, a second opening portion penetrating through the first insulating film and reaching the semiconductor substrate, and a trench portion formed in the semiconductor substrate. A first opening width of the first opening portion and a second opening width of the second opening portion are greater than a trench width of the trench portion. The trench portion is closed by a third insulating film while leaving a space in the trench portion.

Abstract: Provided is an SOI wafer manufacturing method that allows production of an SOI wafer having a high gettering ability and a small resistance variance in a thickness direction of an active layer, at high productivity. The SOI wafer manufacturing method includes a first step of implanting light element ions to a surface of at least one of a first substrate and a second substrate to form, on the at least one of the first substrate and the second substrate, a modified layer in which the light element ions are present in solid solution, a second step of forming an oxide film on a surface of at least one of the first substrate and the second substrate, a third step of bonding the first substrate and the second substrate according to a bonding thermal processing, and a fourth step of obtaining an active layer by thinning the first substrate.

Abstract: A method of manufacturing an SOI wafer, including (a) forming a thermal oxide film on an SOI layer of an SOI wafer by a heat treatment under an oxidizing gas atmosphere, (b) measuring thickness of the SOI layer after forming the thermal oxide film, (c) performing a batch cleaning, wherein an etching amount of SOI layer is adjusted depending on thickness of the SOI layer measured in step (b) such that thickness of the SOI layer is adjusted to be thicker than a target value after etching, (d) measuring thickness of the SOI layer after batch cleaning, (e) performing a single-wafer cleaning, wherein an etching amount of the SOI layer is adjusted depending on thickness of the SOI layer measured in step (d) such that thickness of the SOI layer is adjusted to be the target value after etching, and removing the thermal oxide film formed in step (a) before or after step (b).

Abstract: A method includes a patterned hard mask layer formed over a substrate. The substrate is etched using the patterned hard mask layer to form a trench therein but leaving at least one elongated portion of the substrate inside the trench. A first isolation layer is formed over the patterned hard mask layer. The first isolation layer fills the trench and covers the at least one elongated portion of the substrate. A portion of the first isolation layer is removed to expose the at least one elongated portion of the substrate. The at least one elongated portion of the substrate is thereafter removed to form a first opening. A second isolation layer is formed over the first opening, the patterned hard mask layer, and the first isolation layer, the second isolation layer sealing the first opening to form an air gap.

Abstract: A plasma processing method performs an etching process of supplying a fluorine-containing gas into a plasma processing space and etching a target substrate, in which a silicon oxide film or a silicon nitride film is formed on a surface of a metal silicide film, with plasma of the fluorine-containing gas (process S101). Then, the plasma processing method performs a reduction process of supplying a hydrogen-containing gas into the plasma processing space and reducing, with plasma of the hydrogen-containing gas, a metal-containing material deposited on a member, of which a surface is arranged to face the plasma processing space, after the etching process (process S102). Thereafter, the plasma processing method performs a removal process of supplying an oxygen-containing gas into the plasma processing space and removing metal, which is obtained by reducing the metal-containing material in the reduction process, with plasma of the oxygen-containing gas (process S103).

Abstract: A method of forming an interconnect structure is provided. The method includes forming a first dielectric layer, and forming an opening in the first dielectric layer. The method also includes applying a gas to the first dielectric layer adjacent to the opening, where after applying the gas to the first dielectric layer adjacent to the opening, a bottom surface of the opening has been planarized. The method also includes etching the first dielectric layer through the opening to expose a first contact underlying the first dielectric layer, and forming a conductive line in the opening.

Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.

Abstract: A method of forming fully aligned vias in a semiconductor device includes forming an Mx level interconnect line embedded in an Mx interlevel dielectric (ILD). The Mx level interconnect is recessed below the Mx interlevel dielectric or a dielectric is selectively deposited on the Mx interlevel dielectric. The method also includes laterally etching the exposed upper portion of the Mx interlevel dielectric bounding the recess or laterally etching the selectively deposited dielectric. A dielectric cap layer and an Mx+1 level interlevel dielectric is deposited on top of the Mx interlevel dielectric, and a via opening is formed.

Abstract: A method is provided which includes dispensing and removing different deposition solutions during an electroless deposition process to form different sub-films of a composite layer. Another method includes forming a film by an electroless deposition process and subsequently annealing the microelectronic topography to induce diffusion of an element within the film. Yet another method includes reiterating different mechanisms of deposition growth, namely interfacial electroless reduction and chemical adsorption, from a single deposition solution to form different sub-films of a composite layer. A microelectronic topography resulting from one or more of the methods includes a film formed in contact with a structure having a bulk concentration of a first element. The film has periodic successions of regions each comprising a region with a concentration of a second element greater than a set amount and a region with a concentration of the second element less than the set amount.

Abstract: Disclosed are a method of forming a seed layer on a high-aspect ratio via and a semiconductor device having a high-aspect ratio via formed thereby. Thus, efficient Cu filling-plating is possible, and plating adhesion of the seed layer to filling-plated Cu can be simply and profitably enhanced, thus imparting high durability upon forming metal wiring for electronic components. Moreover, stress of the seed layer can be lowered, thereby enhancing plating adhesion.

Abstract: A method of forming a conductive structure includes forming a first opening and a second opening in a dielectric layer on a substrate, wherein the first opening is narrower than the second opening. The method further includes depositing a diffusion barrier layer to line the first opening and the second opening. The method further includes forming a metal layer over the diffusion barrier layer to fill at least portions of the first opening and the second opening, wherein a maximum thickness of the metal layer in the first opening is greater than a maximum thickness of the metal layer in the second opening.

Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.