Patents Issued in June 12, 2018
  • Patent number: 9996267
    Abstract: Embodiments of the present invention provide systems and methods for adjusting synchronization rates of volumes. Volumes and their copies (i.e., mirrored volumes) provide physical or virtual storage on a data storage medium. Depending on the function (i.e., the purpose) of mirrored volumes, a certain synchronization rate is recommended. Embodiments of the present invention provide systems and methods for an automatic dynamic adjustment of individual synchronization rates by adapting to changes in system workloads in order to avoid degradation of user-driven input/output (IO) and to efficiently achieve nearly 100% synchronization for all mirrored volumes.
    Type: Grant
    Filed: August 11, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stephen A. Byrd, Scott J. Colbeck
  • Patent number: 9996268
    Abstract: According to one embodiment, a memory system writes data to a first block, and executes a garbage collection when the number of free blocks is not greater than a first threshold value. The memory system calculates a first number which is a ratio of the number of copy destination blocks needed for the garbage collection to the number of blocks to which data designated by a write command is written. The memory system determines whether the first number is greater than a second threshold value when a first command is received from the host, and performs fill-up processing for the first block when the first number is not greater than the second threshold value.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: June 12, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Ryuji Nishikubo, Hiroki Matsudaira, Norio Aoyama
  • Patent number: 9996269
    Abstract: Method including receiving first and second identification data relative to data blocks to be transmitted via data bus between processor and system memory. Listening data transmitted via data bus to detect block data corresponding to the first or second identification data; storing in a first location of temporary storage a first data block transmitted via bus and corresponding to first identification data; storing in a second location of temporary storage a second data block transmitted via bus and corresponding to the second identification data. The storing of the first and second data blocks being performed without disturbing transfer of the first and second data blocks via data bus. When the first and/or second data blocks are stored in the temporary storage activating their respective signature calculator connected to the location of the temporary storage to compute a signature of the data block, and storing the signature in a result memory.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: June 12, 2018
    Inventor: Dmitriy Gusev
  • Patent number: 9996270
    Abstract: Various embodiments for managing data by a processor in a multi-tiered computing storage environment. Input/Output (I/O) statistics are examined from each of cache and device drivers in the computing storage environment. Based on the I/O statistics, a ranking mechanism is applied to differentiate data between at least a cache rank and a Solid State Drive (SSD) rank. The ranking mechanism migrates data between the cache rank and SSD rank such that storage space in the cache rank is reserved for those of the plurality of data workload types having a greater adverse effect on a storage performance characteristic if stored in the SSD rank than if those workload types were stored in the cache rank.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yong Guo, Bruce McNutt, Jie Tian, Yan Xu
  • Patent number: 9996271
    Abstract: A storage controller includes a co-access pattern mining unit configured to detect co-access patterns of data co-accessed during a particular time duration and to generate co-access groups including a plurality of pieces of data complying with the co-access patterns. The storage controller further include a co-access group matching unit configured to select a co-access group matched with read-requested data, among the generated co-access groups, and a data placement unit configured to store the data included in the selected co-access group in a pre-fetch buffer.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung-June Jung, Ju-Pyung Lee, Gae-Won You, Hoshik Lee
  • Patent number: 9996272
    Abstract: A computer program product is provided for storage controller-mediated volume transformation in a shared-resource environment. The computer program product comprises a computer readable storage medium having program instructions embodied therewith. The program instructions are executable by a computer to cause the computer to receive, from an initiating host system, a command to send a notification to other host systems connected to a shared volume. Additionally, the programs instructions are executable by the computer to cause the computer to broadcast an interrupt to the other host systems connected to the shared volume, and receive responses from the other host systems connected to the shared volume. Moreover, the programs instructions are executable by the computer to cause the computer to notify the initiating host system of the responses received from the other host systems connected to the shared volume.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Susan K. Candelaria, John R. Paveza, Dale F. Riedy
  • Patent number: 9996273
    Abstract: A storage system in one embodiment comprises at least one processor, a processor memory, an input-output controller, and a directly-addressable storage device having volatile memory and non-volatile memory. The input-output controller generates a plurality of write commands in conjunction with storage of data in the storage system, the write commands including at least a first write command comprising the data and a second write command comprising one or more interrupts. If an address of a given one of the write commands falls within a specified interrupt group window, the write command is copied to the directly-addressable storage device so as to provide at least one of the one or more interrupts to that storage device. The directly-addressable storage device responds to receipt of the interrupt by writing data from the volatile memory to the non-volatile memory and generating a corresponding additional interrupt to the processor.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 12, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Steven Sardella, Walter A. O'Brien, III
  • Patent number: 9996274
    Abstract: A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: June 12, 2018
    Assignee: Conversant Intellectual Property Management Inc.
    Inventor: Jin-Ki Kim
  • Patent number: 9996275
    Abstract: A transition tool estimates a cutover time in a copy-free transition of storage objects. The transition tool determines how many storage objects of each type of storage object there are to transition from a source storage system to a destination storage system. The transition tool can measure an operation time for both the source storage system and the destination storage system. The transition tool can estimate an export duration using the source storage system operation time, the number of each type of storage object, and a number of operations for that type of storage object. The transition tool can estimate an import duration using the destination storage system operation time, the number of each type of storage object, and a number of operations for that type of storage object. A total cutover time can then be calculated from the export and import durations.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: June 12, 2018
    Assignee: NetApp Inc.
    Inventors: Vijaya Bhaskar Reddy C H, Vani Vully, Ravi Anapindi, Vasudev Mulchandani
  • Patent number: 9996276
    Abstract: According to one embodiment, a memory system includes, as an example, a temperature information receiver that receives temperature information; and a gradient determining unit that determines a gradient related to a temperature increase, based on the temperature information about a plurality of temperatures received by the temperature information receiver.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 12, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Akira Hikimura, Takayuki Tamura
  • Patent number: 9996277
    Abstract: This technology relates to a memory system for processing data into a memory device and an operating method of the same. The memory system may include a memory device comprising one or more closed memory blocks each including plural pages, and a controller suitable for generating valid page counts (VPCs) for each closed memory block at least two different time points, generating a VPC offset for each closed memory block between the at least two different time points, selecting a source memory block among the closed memory blocks according to the generated VPC offsets, and performing a garbage collection operation to the selected source memory block.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventor: Jong-Min Lee
  • Patent number: 9996278
    Abstract: During normal power operation, an erased free block is prepared in nonvolatile memory so that at least one erased free block is continuously available as a standby block. If a power failure occurs, volatile data and its address conversion information are written into the standby block in the nonvolatile memory.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: June 12, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Tatsuya Zettsu
  • Patent number: 9996279
    Abstract: Various embodiments are directed to providing integrity protection for a system management mode. During initialization, a hash value of a system management mode control routine may be determined. Subsequently, during operation, the hash value may be compared to a hash value of a system management mode control routine to be executed. The system management mode control routine to be executed may be determined to be authentic if the hash values are the same.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: June 12, 2018
    Assignee: INTEL CORPORATION
    Inventors: Jorge E. Gonzalez Diaz, Juan Manuel Cruz Alcaraz
  • Patent number: 9996280
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for data register copying for a non-volatile storage array. An apparatus may include an array of non-volatile storage cells. A set of write buffer data registers may be configured to store target data for a program operation for an array. Write buffer data registers may communicate target data to corresponding columns of an array. A set of shadow data registers may be configured to receive target data from peripheral circuitry for an array. A portion of target data received by a shadow data register may be copied to a corresponding write buffer data register while the shadow data register receives the portion of the target data.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 12, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventor: Jingwen Ouyang
  • Patent number: 9996281
    Abstract: A data storage device is configured to mark data for refresh in response to determining that a first measured temperature associated with writing the data to the memory exceeds a first threshold. The data storage device is further configured to refresh the marked data in response to determining that a second measured temperature associated with the memory is below a second threshold.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: June 12, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Eran Sharon, Nian Niles Yang, Idan Alrod, Evgeny Mekhanik, Mark Shlick, Joanna Lai
  • Patent number: 9996282
    Abstract: A method of operating a data storage device including a non-volatile memory device includes receiving an update command from a host; and closing a first log block, which is included in the non-volatile memory device and which includes an open word line, in response to the update command. The closing is performed to avoid update data, which is transmitted from the host and related to the update command, being subsequently written to an empty page of the first log block.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Taek Kyun Lee
  • Patent number: 9996283
    Abstract: A method for execution by a dispersed storage and task (DST) processing unit includes generating storage unit performance data based on a performance threshold value and storage unit performance values of storage units in a storage unit write set. Storage unit write set data indicating a new storage unit write set based on the storage unit performance data is generated, where at least one slow-performing storage unit is removed from the storage unit write set to create the new storage unit write set when the at least one slow-performing storage unit has a storage unit performance value that compares unfavorably to the performance threshold value. A plurality of write requests are generated for transmission to the new storage unit write set via a network, each including a data slices to be written to a corresponding storage unit of the new storage unit write set.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Jason K. Resch
  • Patent number: 9996284
    Abstract: A memory system that has a multi-channel volatile memory subsystem is coupled to a non-volatile memory subsystem to provide independent, configurable backup of data. The volatile memory subsystem has one or more main memory modules that use a form of volatile memory such as DRAM memory, for which the NV subsystem provides selective persistent backup. The main memory modules are dual in-line memory modules or DIMMs using DDR SDRAM memory devices. The non-volatile memory subsystem (NV backup) includes an NV controller and non-volatile memory NVM. The NV backup can also include a memory cache to aid with handling and storage of data. In certain embodiments, the NV controller and the non-volatile memory are coupled to the one or more DIMM channels of the main memory via associated signal lines. Such signal lines can be, for example, traces on a motherboard, and may include one or more signal buses for conveying data, address, and/or control signals.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: June 12, 2018
    Assignee: Netlist, Inc.
    Inventor: Hyun Lee
  • Patent number: 9996285
    Abstract: Memory systems may include a memory storage including at least a first stripe and a second stripe, the first stripe including data pages corresponding to the first stripe and a first parity page suitable for storing a first XOR parity, and the second stripe including data pages corresponding to the second stripe and a second parity page suitable for storing a second XOR parity, the data pages and parity pages being stored over a plurality of memory dies, wherein each memory die includes a number of planes; and a controller suitable for cyclically interleaving the data pages corresponding to the first stripe and the data pages corresponding to the second stripe.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventors: Jingyu Kang, Chung-Li Wang, Cai Wang, Yibo Zhang
  • Patent number: 9996286
    Abstract: The present disclosure relates to a data storage system, and processes and computer programs for such data storage system, for example including processing of: managing one or more metadata tree structures for storing data to one or more storage devices of the data storage system in units of blocks, each metadata tree structure including a root node pointing directly and/or indirectly to blocks, and a leaf tree level having one or more direct nodes pointing to blocks, and optionally including one or more intermediate tree levels having one or more indirect nodes pointing to indirect nodes and/or direct nodes of the respective metadata tree structure; maintaining the root node and/or nodes of at least one tree level of each of at least one metadata structure in a cache memory; and managing I/O access to data based on the one or more metadata structures.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 12, 2018
    Assignee: Hitachi, Ltd.
    Inventors: Mitsuo Hayasaka, Christopher James Aston, Jonathan Mark Smith, Yuko Matsui, Simon Latimer Benham, Trevor Edward Willis
  • Patent number: 9996287
    Abstract: According to certain aspects, a system includes a client device that includes a virtual machine (VM) executed by a hypervisor, a driver located within the hypervisor, and a data agent. The VM may include a virtual hard disk file and a change block bitmap file. The driver may intercept a first write operation generated by the VM to store data in a first sector, determine an identity of the first sector based on the intercepted write operation, determine an entry in the change block bitmap file that corresponds with the first sector, and modify the entry in the change block bitmap file to indicate that data in the first sector has changed. The data agent may generate an incremental backup of the VM based on the change block bitmap file in response to an instruction from a storage manager, where the incremental backup includes the data in the first sector.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: June 12, 2018
    Assignee: Commvault Systems, Inc.
    Inventors: Henry Wallace Dornemann, Rahul S. Pawar
  • Patent number: 9996288
    Abstract: In one embodiment, a system includes a disk cache that includes a plurality of hard disk drives (HDDs) and a controller. The controller is configured to create one or more tape-managed partitions in the disk cache, each of the one or more tape-managed partitions being configured to store data that is subject to hierarchical storage management (HSM). The controller is also configured to create a premigration queue configured to service premigration data for all of the one or more tape-managed partitions. Moreover, the controller is configured to receive a premigration delay value for a first tape-managed partition, the premigration delay value defining a time period that elapses prior to queuing the premigration data for the first tape-managed partition to the premigration queue. The premigration delay value is based on a volume creation time. Other systems, methods, and computer program products are described in accordance with more embodiments.
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Norie Iwasaki, Katsuyoshi Katori, Koichi Masuda, Joseph M. Swingler
  • Patent number: 9996289
    Abstract: Embodiments of the present disclosure provide a method and apparatus for assigning lock resources to objects by obtaining a first alternative lock for the object, and determining first correlations between the object and each of one or more other objects when the first alternative lock has been assigned to the one or more other objects, wherein in response to determining that each of the first correlations is lower than a predetermined threshold, assign the first alternative lock to the object, and may maximize the possibility of parallel execution and reduce the time waiting for lock resources, thereby avoiding lock contention.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: June 12, 2018
    Assignee: EMC IP HOLING COMPANY LLC
    Inventors: Walter Lei Wang, Matt Zhu Zhang, Gang Cao, Ren Ren, Xiangqing Yang
  • Patent number: 9996290
    Abstract: Embodiments include providing content requested by a user via an access point capable of wireless communication. Aspects include receiving the content provided by the management server and storing the content provided by the management server into a volatile memory provided in the wireless communication apparatus. Aspects also include storing difference data into a nonvolatile memory if it is requested to change the content stored in the volatile memory and monitoring a state of communication connection with the access point and whether or not a packet giving an instruction to hold the content has been received. Aspects further include deleting the content stored in the volatile memory if communication with the access point is disconnected or if the packet is unreceived.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Yasunao Katayama, Daiju Nakano, Kohji Takano
  • Patent number: 9996291
    Abstract: A storage system in one embodiment comprises a host processor, a volatile memory associated with the host processor, and a solid-state storage device comprising a non-volatile memory. The host processor is configured to detect a particular power condition, such as a power failure condition, and responsive to the detected power condition to direct the copying of data from the volatile memory associated with the host processor to the non-volatile memory of the solid-state storage device. In conjunction with directing the copying of data from the volatile memory associated with the host processor to the non-volatile memory of the solid-state storage device, the host processor further directs the solid-state storage device to enter an enhanced write bandwidth operating mode in which the solid-state storage device temporarily at least partially suspends at least one specified background process that would otherwise tend to restrict an achievable write bandwidth of the solid-state storage device.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: June 12, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Amnon Izhar, Patrick Weiler
  • Patent number: 9996292
    Abstract: A memory system includes: a non-volatile memory device including a normal region in which Most Significant Bits (MSBs) and Least Significant Bits (LSBs) stored in memory cells are accessed simultaneously, a hot region in which MSBs stored in memory cells are accessed, and a cold region in which LSBs stored in memory cells are accessed; and a memory controller controlling the non-volatile memory device, Herein, the memory controller includes: a read/write counter that counts the number of read operations and the number of write operations that are performed for each of logical cluster to thereby produce a counting result; and a region selector that maps each logical cluster to one among the normal region, the hot region and the cold region based on the counting result to thereby produce mapping data.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventors: Dong-Gun Kim, Jung-Hyun Kwon
  • Patent number: 9996293
    Abstract: A method for managing memory allocation in a database receives an invocation of a stored statement defined to allocate objects, each with a stored size. The method determines an actual size relating to the invocation and determines a preferred statement among defined statements with defined object sizes. The defined statements include the stored statement and alternative stored statements that provide an alternative implementation of the stored statement defined to allocate the objects with alternative sizes lower than stored sizes. The preferred statement has defined sizes compliant to actual sizes according to preference criterion based on comparing defined and actual sizes. The method invokes the preferred statement for execution in place of the stored statement when different. The method stores a new statement, having new sizes compliant to actual sizes according to alternate criterion, responsive to unfullfilling a condition based on comparing defined sizes of the preferred statement with actual sizes.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Valerio Bellizia, Stefano Sidoti
  • Patent number: 9996294
    Abstract: A computer-implemented method according to one embodiment includes receiving a request to initialize a storage device, identifying a size of the storage device to be initialized, determining a size of a table of contents and a location for the table of contents within the storage device, based on the identified size of the storage device to be initialized, determining a type of the table of contents; and initializing the storage device, utilizing the determined size of the table of contents, the determined location for the table of contents, and the determined type of the table of contents.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Michael J. Koester, Kevin L. Miner, Trinh Huy Nguyen, Carrie J. Van Noorden
  • Patent number: 9996295
    Abstract: A semiconductor memory device and a scrambling method thereof are provided, which are capable of realizing a balance between a data scrambling function and an accessible time. The semiconductor memory device of the invention includes a page buffer/sense circuit with the data scrambling function. During a programming operation, the page buffer/sense circuit holds data to be programmed, performs a scrambling process on the held data and programs the scrambled data to a selected page of a memory array. During a reading operation, the page buffer/sense circuit holds data read from the selected page and performs a descrambling process on the held data.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 12, 2018
    Assignee: Winbond Electronics Corp.
    Inventor: Naoaki Sudo
  • Patent number: 9996296
    Abstract: An electronic control unit includes: a nonvolatile memory capable of erasing data in units of erasure blocks and also writing data in units of write blocks smaller than the erasure blocks; and a processor. In response to a data rewrite request from outside, the processor of the electronic control unit erases data in a portion of the nonvolatile memory in units of erasure blocks and writes data into the portion of the nonvolatile memory in units of write blocks. The amount of data sent to the electronic control unit from outside is thereby decreased and the time needed to rewrite data in the nonvolatile memory is reduced.
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: June 12, 2018
    Assignee: Hitachi Automotive Systems, Ltd.
    Inventors: Toshifumi Miyake, Yusuke Abe, Koji Yuasa, Toshihisa Arai
  • Patent number: 9996297
    Abstract: A method of data separation includes receiving a host write command operation, identifying temperature of data contained in memory blocks during the host write command operation, selecting a victim block of the memory blocks based on the identified temperature, moving data from the victim block to a destination block, and assigning a sequence number to the destination block when the destination block is full.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventor: Fan Zhang
  • Patent number: 9996298
    Abstract: A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to receipt of the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to receipt of the paste-type request, the lower level cache issues a command to write the data granule from the non-architected buffer to the memory-mapped device. In response to receipt from the memory-mapped device of a busy response, the processor core abandons the memory move instruction sequence and performs alternative processing.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Lakshminarayana B. Arimilli, Guy L. Guthrie, William J. Starke, Jeffrey A. Stuecheli, Derek E. Williams
  • Patent number: 9996299
    Abstract: A data storage device may be configured to write first data to a first set of storage elements of a non-volatile memory and to write second data to a second set of storage elements of the non-volatile memory. The first data may be processed by a data shaping operation, and the second data may not be processed by the data shaping operation. The data storage device may be further configured to read a representation of the second data from the second set of storage cells and to determine a block health metric of a portion of the non-volatile memory based on the representation of the second data. The portion may include the first set of storage elements and the second set of storage elements. As an illustrative, non-limiting example, the first portion may be a first block of the non-volatile memory.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: June 12, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC
    Inventors: Nian Niles Yang, Idan Alrod
  • Patent number: 9996300
    Abstract: A method of using flash memories having an electrically erasable programmable read-only memory emulation in a microcontroller, includes: dividing information to be stored in a computer memory into a first piece of information having executable code, and a second piece of information having non-executable code. If a free storage capacity of a first memory is sufficiently large to receive the first piece of information storing the first piece of information in the first memory. If a free storage capacity of a second memory is sufficiently large to receive the second piece of information, storing the second piece of information in the second memory.
    Type: Grant
    Filed: August 19, 2016
    Date of Patent: June 12, 2018
    Inventor: Arnd Schaffert
  • Patent number: 9996301
    Abstract: Systems and methods for list retrieval in a storage device are provided that significantly reduces the number of commands needed to retrieve data. A single command or request may be issued to receive data stored at a parent node, a child node, and/or a grandchild node. For example, a request may be issued that includes a node corresponding to a particular level, a depth level below that particular level to which to obtain data and/or filter criteria. With this information, the requested information may be obtained to the depth level while filtering out information not included in the request. When the request corresponds to a parent node and information about the children nodes is desired, for example, additional requests are not needed to obtain information from all of the parent node and the children nodes. Thus, the length of time needed to provide certain stored management information is reduced.
    Type: Grant
    Filed: December 15, 2016
    Date of Patent: June 12, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Archana Katarki, James Kremer
  • Patent number: 9996302
    Abstract: A storage device includes a non-volatile semiconductor memory device including a plurality of physical blocks, and a controller configured to associate one of the physical blocks with a stream ID, receive a first command including the stream ID, and in response thereto, transmit information on capacity of unwritten space in the physical block associated with the stream ID.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: June 12, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Daisuke Hashimoto, Shinichi Kanno
  • Patent number: 9996303
    Abstract: A method and a system are provided for improving performance of a hybrid drive including a non-volatile semiconductor memory device partitioned into blocks, each of the blocks containing a plurality of sectors, and a magnetic storage device. Performance of the hybrid drive is improved by tracking data types of each sector stored in the blocks, the data types including a first data type, which is data that is unconditionally available for host accesses, a second data type, which is data that is conditionally available for host accesses, and a third data type, which is data unavailable for host accesses, and collecting erasable blocks from the blocks of the non-volatile semiconductor memory device according to the data types. The erasable blocks include a block that contains data of the second data type, such that the host may access from this block even though this block is erasable.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: June 12, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Richard M. Ehrlich, Eric R. Dunn
  • Patent number: 9996304
    Abstract: The present invention provides a data storage device including a flash memory, a plurality of counting control arrays and a controller. The flash memory includes a plurality of chips, each chip has a plurality of pages arranged to be assembled into a super block according to a predetermined order, and each of the super blocks includes the pages of the different chips. The controller keeps the value of a first field of a first counting control array corresponding to a first chip required to be read and writes a second value into the other fields except for the first field of the first counting control array when the first field is a first value, and writes the first value into the first field and keeps the values of the other fields of the first counting control array when the first field is the second value.
    Type: Grant
    Filed: March 2, 2016
    Date of Patent: June 12, 2018
    Assignee: SILICON MOTION, INC.
    Inventors: Kuan-Lin Chen, Wu-Chi Kuo
  • Patent number: 9996305
    Abstract: A print control method that is capable of canceling the unprintable state without troubling a user. An image forming apparatus performs a print process according to print data transmitted from an information processing apparatus by the print control method. An anomaly detection step detects anomaly in a print related process, which is relevant to the print process, under execution by the information processing apparatus. A state shifting step stops the print process under execution by the image forming apparatus, and makes the image forming apparatus shift to a printable state for preparing a new print process that is different from the print process that the image forming apparatus is executing when anomaly is detected in the print related process. A reboot step reboots the information processing apparatus in response to the shift of the image forming apparatus to the printable state.
    Type: Grant
    Filed: August 17, 2016
    Date of Patent: June 12, 2018
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Munetaka Sakata
  • Patent number: 9996307
    Abstract: An information processing apparatus capable of executing near field wireless communication, comprises: a display unit configured to display a screen; an obtaining unit configured to obtain identification information regarding a device from a near field wireless communication tag with use of the near field wireless communication; a selection unit configured, in a case where the obtaining unit obtained the identification information, to select one of first processing for connecting to the device indicated by the identification information and second processing for connecting to the device indicated by the identification information and sending data to the device, based on a type of screen being displayed by the display unit; and a processing unit configured to execute the processing selected by the selection unit.
    Type: Grant
    Filed: January 20, 2017
    Date of Patent: June 12, 2018
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shukei Kurihara
  • Patent number: 9996308
    Abstract: Provided are a tethering-type head-mounted display (HMD), and a control method thereof. The HMD is in communications with a mobile terminal and includes a display to selectively display content. A sensor detects a state in which the HMD is worn by a user, and the HMD presents notification information about an event detected in the mobile terminal. The controller further pauses, when the sensor senses a change in the state in which the HMD is worn by the user while the notification information is being presented by the display, the presentation of the content, and generates, based on pausing the presentation of the content, bookmark information identifying the content and a point in time when the sensor senses the change in the state in which the HMD is worn by the user.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: June 12, 2018
    Assignee: LG ELECTRONICS INC.
    Inventors: Cheongha Park, Goeun Joo
  • Patent number: 9996309
    Abstract: The present disclosure relates to technologies for sensor networks, machine-to-machine (M2M), machine-type communication (MTC), and Internet of things (IoT). The present disclosure may be used in intelligent services (smart home, smart building, smart city, smart car, or connected car, health-care, digital education, retail business, security and safety-related services, etc.) A method and apparatus for transmitting information in a communication system are provided. According to the present disclosure, an electronic device receives sensing data from at least one sensor, receives a distress signal from at least one user device, and displays search information for guiding to an area to be searched determined based on the sensing data and the distress signal through a display screen of a wearable device.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: June 12, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Eun Lee, Do-Hyun Pyun, Tae-Jin Woo, Seung-Ku Kim, Bo-Seok Moon
  • Patent number: 9996310
    Abstract: Systems and methods for displaying prioritized content using a display array are described herein. In some embodiments, a display array may include two or more display devices, which may render content thereby. If an update or change to the content occurs, or if new content is requested, then that content may be assigned a higher priority level. A computing system may include a device management system that continually monitors the availability of the various display devices of the display array, and based on the content received by an applications management system of the computing system, determines which display device should render which content. For instance, an update to content displayed on a second display device may be caused to be displayed on a first display device in response to the device management system determining that the first display device is to be used for displaying high priority content.
    Type: Grant
    Filed: September 15, 2016
    Date of Patent: June 12, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: David Edward Bliss, Michael Douglas McQueen
  • Patent number: 9996311
    Abstract: System, method, and computer product embodiments for efficiently casting interactively-controlled visual content displayed on a first display screen to a second display screen. In an embodiment, the computing device sends the visual content displayed on the first display screen to a multimedia device for displaying on the second display screen. Upon receipt of an instruction that visually manipulates how the visual content is displayed on the first display screen, the computing device generates a command representative of the received instruction. The command may specify a positional relationship between the center of the first display screen and the visual content displayed on the first display screen. Then, the computing devices sends the command to the multimedia device that causes the second display screen to display the visual content according to the positional relationship.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: June 12, 2018
    Assignee: ROKU, INC.
    Inventors: Gregory S. Gates, Harold Sun, Michael Chin-Ming Fu
  • Patent number: 9996312
    Abstract: Low power consumption is realized focusing on the refresh interval of a low leakage display panel. Display systems and microcomputers are described herein. One embodiment of a display system includes a display driver. The driver receives an enable signal from the outside, stops the display operation of an internal circuit in an inactive state of the enable signal, and resumes the display operation of the internal circuit in an active state. Instead of the enable signal, a command supplied from the outside may be used. When resuming the display operation, the display driver performs control to make the start timing of the display operation earlier for a circuit that requires a long time for activation. A microcomputer that outputs an enable signal or a command controls the output or the output stop of display data according to the state of the enable signal or the command.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: June 12, 2018
    Assignee: Synaptics Japan GK
    Inventor: Kei Miyazawa
  • Patent number: 9996313
    Abstract: Volume limiting systems and methods are operable to limit volume output from media presentation devices. An exemplary embodiment detects a sound using a microphone, wherein the sound corresponds to an audio output of at least one controlled media presentation device, and wherein the microphone is remotely located from the at least one controlled media presentation device; compares a level of the detected sound with a predefined maximum volume limit; generates a volume output limit command in response to the detected sound exceeding the predefined maximum volume limit; and communicates the volume output limit command to the media presentation device. The media presentation device then reduces a volume level of its audio output. In some instances, volume may be limited during user specified periods.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: June 12, 2018
    Assignee: EchoStar Technologies L.L.C.
    Inventor: Bernard A. McCarthy
  • Patent number: 9996314
    Abstract: An audio control apparatus particularly suited for an active outdoor type of person integrates multiple electronic devices. Audio source devices can include a mobile phone, a music player, and a walkie talkie. Audio sink devices can include a video recorder. The audio signals from the audio source devices may be mixed and sent to the video recorder to capture live audio signals. The user controls the audio control apparatus using either integrated or external UI buttons, which are context specific, configurable and allow control of the external devices from a single UI. External UI buttons may be mounted to a helmet or another easy to access location. A USB port on the external UI allows charging the audio control apparatus without needing to access or otherwise disturb the apparatus while it is nicely positioned within the helmet.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: June 12, 2018
    Inventor: Martin T. Sunstrum
  • Patent number: 9996315
    Abstract: Systems and methods of using audio input with a mobile device. A method comprises receiving content at a mobile device; annotating, at the mobile device, a selectable item of a user interface associated with the content with an annotation; receiving, at the mobile device, an audio input associated with the annotation; converting, at the mobile device, the audio input into a user interface command; and causing the mobile device to perform a function in response to the user interface command.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: June 12, 2018
    Assignee: Gula Consulting Limited Liability Company
    Inventor: Melvin L. Barnes, Jr.
  • Patent number: 9996316
    Abstract: Devices, systems, and methods provide synchronization of multiple voice-controlled devices to establish priority of one of the devices to respond to an acoustic signal, preventing other devices from responding to a single user command. Each device is configured to mediate its response to a wakeword by, after detecting the wakeword in an audio input, generating a data packet and attempting to send it to the other devices over a communication channel that prevents data collision. One device will succeed in sending the packet, while the other devices cannot until they receive the first device's packet, indicating that the first device has priority. Additionally, the devices may process their audio inputs to determine a signal quality, the signal qualities are shared between all devices, and the device with the best signal quality assumes priority.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: June 12, 2018
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventor: Milos Jorgovanovic
  • Patent number: 9996317
    Abstract: A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.
    Type: Grant
    Filed: January 31, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventor: Takeo Yasuda