Patents Issued in June 12, 2018
  • Patent number: 9996368
    Abstract: A method, system and computer program product for creating, editing, and generating operating manuals utilizing scripts. Operations performed by an author during manual creation are saved as scripts. The operations are replayed when regenerating or modifying the manual. When replaying the script of the operating manual, the script may be stopped at convenient points to add additional operations and/or modifications. These additional operations and/or modifications are also recorded as scripts to enable generation of the edited/modified manual.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Karim Hamzaoui, Ryo Kamimura, Kentaro Takiguchi
  • Patent number: 9996369
    Abstract: A closed-loop service, referred to as an Adaptive Data Analytics Service (ADAS), characterizes the performance of a system or systems by providing information describing how users or agents are operating the system, how the system components interact, and how these respond to external influences and factors. The ADAS then builds models and/or defines relationships that can be used to optimize performance and/or to predict the results of changes made to the system(s). Subsequently, this learning provides the basis for administering, maintaining, and/or adjusting the system(s) under study. Measurement can be ongoing, even after the operating parameters or controls of a system under the administration or monitoring of the ADAS have been adjusted, so that the impact of such adjustments can be determined.
    Type: Grant
    Filed: December 14, 2015
    Date of Patent: June 12, 2018
    Assignee: Anki, Inc.
    Inventors: Patrick DeNeale, Tom Eliaz
  • Patent number: 9996370
    Abstract: Disclosed are examples of memory allocation and reallocation for virtual machines operating in a shared memory configuration creating a swap file for at least one virtual machine. One example method may include allocating guest physical memory to the swap file to permit the at least one virtual machine to access host physical memory previously occupied by the guest physical memory. The example method may also include determining whether an amount of available host physical memory is below a minimum acceptable level threshold, and if so then freeing at least one page of host physical memory and intercepting a memory access attempt performed by the at least one virtual machine and allocating host physical memory to the virtual machine responsive to the memory access attempt.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: June 12, 2018
    Assignee: Open Invention Network LLC
    Inventors: Farid Khafizov, Andrey Mokhov
  • Patent number: 9996371
    Abstract: A virtual switching method, a related apparatus, and a computer system are provided. The method includes receiving a first message sent by a source node, where the first message is used to request a first virtual machine to perform switching processing on to-be-switched data, where the to-be-switched data is sent from the source node to a target node and at least one of the source node and the target node is a second virtual machine; and determining a second message according to an address of the target node contained in the to-be-switched data and a configured port mapping table, and sending the second message, where the second message is used to instruct the target node to acquire the to-be-switched data from a storage device of a hardware layer.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: June 12, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Yang Lin, Kun Zheng
  • Patent number: 9996372
    Abstract: An information processing apparatus includes a time determination processor which determines a time for acquiring state information on an operation system, from the operation system, on the basis of a processing status of tasks executed by the operation system, the processing status being acquired from the operation system, an information acquisition processor which acquires the state information and stores the state information in a storage, at the determined time for acquiring state information, and an information reply processor which sends back the state information stored in the storage, when an acquisition request for the state information is received from any of one or a plurality of monitoring apparatuses which monitor the operation system.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: June 12, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Katsuhiko Ono
  • Patent number: 9996373
    Abstract: An approach for avoiding overloads of network adapters. The approach receives one or more requests from one or more virtual machines, wherein the one or more requests are directed to one or more network adapters. The approach determines whether a first network adapter of the one or more network adapters is saturated. Responsive to a determination that the first network adapter is saturated, the approach sends a first busy event to a first virtual machine of the one or more virtual machines.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kiran K. Anumalasetty, Venkata N. S. Anumula, Vinod Kumar Boddukuri, Sanket Rathi, Rajaboina Yadagiri
  • Patent number: 9996374
    Abstract: An update is deployed to a guest virtual machine of a hypervisor during runtime of the guest virtual machine. An executing thread of the guest virtual machine is identified and execution of the thread is redirected to a function to open a handle to a file, of the guest virtual machine, to which data of the update is to be written. The data is provided to a component of the guest virtual machine, and then execution of the thread is redirected to a function to write the data provided to the component to the file.
    Type: Grant
    Filed: June 16, 2015
    Date of Patent: June 12, 2018
    Assignee: ASSURED INFORMATION SECURITY, INC.
    Inventors: Michael Joseph Sieffert, Jonathan Einstoss, Stephen Raymond Pape, Adam T. Meily
  • Patent number: 9996375
    Abstract: A pre-configured hyper-converged computing device for supporting a virtualization infrastructure includes a first independent server node at a first location comprising a first server node unique identifier, a second independent server node at a second location comprising a second server node unique identifier. The first server node unique identifier correlates to the first location. The second server node unique identifier correlates to the second location such that an exact location of the first or second independent server node are determined within the pre-configured hyper-converged computing device.
    Type: Grant
    Filed: October 31, 2014
    Date of Patent: June 12, 2018
    Assignee: VMware, Inc.
    Inventors: Wit Riewrangboonya, Michael R. Macfaden, Dave Shanley
  • Patent number: 9996376
    Abstract: A virtual machine monitoring method and a system thereof are provided. The virtual machine monitoring method includes: detecting at least one hardware resource of an electronic device and storing corresponding hardware configuration data, detecting display information of the electronic device and storing corresponding display configuration data, connecting a server and receiving image data therefrom, establishing a virtual machine based on the image data, configuring the at least one hardware resource on the virtual machine based on the hardware configuration data, setting a display image on the virtual machine based on the display configuration data, and clearing the image data to end the virtual machine, so as to provide a user-friendly interface and achieve corporate data security.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: June 12, 2018
    Assignee: Wistron Corporation
    Inventors: Chih-Ming Chen, Horng-Song Wu
  • Patent number: 9996377
    Abstract: Embodiments relate to virtual machine (VM) migration via a mobile device. A method includes requesting, by a mobile device, a source computer to capture a state and memory contents of a VM executing on the source computer. The VM includes the state, the memory contents, and data. The state and memory contents of the VM are stored on the mobile device. Security information about a target computer is determined by the mobile device. A migration of the VM to the target computer is initiated by the mobile device. The initiating includes sending the stored state and memory contents of the VM from the mobile device to the target computer. An activation of the VM on the target computer is initiated and access is provided to at least a subset of the data of the VM. The subset is selected based on the security information.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Eli M. Dow, James P. Gilchrist, Steven K. Schmidt, Charles J. Stocker, IV
  • Patent number: 9996378
    Abstract: A technique for failure monitoring and recovery of a first application executing on a first virtual machine includes storing machine state information during execution of the first virtual machine at predetermined checkpoints. An error message that includes an application error state at a failure point of the first application is received, by a hypervisor, from the first application. The first virtual machine is stopped in response to the error message. The hypervisor creates a second virtual machine and a second application from the stored machine state information that are copies of the first virtual machine and the first application. The second virtual machine and the second application are configured to execute from a checkpoint preceding the failure point. In response to receipt of a failure interrupt by the second application, one or more recovery processes are initiated in an attempt to avert the failure point.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventor: Geraint North
  • Patent number: 9996379
    Abstract: A method for registering a plurality of callbacks. The method may include receiving at least one callback function in a virtual machine, which includes a plurality of callback registration information. The method may include registering each at least one received callback function in a virtual machine tool interface within the virtual machine to a list of callback functions for an event based on the plurality of callback registration information. The method may include monitoring the virtual machine for an occurrence of the event. The method may include determining the event has occurred. The method may also include generating a local frame for each at least one registered callback function within the list of callback functions for the determined event. The method may include executing each at least one registered callback function based on each generated local frame associated with each at least one registered callback function.
    Type: Grant
    Filed: January 25, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joshua H. Armitage, Michael P. Clarke, John A. W. Kaputin, King-Yan Kwan, Andrew Wright
  • Patent number: 9996380
    Abstract: A task definition is received. The task definition indicates at least a location from which one or more software image can be obtained and information usable to determine an amount of resources to allocate to one or more software containers for the one or more software image. A set of virtual machine instances in which to launch the one or more software containers is determined, the one or more software image is obtained from the location included in the task definition and is launched as the one or more of software containers within the set of virtual machine instances.
    Type: Grant
    Filed: January 26, 2016
    Date of Patent: June 12, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Deepak Singh, Anthony Joseph Suarez, William Andrew Thurston, Anirudh Balachandra Aithal, Daniel Robert Gerdesmeier, Euan Skyler Kemp, Kiran Kumar Meduri, Muhammad Umer Azad
  • Patent number: 9996381
    Abstract: Techniques for configuring virtual machine instances are described herein. A virtual machine instance is instantiated and the virtual machine instance is monitored to receive notifications of configuration events associated with that virtual machine instance. Each configuration event, which specifies configuration changes to the virtual machine instance, includes a set of metadata associated with the configuration event. The metadata is extracted from the configuration event and the configuration changes are applied to the virtual machine instance. A new virtual machine image is then produced from the virtual machine instance and the extracted metadata is associated with the new virtual machine image.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: June 12, 2018
    Assignee: Amazon Technologies, Inc.
    Inventors: Gurinder Raju, Karmveer Veer Singh, Abhinav Shrivastava, Sheshadri Supreeth Koushik, Deepak Suryanarayanan
  • Patent number: 9996382
    Abstract: A method, system and computer program product are provided for implementing dynamic cost calculation for a Single Root Input/Output Virtualization (SRIOV) virtual function (VF) in cloud environments. A management function periodically queries the SRIOV adapter for activity statistics for each assigned virtual function. The management function builds a usage heuristic based on the resource usage statistics. The management function calculates dynamic cost for the SRIOV VF based on the resource usage statistics. Calculated dynamic costs for the SRIOV VF are provided to a virtual function user and users are enabled to scale their VF resources. The VF resources are selectively scaled-up and scaled-down responsive to user input based upon VF resource usage.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Manu Anand, Charles S. Graham, Timothy J. Schimke
  • Patent number: 9996383
    Abstract: Techniques for handling inheritance of disk state when forking virtual machines (VMs) are provided. In one embodiment, a computer system can receive a request to fork a child VM from a parent VM. In response, the computer system can take a disk snapshot of the parent VM, where the disk snapshot results in a child disk for the child VM, where the child disk is a delta disk that points to a parent disk of the parent VM, and where the parent disk serves as the parent VM's current running point. The computer system can then determine whether the parent disk is a delta disk. If so, the computer system can copy the content of the parent disk to the child disk, traverse a disk hierarchy associated with the parent disk to identify a base disk above the parent disk in the hierarchy, and cause the child disk to point directly to the base disk.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: June 12, 2018
    Assignee: VMWARE, INC.
    Inventors: Gabriel Tarasuk-Levin, Jayanth Gummaraju, Hui Li, Li Zheng
  • Patent number: 9996384
    Abstract: Described is a technology by which a virtual machine may be safely migrated to a computer system with a different platform. Compatibility of the virtual machine may be checked by comparing the virtual machine's capabilities against those of the new platform. To ensure compatibility, when created the virtual machine may have its capabilities limited by the lowest common capabilities of the different platforms available for migration. Computer systems may be grouped into migration pools based upon similar capabilities, and/or a virtual machine may be mapped to certain computer systems based upon capabilities needed by that virtual machine, such as corresponding to needed performance, fault tolerance and/or flexibility.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: June 12, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Robert Bradley Bennett, René A. Vega, Shuvabrata Ganguly, Matthew Douglas Hendel, Rajesh Natvarlal Davé, Lars Reuther, Tamás Gál, Yuan Zheng
  • Patent number: 9996385
    Abstract: Dynamically changing the aggressiveness of optimization of virtual machines on physical hosts allows more efficient and varied optimization. An aggressiveness policy mechanism periodically applies system conditions to the aggressiveness policies to create aggressiveness settings that are provided to an optimizer. The optimizer then uses the aggressiveness settings to dynamically adjust the aggressiveness of placement of virtual machines according to the aggressiveness settings and consistent with other optimization policies. The aggressiveness policy mechanism may allow a system administrator to create and/or select aggressiveness policies.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Joseph W. Cropper, Jennifer D. Mulsow, Taylor D. Peoples, Edward Shvartsman
  • Patent number: 9996386
    Abstract: Methods and apparatus relating to mid-thread pre-emption with software assisted context switch are described. In an embodiment, one or more threads executing on a Graphics Processing Unit (GPU) are stopped at an instruction level granularity in response to a request to pre-empt the one or more threads. The context data of the one or more threads is copied to memory in response to completion of the one or more threads at the instruction level granularity and/or one or more instructions. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Brian D. Rauchfuss, Naveen R. Matam, Michael K. Dwyer, Aditya Navale
  • Patent number: 9996387
    Abstract: A data stream processing unit (DPU) and methods for its use and programming are disclosed. A DPU includes a number of processing elements (PEs) arranged in a physical sequence. Each datum in the data stream visits each PE in sequence. Each PE has a memory circuit, data and metadata input and output channels, and a computing circuit. The metadata input represents a partial computational state that is associated with each datum as it passes through the DPU. Each computing circuit implements a finite state machine that operates on the data and metadata inputs as a function of its position in the sequence and a data context, producing an altered partial computational state that accompanies the datum. When the data context changes, the current state of the finite state machine is stored, and a new state is loaded. The processing elements may be collectively programmed to perform any desired computation.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: June 12, 2018
    Assignee: Lewis Rhodes Labs, Inc.
    Inventors: David Follett, Pamela L. Follett
  • Patent number: 9996388
    Abstract: The illustrative embodiments described herein provide systems and methods for managing the execution of processing jobs. In one embodiment, a method includes receiving a processing job associated with a set of processing job parameters. The processing job is sent from a user interfacing device associated with a user. The method also includes determining a processing job priority for the processing job using the set of processing job parameters, identifying a destination processing device capable of executing the processing job using the set of processing job parameters, and initiating execution of the processing job at the destination processing device to form processed data in response to determining to execute the processing job based on the processing job priority.
    Type: Grant
    Filed: March 28, 2017
    Date of Patent: June 12, 2018
    Assignee: Open Invention Network LLC
    Inventor: Margarita Khafizova
  • Patent number: 9996389
    Abstract: Embodiments presented herein provide techniques for optimizing parallel data flows of a batch processing job using a profile of the processing job. An application retrieves a job profile for a processing job. The processing job has a plurality of processing stages specified in an execution profile. The job profile includes statistical data for at least one of the processing stages obtained during prior executions of the job. The application modifies properties of the execution profile based on the job profile to optimize the execution of the job. The application executes the processing job with the modified execution profile.
    Type: Grant
    Filed: March 11, 2014
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian K. Caufield, Lawrence A. Greene, Eric A. Jacobson, Yong Li, Xiaoyan Pu
  • Patent number: 9996390
    Abstract: Exemplary embodiments provide a method for managing a transaction for a memory module in a computer system. The memory modules have latencies. A busyness level of the memory module for the transaction is determined. A projected response time for the transaction is predicted based on the busyness level. In some embodiments whether to perform a context switching for the transaction is determined based on the projected response time and context switching policies. The context switching may be performed based on this determination.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hongzhong Zheng, Suhas
  • Patent number: 9996391
    Abstract: A management device includes: a memory; and a processor coupled to the memory. The processor executes a process including: storing therein an assignment table including first assignment information indicating whether a job is assigned to the information processing devices and second assignment information indicating that a job is constantly assigned to virtual information processing devices arranged at ends of a connection relation of the information processing devices; searching regions in which idle information processing devices assigned with no job are arranged continuously, using the assignment table stored at the storing; specifying a region appropriate for assignment of a job as an assignment target among the regions searched by the searching; and assigning the job as the assignment target to the region specified by the specifying.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: June 12, 2018
    Assignee: FUJITSU LIMITED
    Inventor: Akitaka Iwata
  • Patent number: 9996392
    Abstract: In embodiments of an idle time service, it can be determined that processing on a device is in an idle state. An execution duration of applications that are scheduled to be executed by a processor of the device can then be extended to reduce power consumption by the device. In other embodiments, it can be determined that an application configured to execute on a device is a background application. The execution duration of the background application can then be extended to reduce power consumption by the device.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: June 12, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Patrick L. Stemen, Nicholas S. Judge, Tristan A. Brown, Dean L. DeWhitt
  • Patent number: 9996393
    Abstract: A method, program product, and system is provided for dynamic virtual processor management in a computer having a plurality of concurrent multi-threaded physical processors. A workload is assigned to a first virtual processor manager pool based on a virtual processor manager mode of the first virtual processor manager pool. A current utilization ratio and a response time ratio for the workload are calculated. The workload is dynamically moved to a second virtual processor manager pool based on either the current utilization ratio or the response time ratio exceeding a configurable threshold. The workload is dynamically moved between virtual processor manager pools to realize target performance metric requirements.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Dean J. Burdick, Bruce Mealey, Bret R. Olszewski, Basu Vaidyanathan
  • Patent number: 9996394
    Abstract: An application programming interface is provided that allows programmers to encapsulate snippets of executable code of a program into accelerator tasks. A graph is generated with a node corresponding to each of the accelerator tasks with edges that represent the data flow and data dependencies between the accelerator tasks. The generated graph is used by a scheduler to schedule the execution of the accelerator tasks across multiple accelerators. The application programming interface further provides an abstraction of the various memories of the accelerators called a datablock. The programmer can store and use data stored on the datablocks without knowing where on the accelerators the data is stored. The application programming interface can further schedule the execution of accelerator tasks to minimize the amount of data that is copied to and from the accelerators based on the datablocks and the generated graph.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: June 12, 2018
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Christopher J. Rossbach, Jonathan James Currey
  • Patent number: 9996395
    Abstract: A plan including several groups of tasks is constructed for performing maintenance on a plurality of interrelated machines. A maintenance task in a first group is caused to execute within a window of time allocated for the maintenance. A determination is made that an estimated amount of time needed to execute a second group of tasks from the several groups is more than the remaining time in the window. In response to such a determination, the execution of the second group of tasks is omitted. The execution of a post-requisite task of the first group is completed. A maintenance task in the second group is executed during a second window of time allocated for the maintenance.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bradford A. Fisher, James K. MacKenzie, Dominic O'Toole
  • Patent number: 9996396
    Abstract: Provided are a computer program product, system, and method for transferring a virtual machine from a first server to a second server. A first enhanced system translator executing on the first server includes a first virtual machine interface to interface with a first instance of the virtual machine on the first server and a first convert state component. A second enhanced system translator executing on the second server includes a second virtual machine interface to interface with a second instance of the virtual machine and a second convert state component. The first convert state component converts a state of the first instance of the virtual machine to a first instruction set architecture and the second convert state component converts the first instructions set architecture to a second instruction set architecture for use by the second instance of the virtual machine to run on the second server.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Paul Knowles, Adam James McNeeney, Henry Paul Nash
  • Patent number: 9996397
    Abstract: Apparatus, systems and methods aggregating electronic devices for sharing functionality to fulfill requested tasks, while also monitoring and controlling battery energy levels in these electronic devices to ensure sufficient battery power is available on the devices, individually or collectively, to fulfill a requested task. The electronic devices are positioned in proximity to a computing device for determining functionalities that may be shared amongst the various electronic devices to fulfill the requested task. These electronic devices are also provided in proximity to a charge distribution unit (CDU) for determining if each electronic device has enough battery power to complete all, or a portion, of the requested task. If any device needs charging, the CDU allocates and distributes battery power from one or more other device batteries and/or power outlet. The charging power is then transferred to the electronic device in need of charging to fulfill the requested task.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pasquale A. Catalano, Casimer M. DeCusatis, Rajaram B Krishnamurthy, Michael Onghena, Anuradha Rao
  • Patent number: 9996398
    Abstract: An application processor includes a first core and a second core. The first core is configured to implement a scheduler which monitors a workload of a task of the first core, and the first core is further configured to implement an idle checker which determines whether the second core is idle.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: June 12, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Gyeong Taek Lee, Seung Kyu Kim, Kyung Min Park, Jong Lae Park, Ji Eun Park
  • Patent number: 9996399
    Abstract: A system, method, computer program, and/or computer readable medium for providing hierarchical interception for applications within isolated environments. The computer readable medium includes computer-executable instructions for execution by a processing system. The computer-executable instructions may be for installing interceptors, configuring interceptors, preloading shared libraries, using trampoline functions, removal of interceptors, mapping between resources inside and outside the isolated environment, providing an interception database, loading the interception database, redirection of resources, and providing the hierarchy of interceptors.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: June 12, 2018
    Assignee: Open Invention Network LLC
    Inventor: Allan Havemose
  • Patent number: 9996400
    Abstract: In an asymmetric multi-CPU system on which a plurality of type of CPUs with different data processing performance and power consumption are mounted in groups for each type, a plurality of forms of combination of the types and numbers of CPUs are defined in such a way that the maximum numbers of the overall data processing and power consumption very by stages. Then, the system performs a control of allocation of the data processing to the CPU identified by the form selected from the definition information according to the data processing environment, in order to reduce unnecessary power consumption according to the data processing environment, such as data processing load, and to easily achieve the required data processing performance.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: June 12, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tetsuya Nakagawa
  • Patent number: 9996401
    Abstract: A task processing method and virtual machine are disclosed. The method includes selecting an idle resource for a task; creating a global variable snapshot for a global variable; executing the task, in private memory space in the selected idle resource; after the execution of the task is complete, acquiring a new global variable snapshot corresponding to the global variable, and acquiring an updated global variable according to a local global variable snapshot and the new global variable snapshot; and determining whether a synchronization variable of a to-be-executed task in a task synchronization waiting queue includes the current updated global variable, and if the synchronization variable of the to-be-executed task in the task synchronization waiting queue includes the current updated global variable, putting the task into a task execution waiting queue.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: June 12, 2018
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lin Gu, Zhiqiang Ma, Zhonghua Sheng, Liufei Wen
  • Patent number: 9996402
    Abstract: NUMA-aware reader-writer locks may leverage lock cohorting techniques and may support reader re-entrancy. They may implement a delayed sleep mechanism by which a thread that fails to acquire a lock spins briefly, hoping the lock will be released soon, before blocking on the lock (sleeping). The maximum spin time may be based on the time needed to put a thread to sleep and wake it up. If a lock holder is not executing on a processor, an acquiring thread may go to sleep without first spinning. Threads put in a sleep state may be placed on a turnstile sleep queue associated with the lock. When a writer thread that holds the lock exits a critical section protected by the lock, it may wake all sleeping reader threads and one sleeping writer thread. Reader threads may increment and decrement node-local reader counters upon arrival and departure, respectively.
    Type: Grant
    Filed: April 7, 2014
    Date of Patent: June 12, 2018
    Assignee: Oracle International Corporation
    Inventor: Rahul Yadav
  • Patent number: 9996403
    Abstract: A middleware machine environment can provide message queues for multinode applications. The transactional middleware machine environment includes a message control data structure on a message receiver and a heap data structure in a shared memory that is associated with the message receiver. The message sender operates to write a message directly into the heap data structure, and to maintain metadata associated with the message in the message control data structure. Furthermore, the message control data structure can be a ring structure with a head pointer and a tail pointer. Additionally, the message receiver resides on a server that is connected with a plurality of clients, with each of said clients keeping a private copy of the message control data structure. Also, the message receiver can support concurrent access to the message control data structure associated with the message receiver.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: June 12, 2018
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Richard Frank, Todd Little, Arun Kaimalettu, Leonard Tominna
  • Patent number: 9996404
    Abstract: A method and apparatus for message cache management for message queues is provided. A plurality of messages from a plurality of enqueuers are enqueued in a queue comprising one or more shards, each shard comprising one or more subshards. A message cache is maintained in memory. Enqueuing a message includes enqueuing the message in a current subshard of a particular shard, which includes storing the message in a cached subshard corresponding to the current subshard of the particular shard. For each dequeuer-shard pair, a dequeue rate is determined. Estimated access time data is generated that includes an earliest estimated access time for each of a plurality of subshards based on the dequeuer-shard pair dequeue rates. A set of subshards is determined for storing as cached subshards in the message cache based on the earliest estimated access times for the plurality of subshards.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: June 12, 2018
    Assignee: Oracle International Corporation
    Inventors: Mukesh Jaiswal, Shubha Bose, James W. Stamos, Alan R. Downing, Devendra Singh
  • Patent number: 9996405
    Abstract: A prognostics analysis software module is embedded in a programmable logic controller (PLC) software platform. During cycling of the PLC real-time operating program, data is read from sensors and written to a buffer only when the prognostics analysis software module is idle. The prognostics analysis software module is then activated by a system function block of the PLC software platform. Before determining any prognostic information, prediction models within the prognostics analysis software module are automatically trained using features extracted from the sensor data.
    Type: Grant
    Filed: April 12, 2013
    Date of Patent: June 12, 2018
    Assignee: Siemens Corporation
    Inventors: Linxia Liao, Ertan Eligul, Zachery Edmondson
  • Patent number: 9996406
    Abstract: To provide a machining program processing apparatus capable of preventing an increase in the program correction time or does not let the program correction time go to waste. A machining program processing apparatus includes: a grammar checking unit executing grammar check of a machining program; a transmission processing unit transmitting the machining program to an external device; and a deletion processing unit deleting the machining program, wherein, when a transmission request of the machining program including a grammar error is received, the transmission processing unit confirms whether the transmission is to be permitted or not.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: June 12, 2018
    Assignee: DMG MORI CO., LTD.
    Inventor: Masakazu Takayama
  • Patent number: 9996407
    Abstract: A system may include a processing unit executing program instructions (SW), a data acquisition (DAQ) hardware device for acquiring sample data and/or generating control signals, and host memory configured to store data samples and various data associated with the DAQ and processor operations. The DAQ device may push HW status information to host memory upon being triggered by predetermined events taking place in the DAQ device, e.g. timing events or interrupts, to avoid or reduce SW reads to the DAQ device. The DAQ device may update dedicated buffers in host memory with status data on any of these events. The status information pushed to memory may be read in a manner that allows detection of race conditions. Interrupts generated by the DAQ device may be similarly handled. Upon generating an interrupt, the DAQ device may gather information required to handle the interrupt, and push the information into system memory, along with information identifying the interrupt.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 12, 2018
    Assignee: National Instruments Corporation
    Inventors: Rafael Castro Scorsi, Hector M. Rubio, Gerardo Daniel Domene-Ramirez
  • Patent number: 9996408
    Abstract: A method and system for evaluating performance of software applications. Steps in a first software application within a first web site are mapped to respective similar-function steps in a second software application within a second web site. Measures of performance of: each mapped step in the first software application, the respective similar-function steps in the second software application, and other steps in the second application are determined. A measure of performance of the first software application is determined, based on the measures of performance of each mapped step in the first software application. A measure of performance of the second software application is determined, based on the measures of performance of the respective similar-function steps and the other steps in the second software application. Improved performance is obtained for the and/or first software application by utilizing the measure of performance of the first and/or second software application, respectively.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Stig A. Olsson, Terrence D. Smetanka, Geetha Vijayan
  • Patent number: 9996409
    Abstract: A big data processing system includes a workload trimming function that separates out from among a set of identified anomalies, those that are clearly outliers, rather than ones residing within clusters of anomalies as mapped within an anomalies distribution space. The outlier anomalies are not subjected to a computationally-intensive anomalies aggregating process and thus, processing resources are conserved.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: June 12, 2018
    Assignee: CA, Inc.
    Inventors: Ye Chen, Jin Zhang, Lan Xu, Chi Zhang, Yue Xiao
  • Patent number: 9996410
    Abstract: A non-transitory computer-readable recording medium having stored therein a program for causing a computer to execute a process for detecting a sign, the process includes obtaining message information output from one or a plurality of information processing devices; obtaining configuration information in the one or the plurality of information processing devices; storing the obtained message information and the obtained configuration information in a common format; and outputting predetermined message information and predetermined configuration information according to comparison of a predetermined pattern described in the common format and the message information and the configuration information stored in the common format.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: June 12, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Otsuka, Yukihiro Watanabe, Yasuhide Matsumoto
  • Patent number: 9996411
    Abstract: Embodiments of the present invention provide methods, program products, and systems for improving DIMM level memory mirroring. Embodiments of the present invention can be used to configure a first memory module device of a pair memory module devices to receive a set of read and write operations and configure a second memory module device of the pair of memory module devices to receive only write operations of the set of read and write operations. Embodiments of the present invention can, responsive to detecting a failure, reconfiguring the first and the second memory module device to set the first memory module device to receive only write operations of the set of read and write operations and the second memory module device to receive read and write operations of the set of read and write operations.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Diyanesh B. Chinnakkonda Vidyapoornachary, Saravanan Sethuraman
  • Patent number: 9996412
    Abstract: Memory systems may include a memory storage, and a controller suitable for, receiving a plurality of codewords, each codeword including a user bits portion divided into a number of sub-trunks, determining whether a codeword in the plurality of codewords is decidable, identifying a location of an erroneous sub-trunk in a codeword determined to be undecodable, and recovering the erroneous sub-trunk by summing sub-trunks of other codewords that have a location in their respective codewords that is the same as the location of the erroneous sub-trunk.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: June 12, 2018
    Assignee: SK Hynix Inc.
    Inventors: Fan Zhang, June Lee, Yu Cai
  • Patent number: 9996413
    Abstract: An improved system is disclosed for ensuring the integrity of data stored on a dispersed data storage network. Checksums are used to ensure integrity of both data segments and data slices. Checksums appended to data slices are checked by receiving slice servers to ensure that no errors occurred during transmission. Slice servers also periodically recalculate checksums for stored data slices to ensure that data slices have not been corrupted during storage. Checksums appended to data segments are checked when data segments are read from the storage network.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: Greg Dhuse, Vance Thornton, Jason Resch, Ilya Volvovski, Dusty Hendrickson, John Quigley
  • Patent number: 9996414
    Abstract: An aspect includes a method for auto-disabling dynamic random access memory (DRAM) error checking based on a threshold. A method includes receiving data at a DRAM from a memory controller and executing error checking logic based on the data. The error checking logic detects an error condition in the data and it is determined, at the DRAM, whether detecting the error condition in the data causes an error threshold to be reached. The error checking logic is disabled at the DRAM in response to determining that detecting the error condition in the data causes the error the error threshold to be reached. The error condition is communicated to the memory controller in response to determining that detecting the error condition does not cause the error threshold to be reached.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: June 12, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edgar R. Cordero, Marc A. Gollub, Warren E. Maule, Lucas W. Mulkey, Anuwat Saetow
  • Patent number: 9996415
    Abstract: A data correcting method for a rewritable non-volatile memory module is provided. The method includes: if a first user data read from a first physical programming unit cannot be corrected by a corresponding first parity code, reading at least one group parity code of a first encoded group that the first physical programming unit belongs to into a buffer, sending the group parity code to a correcting circuit, and reading a user data from physical programming units belonging to the first encoded group into the buffer and sending the user data and the group parity code to the correcting circuit in batches to obtain a corrected first user data corresponding to the first user data.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: June 12, 2018
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Ming-Jen Liang, Kheng-Chong Tan
  • Patent number: 9996416
    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: June 12, 2018
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Haitao Xia, Fan Zhang, Shu Li, Jun Xiao
  • Patent number: 9996417
    Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: June 12, 2018
    Assignee: Apple Inc.
    Inventors: Assaf Shappir, Etai Zaltsman, Guy Ben-Yehuda