Abstract: In a method for managing memory space in a network device two or more respective allocation requests from two or more processing cores among a plurality of processing cores sharing a memory space are received at a memory management device during a first single clock cycle of the memory management device, the two or more allocation requests requesting to allocate, to the two or more processing cores, respective buffers in the shared memory space. In response to receiving the two or more allocation requests, the memory management device allocates to the two or more processing cores, respective two or more buffers in the shared memory space. Additionally, the management device, during a second single clock cycle of the memory management device, transmits respective allocation responses to each of the two or more processing cores, wherein each allocation response includes an indication of a respective allocated buffer.

Abstract: The invention introduces a method for prefetching data, which contains at least the following steps: receiving a first read request and a second read request from a first LD/ST (Load/Store) queue and a second LD/ST queue, respectively, in parallel; obtaining a first cache-line number and a first offset from the first read request and a second cache-line number of a second offset from the second read request in parallel; obtaining a third cache-line number from a cache-line number register; obtaining a third offset from an offset register; determining whether an offset trend is formed according to the first to third cache-line numbers and the first to third offsets; and directing an L1 (Level-1) data cache to prefetch data of a cache line when the offset trend is formed.

Abstract: Presented herein are methods, non-transitory computer readable media, and devices for integrating a workload management scheme for a file system buffer cache with a global recycle queue infrastructure.

Abstract: Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the compressed data fit entirely within a primary block in the first memory region, both data and metadata are retrieved in a single memory access. Otherwise, overflow data is stored in an overflow block in the second memory region. The first and second memory regions may be located in the same row of a DRAM, for example, or in different regions of a DRAM and may be configured to enable standard DRAM components to be used. Compression and decompression logic circuits may be included in a memory controller.

Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Abstract: An apparatus for mapping user data into a selective underlying exposure address (SUE) space includes a memory that stores machine instructions and a processor that executes the instructions to combine first user data from a plurality of logically-addressed blocks to create a SUE page. The SUE page corresponds to a respective physical page of a respective physical block on each of a plurality of dies for which corresponding physical blocks of memory cells are jointly managed as a unit in a storage device. The processor further executes the instructions to store mapping information associating the first user data with the SUE page in a logical address space in the storage device.

Abstract: A multiple stage memory management unit (MMU) comprises a first MMU stage configured to translate an input virtual memory address to a corresponding intermediate memory address, the first MMU stage generating a set of two or more intermediate memory addresses including the corresponding intermediate memory address; and a second MMU stage configured to translate an intermediate memory address provided by the first MMU stage to a physical memory address, the second MMU stage providing, in response to an intermediate memory address received from the first MMU stage, a set of two or more physical memory addresses including the physical memory address corresponding to the intermediate memory address received from the first MMU stage; the first MMU stage being configured to provide to the second MMU stage for translation, intermediate memory addresses in the set other than any intermediate memory addresses in the set for which the second MMU stage will provide a physical memory address as a response to translation

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract: A process for caching data according to one embodiment includes maintaining a random data list and a sequential data list, and dynamically establishing a desired size of the sequential data list. Dynamically establishing the desired size of the sequential data list includes increasing the desired size of the sequential data list in response to at least one of: detecting a hit on a bottom of the sequential data list, and detecting a read miss on sequential tracks. Dynamically establishing the desired size of the sequential data list also includes decreasing the desired size of the sequential data list in response to detecting a hit on a bottom of the random data list.

Abstract: A method is disclosed that includes, generating, by a controller of a storage device, telemetry data associated with the storage device and stored in a memory device of the storage device. The method further includes determining, by the controller, a telemetry data loss warning condition indicating that a portion of the telemetry data is predicted to be overwritten in the memory device by more recent telemetry data. In response to determining the telemetry data loss warning condition, the controller transmits, to a host device, an asynchronous event notification indicating the telemetry data loss warning condition.

Abstract: A system and method for efficiently performing data allocation in a cache memory are described. A lookup is performed in a cache responsive to detecting an access request. If the targeted data is found in the cache and the targeted data is of a no allocate data type indicating the targeted data is not expected to be reused, then the targeted data is read from the cache without updating cache replacement policy information for the targeted data responsive to the access. If the lookup results in a miss, the targeted data is prevented from being allocated in the cache.

Abstract: The present disclosure is related to encryption of executables in computational memory. Computational memory can traverse an operating system page table in the computational memory for a page marked as executable. In response to finding a page marked as executable, the computational memory can determine whether the page marked as executable has been encrypted. In response to determining that the page marked as executable is not encrypted, the computational memory can generate a key for the page marked as executable. The computational memory can encrypt the page marked as executable using the key.

Abstract: A resilient device authentication system for use with one or more managed devices each including a physical unclonable function (PUF), comprises: one or more verification authorities (VA) each including a processor and a memory loaded with a complete verification set (CVS) that includes hardware part-specific data associated with the managed devices' PUFs and metadata, the processor configured to create a limited verification set (LVS) through one-way algorithmic transformation of hardware part-specific data together with metadata from the loaded CVS so as to create a LVS representing both metadata and hardware part-specific data adequate to redundantly verify all of the hardware parts associated with the LVS; and one or more provisioning entities (PE) each connectable to a VA and including a processor and a memory loaded with a LVS, and configured to select a subset of the LVS so as to create an application limited verification set (ALVS).

Abstract: A system, a method and a computer program product for managing memory access of an avionics control system having at least one control computer having at least one memory control device. The method includes assigning a memory access of at least one unique memory region of at least one memory unit to each of at least one application task or task set. A memory access of at least one application data update task is assigned to at least one subregion of one or more of the at least one unique memory region. At least one data parameter is written to the at least one subregion and the assigned memory access of the at least one application data update task de-activated.

Abstract: When an instruction to access a web server of an external device connected via a local interface is acquired from a user, access destination information for accessing the web server via the local interface is acquired. Based on the acquired access destination information, communication is performed with the web server of the external device via the local interface.

Abstract: System, methods and apparatus are described that facilitate a device to encode/decode data in a data communications interface coupled to a plurality of wires. The device determines a value of a sequence of data bits allocated to a frame, converts the value into a sequence of symbols associated with the frame, and transmits the sequence of symbols to a receiver. The device performs the converting by calculating base-N coefficients of a base-N number polynomial for the frame based on the value, where N is greater than 2, calculating base-2 coefficients of a base-2 number polynomial for each symbol according to a respective base-N coefficient corresponding to each symbol, determining changes of states of the plurality of wires for each symbol according to the base-2 coefficients respectively calculated for each symbol, and generating the sequence of symbols based on the changes of states of the plurality of wires for each symbol.

Abstract: A system that provides virtualized computing resources may include an enhanced PCIe endpoint device on which an emulation processor emulates PCIe compliant hardware in software. The endpoint device may include host interface circuitry that implements pointer registers and control and status registers for each of multiple transaction ring buffers instantiated in memory on the device. In response to receiving a transaction layer packet that includes a transaction, packet steering circuitry may push the transaction into one of the buffers, dependent on the transaction type, a routing identifier for an emulated device to which it is directed, its traffic class or other criteria. The transaction may be processed in software, emulating the hardware device. The host interface circuitry may generate response completion packets for configuration requests and non-posted transactions, and may return them according to PCIe ordering rules, regardless of the order in which they were processed on the endpoint device.

Abstract: A memory-control integrated circuit includes internal data conductors, steering circuitry and distinct first and second data interfaces, the first data interface having twice as many input/output (I/O) transceivers as the second data interface. In a first memory system configuration in which only the first data interface is coupled to a memory module, the steering circuitry couples all the internal data conductors exclusively to the I/O transceivers of the first data interface. In a second memory system configuration in which the first and second data interfaces are coupled to respective memory modules, the steering circuitry couples a first half of the internal data conductors exclusively to the I/O transceivers of the second data interface while a second half of the internal data conductors remains exclusively coupled to half the I/O transceivers of the first data interface.

Abstract: A storage device may be configured to adjust a frequency of a clock signal. The clock signal may be associated with a data transfer rate of data to be communicated between a controller and a memory of the storage device. In some implementations, the frequency maybe adjusted responsive to at least one of a supply voltage provided to the storage device, a temperature of the storage device, or a physical characteristic of the storage device.

Abstract: An apparatus having a fabric interconnect that supports multiple topologies and method for using the same are disclosed. In one embodiment, the apparatus comprises mode memory to store information indicative of one of the plurality of modes; and a first fabric operable in a plurality of modes, where the fabric comprises logic coupled to the mode memory to control processing of read and write requests to memory received by the first fabric according to the mode identified by the information indicative.

Abstract: A method for enabling 8-bit data word access over a protocol limited to 16-bit data word access is provided. Data may be encapsulated within the lowest 19 bits of a 20-bit number. If it is ascertained that an 8-bit data word is to be used in a system supporting only 16-bit data word access, a byte-enable indicator may be provided within a most significant bit of the 20-bit number while also allocating an 8-bit data region for transfer of the 8-bit data word. The 20-bit number may then be transcoded into a 12-digit ternary number, wherein a residual numerical region is defined as a number space by which a first numerical region defined for the 12-digit ternary number exceeds a second numerical region defined by the lowest 19 bits of the 20-bit number.

Abstract: The invention relates to a memory aggregation device for storing a set of input data streams and retrieving data to a set of output data streams, the memory aggregation device comprising: a set of first-in first-out (FIFO) memories each comprising an input and an output; an input interconnector configured to interconnect each one of the set of input data streams to each input of the set of FIFO memories according to an input interconnection matrix; an output interconnector configured to interconnect each output of the set of FIFO memories to each one of the set of output data streams according to an output interconnection matrix; an input selector; an output selector; and a memory controller.

Abstract: A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect.

Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.

Abstract: The invention relates to a method and a coupling device for dynamically allocating USB endpoints of a USB interface, which can be accessed using at least two applications, comprising: a USB interface that has at least two ports, each of which comprises at least one USB endpoint; and a control device for dynamically allocating the USB endpoints. The control device is designed so as to preconfigure each USB endpoint which is required for the at least two applications by means of an initialization process, and thus the control device can switch the allocation of the endpoints according to the access using at least one of the applications without the USB endpoints affected by the switch having to be deactivated.

Abstract: A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

Abstract: Systems and methods for asynchronous mapping of a hot-plugged I/O device associated with a virtual machine. An example method comprises: executing, by a first processing thread running on a host computer system, a virtual processor associated with a virtual machine; initializing, by a second processing thread, a table entry of a guest input/output (I/O) table associated with the virtual machine, wherein the table entry maps a device identifier of an I/O device to a memory buffer associated with the I/O device; pinning the memory buffer associated with the I/O device; responsive to receiving, by a hypervisor running on the host computer system, a completion signal from the second processing thread, notifying the virtual machine of the I/O device being hot-plugged.

Abstract: An advanced PCI Express board assembly is intended for efficiently placing more electronic components or modules having a large height (up to 8.57 mm) in comparison with traditional PCI Express add-in boards. This assembly comprises two PCBs connected together. The first one has the minimum possible sizes. This PCB includes a PCI Express male edge connector and is intended to be plugged in to motherboard female PCI Express connector. The second PCB is parallel to first one and is located in the middle of the space (slot) defined for one add-in PCI Express board. This position makes possible to place high electronic components or modules on the both sides (top and bottom) of the second PCB.

Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

Abstract: A method for processing graphics is provided. The method includes: establishing streams corresponding to graphic layers drawn by at least one application; adding a one-shot signal to the end of the last stream of the streams; packaging the streams with the one-shot signal to form a packet; and transmitting the packet to a display interface unit (DIU).

Abstract: Communication apparatus includes a host interface for connection, via a host bus, to a host processor and a host memory, which is mapped to an address space of the host bus, and a network interface, configured to transmit and receive packets over a network. A local memory is configured to hold data in a memory space that is not mapped to the address space of the host bus. Packet processing circuitry, which is connected between the host interface and the network interface and is connected to the local memory, is configured to receive from the network interface a packet carrying a remote direct memory access (RDMA) request that is directed to an address in the local memory, and to service the RDMA request by accessing the data in the local memory.

Abstract: A processor comprises a plurality of processor units arranged to operate concurrently and in cooperation with one another, and control logic configured to direct the operation of the processor units. At least a given one of the processor units comprises a memory, an arithmetic engine and a switch fabric. The switch fabric provides controllable connectivity between the memory, the arithmetic engine and input and output ports of the given processor unit, and has control inputs driven by corresponding outputs of the control logic. In an illustrative embodiment, the processor units may be configured to perform computations associated with a key equation solver in a Reed-Solomon (RS) decoder or other type of forward error correction (FEC) decoder.

Abstract: This present invention provides a fast data transfer for a concurrent transfer of multiple ROI areas between an internal memory array and a single memory where each PE can specify the parameter set for the area to be transferred independently from the other PE. For example, for a read transfer, the requests are generated in a way that first the first element of each ROI area is requested from the single memory for each PE before the following elements of each ROI area are requested. After the first element from each ROI area has been received from the single memory in a control processor and has been transferred from the control processor over a bus system to the internal memory array, all elements are in parallel stored to the internal memory array. Then, the second element of each ROI area is requested from the single memory for each PE. The transfer finishes after all elements of each ROI area are transferred to their assigned PEs.

Abstract: A content validation module receives an electronic media item in a first format. The content validation module may determine whether the electronic media item will contain errors when the electronic media item is converted to a second format. The content validation module may also obtain an error metric for the electronic media item and may refrain from converting the electronic media item to the second format if the error metric exceeds an error threshold.

Abstract: Computerized techniques can be used for algorithmically determining the composition of elements in a functional system represented in n-dimensional space using a logical data model.

Abstract: A method for processing an audio signal, including: sound is converted to an analog audio input signal and converted into a digital audio signal; a windowed time domain signal is obtained and then a twiddled signal is obtained; the twiddled signal is pre-rotated and then an FFT is performed; an in-place fixed rotate compensation is performed on the FFT signal and then an post-rotated is performed; a quantized signal is obtained and then wrote into a bitstream for transmitting or storing.

Abstract: A passage sentiment classifier that can be used to assign a score that indicates the polarity and magnitude of sentiment expressed by a piece of text using information about similar passages. A passage of text may be a few words, a sentence, a paragraph or an entire document. The invention described classifies automatically passages by first looking up the most similarly classified passage in a storage system, which contains passages that have been classified manually by a human.

Abstract: A method for managing a display of an electronic document (ED) on a display screen includes obtaining the ED specifying a plurality of text and a first graphical element; identifying a starting reference and an ending reference to the first graphical element within the plurality of text; displaying a portion of a segment of the plurality of text in a first region of the display screen, the segment being located between the starting reference and the ending reference; displaying, while displaying the portion of the segment, the first graphical element within a second region of the display screen, wherein the second region is adjacent to the first region on the display screen; removing the segment from the first region; and removing the first graphical element from the display screen in response to removing the segment such that the first region expands into the second region.

Abstract: A method for identifying a font displayed within an electronic document. In one embodiment, the method includes a computer processor identifying a string of two or more characters that correspond to a custom ligature within an electronic document, wherein the custom ligature is associated with at least one character of the electronic document. The method further includes accessing a font library associated with the electronic document. The method further includes identifying a font file within the font library that corresponds to the at least one character of the electronic document that is associated with the custom ligature. The method further includes identifying a glyph within the identified font file that corresponds to the custom ligature. The method further includes substituting the identified glyph into the electronic document to replace at least the custom ligature. The method further includes displaying the substituted glyph within the electronic document.

Abstract: For dynamically changing a rendering of content, the content including a textual character is received at a mobile device. An encoding of the textual character uses a first code point according to a character encoding standard. The mobile device's presence at a geographical location is detected. The mobile device is associated with a user. A variant selection rule is selected at the device. The variant selection rule specifies a location based condition to select a variant corresponding to the textual character. A variant is selected at the device according to the variant selection rule, a variant mapping corresponding to the first code point. The variant mapping includes the variant. The encoding of the textual character is replaced at the device with an encoding of the variant in the rendering of the content.

Abstract: To provide an input assistance device, an input assistance method and a storage medium which can present a character string to be suggested to a user in consideration of a probability of being inputted first in a character string. An input assistance device is for assisting a user to input a character string, the device includes: a character string determining unit that determines a character string to be suggested relating to the inputted kana character string, in the case that a user inputs a kana character string by use of index structure, the index structure recording therein a word together with its kana-reading and the index structure indicating whether or not it is probable that the word is inputted first at a time of inputting a character string; and a suggested candidate presenting unit that presents the character string to be suggested, which is determined, as a suggested candidate.

Abstract: A method includes, but is not limited to any combination of: determining a plurality of third-party content elements based in part on information associated with a request for third-party content. The request for third-party content may be received from a web browser displaying a first webpage to a user. A first element from the plurality of determined third-party content elements is transmitted to the web browser. Upon receiving from the web browser a second request for third-party content including user interaction data with the first element, data associated with the determined plurality of third-party content elements is updated based at least in part on the user interaction data. A second third-party element from the plurality of updated third-party content elements is transmitted to the web browser.

Abstract: An automatic speech recognizer is used to produce a structured document representing the contents of human speech. A best practice is applied to the structured document to produce a conclusion, such as a conclusion that required information is missing from the structured document. Content is inserted into the structured document based on the conclusion, thereby producing a modified document. The inserted content may be obtained by prompting a human user for the content and receiving input representing the content from the human user.

Abstract: Website structure creation. A site navigation structure sketch is created by a free-form drawing using a drawing tool being executed on a computing device. The site navigation structure sketch is stored in pixel form, and processed by transforming the site navigation structure sketch by vectorizing the sketch into a predefined structured representation. A site navigation structure is created based on the predefined structured representation, and the site navigation structure is integrated into a web portal site structure.

Abstract: The invention discloses a device for a browser to process a page element comprising: at least one DOM object processor disposed at the browser side, each DOM object processor being configured to store a customized processing of a specific DOM object; a page parser configured to load an obtained page at the browser side, parse page elements of the obtained page, and convert each page element into a DOM object; a DOM processor coupled to the page parser and the at least one DOM object processor, and configured to invoke the at least one DOM object processor to perform a customized processing on at least one of converted DOM objects. By employing the invention, a personalized customization can be performed to a page according to the user needs. The invention further discloses a corresponding method.

Abstract: In an approach for selecting a version of a webpage to present to a user, a processor receives a request to access a webpage from a device, wherein the webpage includes a plurality of versions of the webpage. A processor receives information about the device. A processor determines a version of the webpage to present, based on the information about the device and a predefined goal associated with the webpage. A processor causes the version of the webpage to be presented.

Abstract: Disclosed are various examples for generating, storing, and loading references separate from a file. A request can be received to generate a reference for a file. A data object can be generated corresponding to the reference. The data object can include characteristics of the file proximate to an area in the file associated with the reference. The data object can be stored in a data store associated with the file. The file and reference can be loaded and rendered. The position of the reference within the file can be determined based on a stored data object.

Abstract: A system is provided in which access to documents and collaboration across varied platforms and feature versions is supported. A conversion and merge services is described that enables a client device to display documents irrespective of the original file format and re-integrate into the original document the modifications of the displayed document. The displayed document (as a whole or in parts) can be imported and converted to the file format of the original document before the changes are compared and merged into the original document. A set of application programming interfaces are also provided that perform certain tasks, such as highlight, comment, or format.

Abstract: Provided is an image processing device capable of displaying an annotation in an appropriate position. An image obtaining unit obtains an image. An annotation target information obtaining unit obtains annotation target information for indicating an annotation target to which to add an annotation, the annotation target being including in the image. An annotation information obtaining unit obtains annotation information indicating an annotation. A display position determination unit determines a display position of the annotation based on the position or the area of the annotation target. A data output unit outputs data on the image with the annotation displayed in the display position determined by the display position determination unit.

Abstract: One embodiment provides a method, including: accessing, using a processor, a form comprising at least one fillable field; receiving, from an audio input device, audio input from a user; identifying, using a processor, a fillable field associated with the audio input; and providing input, based on the audio input, to the fillable field associated with the audio input. Other aspects are described and claimed.