Patents Issued in June 12, 2018
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Patent number: 9996318Abstract: A FIFO memory having a modifiable memory region; the FIFO memory being configured as a linear memory and as a circular buffer; the FIFO memory having a state machine that contains a new base value and a new top value for definition of a memory region allocated in the future, the lower boundary of which region is defined by the new base value and the upper boundary of which is defined by the new top value, and the state machine is configured in such a way that in a read mode and/or a write mode of the FIFO memory, the allocated memory region of the FIFO memory is modifiable by shifting the base pointer to the new base value, and/or by shifting the top pointer to the new top value.Type: GrantFiled: May 18, 2016Date of Patent: June 12, 2018Assignee: ROBERT BOSCH GMBHInventors: Timo Giesselmann, Konstantin Buck, Rainer Dorsch
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Patent number: 9996319Abstract: An example processor includes a register and an ADD low functional unit. The register stores first, second, and third floating point (FP) values. The ADD low functional unit receives a request to perform an ADD low operation and, responsive to the request: adds the first FP value with the second FP value to obtain a first sum value; rounds the first sum value to generate an ADD value; adds the first FP value with the second FP value to obtain a second sum value; subtracts the ADD value from the second sum value to generate a difference value; normalizes the difference value to obtain a normalized difference value; rounds the normalized difference value to generate an ADD low value; and sends the ADD low value to an application.Type: GrantFiled: December 23, 2015Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Cristina S. Anderson, Marius A. Cornea-Hasegan, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Nikita Astafev, Mark J. Charney, Milind B. Girkar, Amit Gradstein, Simon Rubanovich, Zeev Sperber
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Patent number: 9996320Abstract: An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.Type: GrantFiled: December 23, 2015Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Cristina S. Anderson, Marius A. Cornea-Hasegan, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Nikita Astafev, Mark J. Charney, Milind B. Girkar, Amit Gradstein, Simon Rubanovich, Zeev Sperber
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Patent number: 9996321Abstract: Customizations, made at various levels in the customization channel, are saved as separate sets of customization deltas that are applied to a base computing system in order to generate a given solution. In a multi-tenant environment, groups of tenants access different solutions or customization deltas. The tenants are automatically grouped, based upon the solution or customization deltas that they access, and the deltas for those customizations are applied to the base system at runtime, for each group.Type: GrantFiled: June 23, 2015Date of Patent: June 12, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Morten Jensen, Thomas Hejlsberg, Michael Steven Hammond, Christopher Michael Rudolph, Kevin Martin Racer
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Patent number: 9996322Abstract: A system and method for facilitating automatically adjusting a user interface display screen or portion thereof. An example method includes determining context information associated with data, wherein the data is maintained in accordance with a data model; generating a signal when the context information changes; and employing the signal to automatically configure one or more characteristics of a user interface architecture, resulting in an adjusted user interface architecture. The context information may include information specifying one or more attributes relating to the data model. Generating may further include analyzing the one or more attributes to determine a modification to be made to the user interface architecture and then rendering a user interface display screen based on a modified user interface architecture.Type: GrantFiled: December 20, 2013Date of Patent: June 12, 2018Assignee: Oracle International CorporationInventors: Blake Sullivan, Edward Farrell, Jing Wu, Venkata Guddanti, Min Lu, Hongbing Wang, Michael Elges, Michael William McGrath, Gangadhar Konduri
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Patent number: 9996323Abstract: Execution of code in a multitenant runtime environment. A request to execute code corresponding to a tenant identifier (ID) is received in a multitenant environment. The multitenant database stores data for multiple client entities each identified by a tenant ID having one of one or more users associated with the tenant ID. Users of each of multiple client entities can only access data identified by a tenant ID associated with the respective client entity. The multitenant database is a hosted database provided by an entity separate from the client entities, and provides on-demand database service to the client entities. Source code corresponding to the code to be executed is retrieved from a multitenant database. The retrieved source code is compiled. The compiled code is executed in the multitenant runtime environment. The memory used by the compiled code is freed in response to completion of the execution of the compiled code.Type: GrantFiled: February 9, 2015Date of Patent: June 12, 2018Assignee: salesforce.com, inc.Inventors: Gregory D. Fee, William J. Gallagher
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Patent number: 9996324Abstract: Dataflow analysis is provided by monitoring a first and a second computing device to detect an initiation of an application on one or more of these computing devices. In response to detecting the initiation of the application on the first computing device, a first instrumentation procedure is applied to a first randomly selected portion of the application to produce a recorded dataflow for the first randomly selected portion. In response to detecting the initiation of the application on the second computing device, a second instrumentation procedure is applied to a second randomly selected portion of the application to produce a recorded dataflow for the second randomly selected portion. An integrated dataflow solution is assembled for the application from the recorded dataflow for the first randomly selected portion and the recorded dataflow for the second randomly selected portion.Type: GrantFiled: January 17, 2017Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Pietro Ferrara, Marco Pistoia, Omer Tripp
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Patent number: 9996325Abstract: In one example, a device includes one or more processors configured to determine a set of optimization pass configuration data for code of a software program to be compiled, wherein the optimization pass configuration data defines a sequence of optimization passes for the software program during compilation, and execute the sequence of optimization passes on code for the software program based on the set of optimization pass configuration data.Type: GrantFiled: March 6, 2013Date of Patent: June 12, 2018Assignee: QUALCOMM IncorporatedInventors: Chu-Cheow Lim, David Samuel Brackman
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Patent number: 9996326Abstract: An application that includes intrinsics defined in one architecture is to execute without change on a different architecture. Program code that depends on vector element ordering is obtained, and that program code is part of an application including one or more intrinsics. The one or more intrinsics are mapped from a first system architecture for which the application was written to a second system architecture. One or more operations of the program code are then converted from a first data layout to a second data layout. The application, including the mapped intrinsics and the converted data layout, is to be executed on a processor of the different architecture.Type: GrantFiled: August 11, 2015Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Ronald I. McIntosh
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Patent number: 9996327Abstract: Method, program and system for code optimization. A sign assignment instruction with identically sized packed decimal format input and output operands is detected where the sign assignment instruction assigns a value of zero to a packed decimal data value input operand having a value of negative zero. If the input operand to the sign assignment instruction does not result from an add or subtract operation, or the value of the input operand is not greater than a value prior to that operation, the possibility that the value of the input operand of the sign assignment instruction is negative zero is checked when the input operand and the output operand have identical addresses. An instruction is generated and inserted for executing the sign assignment instruction only when there is the possibility that the operand value is negative zero.Type: GrantFiled: November 9, 2015Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventor: Motohiro Kawahito
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Patent number: 9996328Abstract: Methods and systems for compiling codes from programming languages into programming languages are disclosed. An example method may include acquiring a first code written in a first language. The method allows generating, based on the first code, a first deterministic finite state machine (DFSM). The method includes optimizing the first DFSM to obtain a second DFSM. The method includes generating, based on the second DFSM, a second code. The second code can be written in a second language. Generating the first DFSM includes parsing the first code into a first abstract syntax tree (AST), translating the first AST into a first non-deterministic finite state machine (NFSM), and converting the first NFSM into the first DFSM. Generating the second code includes translating the second DFSM into a second NFSM, translating the second NFSM into a second AST, and recompiling the second AST into a second code.Type: GrantFiled: June 22, 2017Date of Patent: June 12, 2018Assignee: Archeo Futurus, Inc.Inventor: Daniel Joseph Bentley Kluss
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Patent number: 9996329Abstract: Various systems and methods for translating atomic read-modify-write accesses are described herein. In one example, a method includes determining that a machine instruction of a first language specifies an atomic read-modify-write access. The method includes generating machine instructions of the second language to perform an atomic access for the address if the address is aligned. The method includes generating machine instructions of a second language to acquire a global lock if the address is unaligned. Additionally, the method includes generating machine instructions of the second language to perform a non-atomic access for the address if the address is unaligned. Also, the method includes generating machine instructions of the second language to release the global lock if the address is unaligned.Type: GrantFiled: February 16, 2016Date of Patent: June 12, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Clarence Dang, Youssef Barakat, Arun Kishan
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Patent number: 9996330Abstract: A system, a method, and a computer program product for deploying objects are disclosed. A file containing a plurality of artifacts for deploying during runtime of an application is defined. At least one dependency for at least one artifact in the plurality of artifacts is determined based on the defined file. A database object for implementation during runtime of the application is created based on the determined dependency. At least one change to the database object during runtime of the application is implemented. The artifact is deployed during runtime of the application based on the implemented change to the database object.Type: GrantFiled: November 23, 2015Date of Patent: June 12, 2018Assignee: SAP SEInventors: Jonathan Bregler, Alexander Bunte, Arne Harren, Andreas Kellner, Daniel Kuntze, Vladislav Leonkev, Simon Lueders, Volker Sauermann, Michael Schnaubelt, Le-Huan Stefan Tran, Michael Wintergerst, Cornelia Kinder, Christopher Schildt
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Patent number: 9996331Abstract: An example method for managing application deployment in a cloud environment may maintain a state machine. The state machine may include a plurality of application states, a plurality of state operations, and relationships among the plurality of application states and the plurality of state operations. In response to a client request for performing a deployment operation on an application in the cloud environment, the method may retrieve a current state of the application in the cloud environment. In response to a determination that the deployment operation is allowed based on the state machine and the current state, the method may generate a deployment plan based on a blueprint associated with the application. The blueprint defines how to perform the deployment operation in the cloud environment.Type: GrantFiled: December 2, 2016Date of Patent: June 12, 2018Assignee: VMWARE, INC.Inventor: Ping Chen
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Patent number: 9996332Abstract: Timing parameters that influence an install time interval for installing a product on computing machines in a test environment in accordance with an installation configuration option are identified. A test value of the timing parameter and a test value of the install time are determined for each of the computing machines. The test values of the timing parameter and the install time determined for the sample computing machines are analyzed to determine an install time calculation expression for the installation configuration option. For installation in accordance with the installation configuration option in a normal operating environment, a current value of each of the timing parameters of the predetermined install time calculation expression for the installation configuration option. The install time interval in the normal operating environment is estimated based on the current value of the timing parameters and the install time calculation expression.Type: GrantFiled: September 23, 2015Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Rand K. Barthel, Yong Li, Eduardo N. Spring
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Patent number: 9996333Abstract: Provided are an apparatus for automating the installation and configuration of infrastructure. The apparatus comprises, an installation information management module which receives installation information of an open-source solution and manages the installation information in a tree structure based on a parent-child relationship, an environment setting management module which receives environment setting information of equipment and manages the environment setting information in a tree structure based on a parent-child relationship, and an installation package management module which generates an installation package and an installation automation script using the installation information and the environment setting information.Type: GrantFiled: March 4, 2016Date of Patent: June 12, 2018Assignee: SAMSUNG SDS CO., LTD.Inventors: Jae-Hong Kim, Jun-Youn Joo, Han-Hwee Cho, Young-Gi Kim, Ju-Seok Yun, Se-Joong Kim
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Patent number: 9996334Abstract: Examples of techniques for deploying a software library and a corresponding field programmable device binary are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: determining whether the software library and the field programmable device binary are available; determining whether to deploy the field programmable device binary to a field programmable device; determining whether to install the software library for use on a general purpose processor; responsive to determining to install the field programmable device binary to the field programmable device, deploying the field programmable device binary to the field programmable device; and responsive to determining to install the software library for use on the general purpose processor, installing the software library for use the general purpose processor.Type: GrantFiled: September 21, 2016Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Yuk L. Chan, Andrew P. Wack, Peter B. Yocom
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Patent number: 9996335Abstract: Particular embodiments described herein provide for a communication system that can be configured to receive a request for an update to a plurality of devices in a system, determine an amount of time to deploy the update, and que a deployment of the update for a least total wait time. In an example, the update is an operating system update.Type: GrantFiled: February 25, 2016Date of Patent: June 12, 2018Assignee: CISCO TECHNOLOGY, INC.Inventors: Rajiv Kumar Grover, Anthony Gordon Kent, Stephen Andrew Bechtold, Arvind Krishnan, Jason Varkey Cheruvatoor
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Patent number: 9996336Abstract: The present invention relates to an apparatus and a method for validating application deployment topology in a cloud environment. There is provided an apparatus for validating application deployment topology in a cloud environment comprising: a topology skeleton generator configured to generate, based on multiple VMs and script packages running on the VMs created by a user and required to deploy an application as well as running order of script packages and data dependency between script packages set by the user, a topology skeleton that comprises at least scripts of script packages of respective VMs and running order of the script packages; and a simulator configured to simulate a runtime environment in the cloud environment at the apparatus, thereby validating the running order and data dependency with respect to the topology skeleton, wherein the simulator is installed in the apparatus by using a simulator installation package retrieved from the cloud environment.Type: GrantFiled: July 14, 2016Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Geng Du, Chong Feng, Wei Feng Li, Xin Li, Qi Liu, Qiang Wang, Yue Wang, Chunxiao Zhang
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Patent number: 9996337Abstract: A power supply device is caused to execute a new program. An electronic apparatus that receives power from a power supply device in a non-contact manner includes: an intra-apparatus circuit that operates with power received via a power transmission path from the power supply device to the electronic apparatus; a program acquiring unit that acquires a program to be executed by the power supply device from outside, and stores the program; and an apparatus-side communicating unit that transmits the program to the power supply device via the power transmission path.Type: GrantFiled: June 27, 2017Date of Patent: June 12, 2018Assignee: NIKON CORPORATIONInventor: Goro Kano
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Patent number: 9996338Abstract: A method, system, and computer program product for handling synchronization of configuration changes between applications and their platforms. A computer implemented method synchronizes middleware configurations with application configurations using a reciprocating protocol. The protocol includes receiving a middleware state variable from a middleware component, then processing the middleware state variable to determine any application configuration state variables that depend on a value of the middleware state variable. The application (or agent) further processes the application configuration state variable to determine any affected middleware state variables and then sends the affected middleware state variable to the middleware component. The determinations can be performed using a forward mapper or reverse mapper, and the determinations can reciprocate repeatedly between applications and their middleware platforms until quiescence.Type: GrantFiled: May 9, 2016Date of Patent: June 12, 2018Inventors: Ivo Dujmovic, Satya Prakash Bandla, Ulhas Murlidhar Pinjarkar, Ramya Damodaran
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Patent number: 9996339Abstract: Disclosed herein are systems, methods, and software to enhance updates to digital content. In at least one implementation, an update agent identifies from a set of files at least a file that is scheduled to be updated from a present version of the file to a new version of the file as part of an update to the set of files. The update may include a set of delta files for updating the file from previous versions of the file to the new version and a complete file for updating the file to the new version.Type: GrantFiled: June 4, 2014Date of Patent: June 12, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Abhishek Agarwal, Anthony D. Krueger, Huy Q. Nguyen, Peter Cai, Jefferson B. Criddle
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Patent number: 9996340Abstract: A computer program product for identifying user managed software modules includes program instructions for: receiving a request for a directed load of a software module into memory, wherein the request includes an address; storing the software module at the address in the received request; adding a name and an address range of the stored software module to a data structure identifying software modules that have been loaded into memory via directed loads; receiving a query that includes an input module name or an input address range; and responsive to determining that the input module name or input address range of the received query is not stored in one or more data structures identifying one or more software modules that have been loaded into memory without directed loads, searching the data structure identifying software modules that have been loaded into memory via directed loads for the respective query.Type: GrantFiled: August 22, 2016Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Peter J. Relson, Ulrich Thiemann
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Patent number: 9996341Abstract: A method and apparatus to build a migration package. According to one embodiment of the invention, a plurality of programming elements are developed and stored in a configuration repository. The configuration repository also includes metadata used to describe each of the programming elements. Selected programming elements are placed in a set of one or more migration scripts to be stored in the migration package. The set of migration scripts may include a master configuration file and a driver file.Type: GrantFiled: July 5, 2013Date of Patent: June 12, 2018Assignee: Oracle International CorporationInventors: Yoram Tal, Larisa Yogolnitser, Ramzi Rabah, Patrick Gerald Wheeler, John Joseph Jakubik, Tuck Leong Chan
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Patent number: 9996342Abstract: In an approach to detection of potential merge errors when merging source code, a computer detects a source code merge process start. The computer compares at least one change made to a main stream of source code to a child stream. The computer determines whether one or more of the at least one change made to the main stream are not included in the child stream. Responsive to determining one or more of the at least one change made to the main stream are not included in the child stream, the computer determines the one or more of the at least one change made to the main stream that are not included in the child stream were removed from the child stream during a software development activity. The computer flags one or more files of the child stream corresponding to the one or more of the at least one change.Type: GrantFiled: January 22, 2016Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Howard Mak, Jacqueline A. Sheather
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Patent number: 9996343Abstract: A system and method that include collecting device version profiles from a plurality of device sources; classifying the device version profiles into a device profile repository; receiving a component version query request; querying the device profile repository according to the version query request; and responding to the query request with results of the query.Type: GrantFiled: May 12, 2016Date of Patent: June 12, 2018Assignee: Duo Security, Inc.Inventors: Jon Oberheide, Douglas Song
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Patent number: 9996344Abstract: Methods, systems, and computer program products for creating a customized runtime environment are described. One or more runtime environment capabilities are determined based on a profile. One or more runtime bundles corresponding to the one or more runtime environment capabilities are identified and the identified runtime bundles are assembled.Type: GrantFiled: July 28, 2016Date of Patent: June 12, 2018Assignee: SAP SEInventors: Ulf Fildebrandt, Madhav Bhargava, Sachit Aggarwal, Tarun Ramakrishna Elankath, Sridhar Jayaraman
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Patent number: 9996345Abstract: In an aspect, a pipelined execution resource can produce an intermediate result for use in an iterative approximation algorithm in an odd number of clock cycles. The pipelined execution resource executes SIMD requests by staggering commencement of execution of the requests from a SIMD instruction. When executing one or more operations for a SIMD iterative approximation algorithm, and an operation for another SIMD iterative approximation algorithm is ready to begin execution, control logic causes intermediate results completed by the pipelined execution resource to pass through a wait state, before being used in a subsequent computation. This wait state presents two open scheduling cycles in which both parts of the next SIMD instruction can begin execution. Although the wait state increases latency to complete an in-progress algorithm, a total throughput of execution on the pipeline increases.Type: GrantFiled: December 20, 2016Date of Patent: June 12, 2018Assignee: Imagination Technologies LimitedInventors: Kristie Veith, Leonard Rarick, Manouk Manoukian
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Patent number: 9996346Abstract: A new zSeries floating-point unit has a fused multiply-add dataflow capable of supporting two architectures and fused MULTIPLY and ADD and Multiply and SUBTRACT in both RRF and RXF formats for the fused functions. Both binary and hexadecimal floating-point instructions are supported for a total of 6 formats. The floating-point unit is capable of performing a multiply-add instruction for hexadecimal or binary every cycle with a latency of 5 cycles. This supports two architectures with two internal formats with their own biases. This has eliminated format conversion cycles and has optimized the width of the dataflow. The unit is optimized for both hexadecimal and binary floating-point architecture supporting a multiply-add/subtract per cycle.Type: GrantFiled: June 28, 2017Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Eric M. Schwarz, Ronald M. Smith, Sr.
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Patent number: 9996347Abstract: Methods and apparatuses relating to a vector instruction with a register operand with an elemental offset are described. In one embodiment, a hardware processor includes a decode unit to decode a vector instruction with a register operand with an elemental offset to access a first number of elements in a register specified by the register operand, wherein the first number is a total number of elements in the register minus the elemental offset, access a second number of elements in a next logical register, wherein the second number is the elemental offset, and combine the first number of elements and the second number of elements as a data vector, and an execution unit to execute the vector instruction on the data vector.Type: GrantFiled: December 24, 2014Date of Patent: June 12, 2018Assignee: INTEL CORPORATIONInventors: Victor Lee, Ugonna Echeruo, George Chrysos, Naveen Mellempudi
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Patent number: 9996348Abstract: A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle load operation. If so, control logic assigns a physical register identifier associated with a source operand of an older dependent store instruction to the destination operand of the load instruction. Additionally, the register rename unit marks the load instruction to prevent it from reading data associated with the source operand of the store instruction from memory. Due to the duplicate renaming, this data may be forwarded from a physical register file to instructions that are younger and dependent on the load instruction.Type: GrantFiled: June 14, 2012Date of Patent: June 12, 2018Assignee: Apple Inc.Inventors: Gerard R. Williams, III, John H. Mylius, Conrade Blasco-Allue
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Patent number: 9996349Abstract: Embodiments of the present invention provide systems and methods for clearing specified blocks of main storage. In one embodiment, an EADM start subchannel is executed. The instructions of the execution of the EADM start subchannel may include a SAP receiving an ADM request block, which specifies a main-storage-clearing operation command. The address and size of a block of main memory to be cleared by the SAP is specified in an MSB designated by the ADM request block.Type: GrantFiled: January 27, 2015Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Anthony F. Coneski, Beth A. Glendening, Dan F. Greiner, Peter G. Sutton, Scott B. Tuttle, Elpida Tzortzatos
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Patent number: 9996350Abstract: Methods and apparatuses relating to a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache. In one embodiment, a hardware processor includes a decoder to decode a prefetch instruction to prefetch a multidimensional block of elements from a multidimensional array into a cache, wherein at least one operand of the prefetch instruction is to indicate a system memory address of an element of the multidimensional block of elements, a stride of the multidimensional block of elements, and boundaries of the multidimensional block of elements, and an execution unit to execute the prefetch instruction to generate system memory addresses of the other elements of the multidimensional block of elements, and load the multidimensional block of elements into the cache from the system memory addresses.Type: GrantFiled: December 27, 2014Date of Patent: June 12, 2018Assignee: INTEL CORPORATIONInventors: Victor Lee, Mikhail Smelyanskiy, Alexander Heinecke
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Patent number: 9996351Abstract: A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such a computer processor includes, for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.Type: GrantFiled: May 26, 2016Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: David S. Levitan, Nicholas R. Orzol, Robert A. Philhower
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Patent number: 9996352Abstract: Systems, methods, and other embodiments associated with a processor that includes selectively enabled features are described. According to one embodiment, a processor includes a plurality of processing routines embedded within the processor that when executed cause the processor to implement corresponding processor features. The processor includes a processor engine configured to determine whether a processing routine of the plurality of processing routines is enabled based, at least in part, on a corresponding value in a control register. The processing engine is configured to selectively execute the processing routine based, at least in part, on whether the value indicates that the processing routine is enabled.Type: GrantFiled: February 24, 2016Date of Patent: June 12, 2018Assignee: MARVELL INTERNATIONAL LTD.Inventor: Kapil Jain
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Patent number: 9996353Abstract: An approach is provided in which a mapper control unit receives first dispatch information corresponding to a first instruction that identifies a first register and a first register type. The mapper control unit dynamically configures a first history buffer entry to support the first register type and, in turn, stores content from the first register into the first history buffer entry. The mapper control unit then receives second dispatch information corresponding to a second instruction that identifies a second register and a second register type, which is different than the first register type. The mapper control unit dynamically configures a second history buffer entry to support the second register type and, in turn, stores content from the second register into the second history buffer entry.Type: GrantFiled: February 26, 2015Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Michael J. Genden, Hung Q. Le, Dung Q. Nguyen, Kenneth L. Ward
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Patent number: 9996354Abstract: A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory. A corresponding method is also disclosed herein.Type: GrantFiled: January 9, 2015Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Lee E. Eisen, Lisa C. Heller, Michael T. Huffer, Eric M. Schwarz
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Patent number: 9996355Abstract: An instruction for parsing a buffer to be utilized within a data processing system including: an operation code field, the operation code field identifies the instruction; a control field, the control field controls operation of the instruction; and one or more general registers, wherein a first general register stores an argument address, a second general register stores a function code, a third general register stores length of an argument-character buffer, and the fourth of which contains the address of the function-code data structure.Type: GrantFiled: February 2, 2017Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John R. Ehrman, Dan F. Greiner
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Patent number: 9996356Abstract: Apparatus and method for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.Type: GrantFiled: December 26, 2015Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Vineeth Mekkat, Oleg Margulis, Jason M. Agron, Ethan Schuchman, Sebastian Winkel, Youfeng Wu, Gisle Dankel
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Patent number: 9996357Abstract: Systems, methods, and computer program products to perform an operation comprising creating, by a kernel, a temporary effective address associated with a virtual segment identifier (VSID), wherein the VSID is received by a processor in an asynchronous interrupt generated by a coherent accelerator in response to a page fault generated by the coherent accelerator in executing an instruction, accessing the temporary effective address by the processor to recreate the page fault on the processor, and resolving the page fault by an operating system executing on the processor.Type: GrantFiled: October 30, 2015Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Andre L. Albot, Vishal C. Aslot, Arnold Flores, Bruce Mealey, Mark D. Rogers
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Patent number: 9996358Abstract: A system and method of coupling a Branch Target Buffer (BTB) content of a BTB with an instruction cache content of an instruction cache. The method includes: tagging a plurality of target buffer entries that belong to branches within a same instruction block with a corresponding instruction block address and a branch bitmap to indicate individual branches in the block; coupling an overflow buffer with the BTB to accommodate further target buffer entries of instruction blocks, distinct from the plurality of target buffer entries, which have more branches than the bundle is configured to accommodate in the corresponding instruction's bundle in the BTB; and predicting the instructions or the instruction blocks that are likely to be fetched by the core in the future and fetch those instructions from the lower levels of the memory hierarchy proactively by means of a prefetcher.Type: GrantFiled: September 30, 2015Date of Patent: June 12, 2018Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNEInventors: Babak Falsafi, Ilknur Cansu Kaynak, Boris Robert Grot
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Patent number: 9996359Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.Type: GrantFiled: April 7, 2016Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Salma Ayub, Jeffrey C. Brownscheidle, Sundeep Chadha, Dung Q. Nguyen, Tu-An T. Nguyen, Salim A. Shah, Brian W. Thompto
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Patent number: 9996360Abstract: A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.Type: GrantFiled: August 9, 2016Date of Patent: June 12, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Dan F. Greiner, Christian Jacobi, Marcel Mitran, Timothy J. Slegel
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Patent number: 9996361Abstract: A processor comprises a first register to store a plurality of data items at a plurality of positions within the first register, a second register, and an execution unit, operatively coupled to the first register and the second register, the execution unit comprising a logic circuit implementing a sort instruction for sorting the plurality of data items stored in the first register in an order of data item values, and storing, in the second register, a plurality of indices, wherein each index identifies a position associated with a data item stored in the first register prior to the sorting.Type: GrantFiled: December 23, 2015Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Asit K. Mishra, Kshitij A. Doshi, Elmoustapha Ould-Ahmed-Vall, Deborah T. Marr
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Patent number: 9996362Abstract: Systems and methods for utilizing a diagnostics only boot mode may include initializing, by a computing device comprising a processor, a boot sequence. The computing device may detect installation of a hardware module. In response to detection of the hardware module, the computing device may initialize an alternate boot sequence.Type: GrantFiled: October 30, 2015Date of Patent: June 12, 2018Assignee: NCR CorporationInventor: Gordon Chisholm
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Patent number: 9996363Abstract: In a compositing window system, as a respective version of the window for an application is written into a window buffer, a corresponding set of per tile signatures indicative of the content of each respective tile in the window buffer is generated and stored. When an updated version of the window is stored into a window buffer, the set of signature values for the updated version is compared to the set of signature values for the previous version in the window buffer to determine which tiles' content has changed. The set of tiles found to have changed is used to generate a set of regions for a window compositor to write to a window in a display frame buffer to update the window in the display frame buffer to display the new version of the window.Type: GrantFiled: March 30, 2012Date of Patent: June 12, 2018Assignee: ARM LimitedInventors: Tom Cooksey, Jon Erik Oterhals, Jørn Nystad, Lars Ericsson, Eivind Liland, Daren Croxford
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Patent number: 9996364Abstract: Methods, devices, and systems are used for a vehicle user interface adaption system. In an example, operations may be effectuated that include displaying a graphical user interface including a first plurality of objects associated with a first unmanned aerial vehicle and receiving data that includes a message from the graphical user interface indicative of a selection of a second unmanned aerial vehicle. A second plurality of objects may be displayed based on the received data.Type: GrantFiled: August 6, 2014Date of Patent: June 12, 2018Assignee: Insitu, Inc.Inventor: James Bryan Zimmerman
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Patent number: 9996365Abstract: A method, system, and/or computer program product formats a layout of an application graphical user interface (GUI). A description of a layout of an operating system (OS) GUI is received. The OS supports an application, and the layout of the OS GUI identifies positions of representations of OS features that are displayed on the OS GUI. The OS features are mapped to application features of the application that is supported by the OS. A layout of an application GUI for the application is formatted to mirror an appearance of the OS GUI, such that representations of the application features are displayed in a same relative position on the application GUI as representations of mapped-to OS features on the OS GUI.Type: GrantFiled: May 12, 2015Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Richard E. Berube, Fang Lu, Jennifer L. Moriarty, Sneha Palarapu, Tejaswini K. Ranadive
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Patent number: 9996366Abstract: A user interface for dynamically validating at least a portion of programming codes as an application program interface (API) modification request. A first window area statically displays data definitions for one or more configurable elements for a request to be operably connected to an API. A second window area displays programming codes structured according to the data definitions for the request. The second window area also receives a first input from a user to modify the configurable elements. In response to receiving the first input, a dynamic request display area receives an instruction from the user to submit the programming codes to the API for validation. The submitted programming codes are not complete as a complete transaction request for processing by the API. The dynamic request display area displays a response substantially immediate after the programming codes are submitted, and response indicates whether the submitted programming codes are valid.Type: GrantFiled: July 12, 2016Date of Patent: June 12, 2018Assignee: VISA INTERNATIONAL SERVICE ASSOCIATIONInventors: Bhavana Tammineni, Shobhit Agrawal
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Patent number: 9996367Abstract: A method for cognitive screen sharing protection is provided. The method may include, in determining a screen sharing session of a client computing device associated with a user has been initiated, receiving, by a processor, a plurality of pertinent state data associated with the client computing device. The method may also include assigning an initial binary status to at least one display window of at least one open application on the client computing device. The method may further include, in determining a change has occurred to the screen sharing session, updating each assigned binary status. The method may also include detecting an undesirable sharing situation on the client computing device based on the updated binary status of the at least one display window. The method may further include performing a precautionary action based on the detected undesirable sharing situation.Type: GrantFiled: September 19, 2017Date of Patent: June 12, 2018Assignee: International Business Machines CorporationInventors: Sheng Hua Bao, Richard L. Martin