Abstract: A semiconductor device (e.g., a flip chip) includes a substrate layer that is separated from a drain contact by an intervening layer. Trench-like feed-through elements that pass through the intervening layer are used to electrically connect the drain contact and the substrate layer when the device is operated.

Abstract: An LDMOS is formed with a second gate stack over n? drift region, having a common gate electrode with the gate stack, and having a higher work function than the gate stack. Embodiments include a device including a substrate; a first well and a second well in the substrate, the first well being doped with a first conductivity type dopant, the second well being doped with a second conductivity type dopant, and the second well surrounding the first well; a source in the first well and a drain in the second well; a doped region of the first conductivity type dopant in the first well, the doped region functioning as a body contact to the first well; a first gate stack on a portion of the first well; a second gate stack on a portion of the second well, the first and second gate stacks having a common gate electrode.

Abstract: A threshold voltage adjusted long-channel transistor fabricated according to short-channel transistor processes is described. The threshold-adjusted transistor includes a substrate with spaced-apart source and drain regions formed in the substrate and a channel region defined between the source and drain regions. A layer of gate oxide is formed over at least a part of the channel region with a gate formed over the gate oxide. The gate further includes at least one implant aperture formed therein with the channel region of the substrate further including an implanted region within the channel between the source and drain regions. Methods for forming the threshold voltage adjusted transistor are also disclosed.

Abstract: A semiconductor device configured with one or more integrated breakdown protection diodes in non-isolated power transistor devices and electronic apparatus, and methods for fabricating the devices.

Abstract: Integrated circuits and methods of producing integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a substrate and a gate overlying the substrate. A drain is defined within the substrate, where the drain and the gate are separated by a drain distance. A source is defined within the substrate adjacent to the gate, wherein the source is divided into two or more source sections.

Abstract: The present invention concept relates to vertical field effect transistor and method of fabricating the same. A method of fabricating a vertical field effect transistor is provided as follows. A fin structure having a sidewall is formed on a substrate. A lower spacer, a gate pattern and an upper spacer surround a lower sidewall region, a center sidewall region and an upper sidewall region, respectively. The lower spacer, the gate pattern and the upper spacer are vertically stacked on each other along the sidewall of the fin structure. To form the lower spacer, a preliminary spacer layer is formed to surround the lower sidewall region of the fin structure; a doped region and an undoped region are formed in the preliminary spacer layer by doping partially impurities in the preliminary spacer using a directional doping process; and the undoped region of the preliminary spacer layer is removed so that the doped region of the preliminary spacer layer remains to form the lower spacer.

Abstract: A device is disclosed. The device comprises a substrate having an epitaxial layer of a first conductivity type, a deep trench of a first depth, a pillar region of a second conductivity type of a second depth and a blocking layer of a third conductivity type immediately below a bottom surface of the deep trench. The second depth is larger than the first depth.

Abstract: A matrix rail structure is formed over a substrate. The matrix rail structure includes a pair of lengthwise sidewalls that extend along a first horizontal direction and comprises, or is at least partially subsequently replaced with, a set of at least one gate electrode rail extending along the first horizontal direction and straight-sidewalled gate dielectrics. A pair of vertical semiconductor channel strips and a pair of laterally-undulating gate dielectrics can be formed on sidewalls of the matrix rail structure for each vertical field effect transistor. At least one laterally-undulating gate electrode extending along the first horizontal direction is formed on the laterally-undulating gate dielectrics. Bottom active regions and top active regions are formed at end portions of the vertical semiconductor channel strips. The vertical field effect transistors can be formed as a two-dimensional array, and may be employed as access transistors for a three-dimensional memory device.

Abstract: A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.

Abstract: Fin field-effect transistor (FinFET) devices and methods of forming the same are provided herein. In an embodiment, a FinFET device includes a semiconductor substrate having a plurality of fins disposed in parallel relationship. A first insulator layer overlies the semiconductor substrate, with the fins extending through and protruding beyond the first insulator layer to provide exposed fin portions. A gate electrode structure overlies the exposed fin portions and is electrically insulated from the fins by a gate insulating layer. Epitaxially-grown source regions and drain regions are disposed adjacent to the gate electrode structure. The epitaxially-grown source regions and drain regions have an asymmetric profile along a lateral direction perpendicular to a length of the fins.

Abstract: Techniques are disclosed for forming a GaN transistor on a semiconductor substrate. An insulating layer forms on top of a semiconductor substrate. A trench, filled with a trench material comprising a III-V semiconductor material, forms through the insulating layer and extends into the semiconductor substrate. A channel structure, containing III-V material having a defect density lower than the trench material, forms directly on top of the insulating layer and adjacent to the trench. A source and drain form on opposite sides of the channel structure, and a gate forms on the channel structure. The semiconductor substrate forms a plane upon which both GaN transistors and other transistors can form.

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

Abstract: Contact structures, FinFET devices and methods of forming the same are disclosed. One of the contact structures includes a source/drain region, a mask layer, a connector and a shielding pattern. The source/drain region is between two gate stacks. A mask layer is over the gate stacks and has an opening corresponding to the source/drain region. The connector is electrically connected to the source/drain region, penetrates through the opening of the mask layer and protrudes above and below the mask layer. The shielding pattern is between the mask layer and the connector and in physical contact with the mask layer.

Abstract: A semiconductor device includes a substrate, an insulating structure, and a gate stack. The substrate has at least one semiconductor fin. The insulating structure is disposed above the substrate and separated from the semiconductor fin to form a gap therebetween. The insulating structure has a sidewall facing the semiconductor fin. The gate stack covers at least a portion of the semiconductor fin and is at least disposed in the gap between the insulating structure and the semiconductor fin. The gate stack includes a high-? dielectric layer and a gate electrode. The high-? dielectric layer covers the semiconductor fin while leaves the sidewall of the insulating structure uncovered. The gate electrode is disposed above the high-? dielectric layer and at least in the gap between the insulating structure and the semiconductor fin.

Abstract: The present description relates to the formation source/drain structures within non-planar transistors, wherein fin spacers are removed from the non-planar transistors in order to form the source/drain structures from the non-planar transistor fins or to replace the non-planar transistor fins with appropriate materials to form the source/drain structures.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements and partially removing the spacer elements such that an upper portion of the recess becomes wider. The method further includes forming a metal gate stack in the recess and forming a protection element in the recess to cover the metal gate stack.

Abstract: The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a first semiconductor region, a second semiconductor region, and a plurality of semiconductor bridges each of which connecting the first semiconductor region and the second semiconductor region; the plurality of semiconductor bridges spaced apart from each other; the active layer being made of a material including M1OaNb, wherein M1 is a single metal or a combination of metals, a>0, and b?0; an etch stop layer on a side of the active layer distal to the base substrate; the first semiconductor region having a first non-overlapping portion, a projection of which is outside that of the etch stop layer in plan view of the base substrate; the second semiconductor region having a second non-overlapping portion, a projection of which is outside that of the etch stop layer in plan view of the base substrate; a first electrode on a side of the first non-overlapping portion distal to the

Abstract: A highly reliable semiconductor device is provided. The semiconductor device includes a first barrier insulating film; a first gate electrode thereover; a first gate insulating film thereover; an oxide semiconductor film thereover; source and drain electrodes over the oxide semiconductor film; a second gate insulating film over the oxide semiconductor film; a second gate electrode over the second gate insulating film; a second barrier insulating film that covers the oxide semiconductor film, the source and the drain electrodes, and the second gate electrode, and is in contact with side surfaces of the oxide semiconductor film and the source and drain electrodes; and a third barrier insulating film thereover. The first to third barrier insulating films are less likely to transmit hydrogen, water, and oxygen than the first and second gate insulating films. The third barrier insulating film is thinner than the second barrier insulating film.

Abstract: The invention relates to a method for forming a uniform silicide film using a crystalline semiconductor film in which orientation of crystal planes is controlled, and a method for manufacturing a thin film transistor with less variation in electric characteristics, which is formed over an insulating substrate using the silicide film. A semiconductor film over which a cap film is formed is irradiated with a laser to be crystallized under the predetermined condition, so that a crystalline semiconductor film including large grain crystals in which orientation of crystal planes is controlled in one direction is formed. The crystalline semiconductor film is used for silicide, whereby a uniform silicide film can be formed.

Abstract: The thin film transistor includes a first insulating layer provided on a substrate; a source electrode and a drain electrode that are provided on the first insulating layer; a semiconductor layer provided so as to cover the first insulating layer, the source electrode, and the drain electrode; a second insulating layer provided on the semiconductor layer; and a gate electrode provided on the second insulating layer, in which the first insulating layer is formed of a hydrophilic/hydrophobic material and has a recess portion, and the source electrode and the drain electrode are provided so as to fill the recess portion of the first insulating layer.

Abstract: A semiconductor device with a novel structure is provided. A semiconductor device with reduced power consumption is provided. A circuit which is configured to supply a signal from an input terminal to both a gate and a backgate of a transistor in a first state and to only the gate in a second state is provided. With this structure, a current supply capability of the transistor can be changed between operations; accordingly, power consumption can be reduced by the amount needed to charge the backgate.

Abstract: A thin-film transistor, including a substrate; an active layer on the substrate; a gate electrode on the active layer; and a gate insulating layer between the active layer and the gate electrode, the active layer including a channel region; source and drain regions at opposite sides of the channel region; and lightly doped regions between the channel region and the source region and between the channel region and the drain region, the source and drain regions being doped with a first element, and the lightly doped regions being doped with a second element different from the first element.

Abstract: The present disclosure provides a solution for a metal oxide semiconductor thin film, including metal hydroxides dissolved in an aqueous or nonaqueous solvent and an acid/base titrant for controlling solubility of metal hydroxides. A solution is synthesized to improve stability and semiconductive performance of a device through addition of other metal hydroxides. The solution is applied on a substrate and annealed by using various annealing apparatuses to obtain a high-quality metal oxide thin film at low temperatures. The thin film is optically transparent, and thus can be applied to thin films for various electronic devices, solar cells, various sensors, memory devices, and the like.

Abstract: An apparatus is provided that includes a substrate and source and drain regions within an annealed active layer having resulted from an annealing of an active layer comprising metal-oxide and formed on the substrate, and an impermeable layer over the source and drain regions of the annealed active layer, wherein the annealing resulting in the annealed active layer was performed with the impermeable layer over portions of the active layer corresponding to the source and drain regions, thereby resulting in a reduction of a resistivity of the source and drain regions of the annealed active layer relative to the active layer. In another aspect, a junctionless transistor is provided wherein the entire active area has a low resistivity based on annealing of an active layer including metal oxide while uncovered or at least partially covered with layers of various gas permeability under oxidizing or non-oxidizing conditions.

Abstract: An imaging element which is capable of obtaining a piece of image data by performing light exposure plural times is provided. In addition, an imaging element which is capable of obtaining image data with little noise is provided. Furthermore, an imaging device with reduced power consumption is provided. In an imaging element including a pixel, the pixel includes a photodiode, a transistor including an oxide semiconductor layer, a diode, and a charge retention portion. The polarity of an electrode of the photodiode which is connected to the transistor is the same as that of an electrode of the diode which is connected to the transistor.

Abstract: A transistor having high field-effect mobility is provided. In order that an oxide semiconductor layer through which carriers flow is not in contact with a gate insulating film, a buried channel structure in which the oxide semiconductor layer through which carriers flow is separated from the gate insulating film is employed. Specifically, an oxide semiconductor layer having high conductivity is provided between two oxide semiconductor layers. Further, an impurity element is added to the oxide semiconductor layer in a self-aligned manner so that the resistance of a region in contact with an electrode layer is reduced. Further, the oxide semiconductor layer in contact with the gate insulating layer has a larger thickness than the oxide semiconductor layer having high conductivity.

Abstract: An oxide sputtering target includes at least one of indium (In), zinc (Zn), tin (Sn), and gallium (Ga), and tungsten (W) in an amount from 0.005 mol % to 1 mol %.

Abstract: Favorable electrical characteristics are given to a semiconductor device. Furthermore, a semiconductor device having high reliability is provided. One embodiment of the present invention is an oxide semiconductor film having a plurality of electron diffraction patterns which are observed in such a manner that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose half-width is 1 nm. The plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed in different areas, the sum of the percentage of first electron diffraction patterns and the percentage of second electron diffraction patterns accounts for 100%, the first electron diffraction patterns account for 90% or more, the first electron diffraction pattern includes observed points which indicates that a c-axis is oriented in a direction substantially perpendicular to the surface where the oxide semiconductor film is formed.

Abstract: The reliability of a transistor including an oxide semiconductor is improved. The transistor in a semiconductor device includes a first oxide semiconductor film over a first insulating film, a gate insulating film over the first oxide semiconductor film, a second oxide semiconductor film over the gate insulating film, and a second insulating film over the first oxide semiconductor film and the second oxide semiconductor film. The first oxide semiconductor film includes a channel region overlapping with the second oxide semiconductor film, a source region and a drain region each in contact with the second insulating film. The channel region includes a first layer and a second layer in contact with a top surface of the first layer and covering a side surface of the first layer in the channel width direction. The second oxide semiconductor film has a higher carrier density than the first oxide semiconductor film.

Abstract: The present invention relates to an amorphous oxide and a thin film transistor using the amorphous oxide. In particular, the present invention provides an amorphous oxide having an electron carrier concentration less than 1018/cm3, and a thin film transistor using such an amorphous oxide. In a thin film transistor having a source electrode 6, a drain electrode 5, a gate electrode 4, a gate insulating film 3, and a channel layer 2, an amorphous oxide having an electron carrier concentration less than 1018/cm3 is used in the channel layer 2.

Abstract: A switching element of LCDs or organic EL displays which uses a thin film transistor device, includes: a drain electrode, a source electrode, a channel layer contacting the drain electrode and the source electrode, wherein the channel layer comprises indium-gallium-zinc oxide having a transparent, amorphous state of a composition equivalent to InGaO3(ZnO)m (wherein m is a natural number less than 6) in a crystallized state, and the channel layer has a semi-insulating property represented by an electron mobility of more than 1 cm2/(V·sec) and an electron carrier concentration is less than 1018/cm3, a gate electrode, and a gate insulating film positioned between the gate electrode and the channel layer.

Abstract: Disclosed are an oxide thin-film transistor and a method of fabricating the same. The oxide thin-film transistor according to an embodiment of the present disclosure includes a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; and an oxide thin film formed on the gate insulating layer, wherein the oxide thin film include a channel region, source region and drain regions disposed on the channel region and spaced apart from each other, and a concentration profile due to a dopant diffused from the gate insulating layer, wherein the channel region operates as a channel layer by the concentration profile.

Abstract: Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.

Abstract: To provide a semiconductor device which has transistor characteristics with little variation and includes an oxide semiconductor. The semiconductor device includes an insulating film over a conductive film and an oxide semiconductor film over the insulating film. The oxide semiconductor film includes a first oxide semiconductor layer, a second oxide semiconductor layer over the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer. The energy level of a bottom of a conduction band of the second oxide semiconductor layer is lower than those of the first and third oxide semiconductor layers. An end portion of the second oxide semiconductor layer is positioned on an inner side than an end portion of the first oxide semiconductor layer.

Abstract: A semiconductor memory device includes a substrate, a multi-layered structure including a plurality of insulating layers and a plurality of conductive layers that are alternately formed above the substrate, and a pillar extending through the multi-layered structure. The pillar includes a semiconductor body extending along the pillar, and a charge-storing film around the semiconductor body, the charge-storing film having a first thickness at first portions facing the insulating layers and a second thickness greater than the first thickness at second portions facing the conductive layers.

Abstract: A method for manufacturing a resistive element includes: preparing a substrate including an n-type silicon layer; doping the silicon layer with an impurity to thereby form a resistive region; heat-treating the resistive region by any of rapid thermal annealing, flash lamp annealing, and excimer laser annealing; and epitaxially growing silicon on the resistive region to thereby form a covering layer.

Abstract: A semiconductor device structure includes a region of semiconductor material with a first major surface and an opposing second major surface. A contact structure is disposed in a first portion of the region of semiconductor material and includes a tub structure extending from adjacent a first portion of the first major surface. A plurality of structures comprising portions of the region of semiconductor material extend outward from a lower surface of the tub structure. In some embodiments, the plurality of structures comprises a plurality of free-standing structures. A conductive material is disposed within the tub structure and laterally surrounding the plurality of structures. In one embodiment, the contact structure facilitates the fabrication of a monolithic series switching diode structure having a low-resistance substrate contact.

Abstract: A semiconductor device includes a first gallium nitride layer disposed on a semiconductor substrate, wherein the first gallium nitride layer has a first conductivity type. The semiconductor device also includes a second gallium nitride layer disposed on the first gallium nitride layer, wherein the second gallium nitride layer has the first conductivity type, and the first gallium nitride layer has a dopant concentration which is greater than that of the second gallium nitride layer. The semiconductor device further includes an anode electrode disposed on the second gallium nitride layer, a cathode electrode disposed on and in direct contact with the first gallium nitride layer, and an insulating region disposed on and in direct contact with the first gallium nitride layer, wherein the insulating region is located between the cathode electrode and the second gallium nitride layer.

Abstract: The inventive technology, in certain embodiments, may be generally described as a solar power generation system with a converter, which may potentially include two or more sub-converters, established intermediately of one or more strings of solar panels. Particular embodiments may involve sweet spot operation in order to achieve improvements in efficiency, and bucking of open circuit voltages by the converter in order that more panels may be placed on an individual string or substring, reducing the number of strings required for a given design, and achieving overall system and array manufacture savings.

Abstract: A solar cell is provided with: a semiconductor substrate having a light-receiving surface and a non-light-receiving surface; a PN junction section formed on the semiconductor substrate; a passivation layer formed on the light-receiving surface and/or the non-light-receiving surface; and power extraction electrodes formed on the light-receiving surface and the non-light-receiving surface. The solar cell is characterized in that the passivation layer includes an aluminum oxide film having a thickness of 40 nm or less. As a result of forming a aluminum oxide film having a predetermined thickness on the surface of the substrate, it is possible to achieve excellent passivation performance and excellent electrical contact between silicon and the electrode by merely firing the conductive paste, which is conventional technology. Furthermore, an annealing step, which has been necessary to achieve the passivation effects of the aluminum oxide film in the past, can be eliminated, thus dramatically reducing costs.

Abstract: A method of manufacturing a photoelectric conversion element including a semiconductor layer includes: forming an electrode; forming an insulating layer covering the electrode; forming an opening in a region of the insulating layer overlapping the electrode in a plan view; forming a covering layer of a semiconductor material on a surface of the insulating layer; and forming the semiconductor layer by patterning the covering layer. In the forming of the semiconductor layer, the semiconductor layer is formed such that an outer circumferential edge of the semiconductor layer is located on the outside of an inner circumferential edge of the opening in the plan view.

Abstract: Methods of fabricating solar cells using a metal-containing thermal and diffusion barrier layer in foil-based metallization approaches, and the resulting solar cells, are described. For example, a method of fabricating a solar cell includes forming a plurality of semiconductor regions in or above a substrate. The method also includes forming a metal-containing thermal and diffusion barrier layer above the plurality of semiconductor regions. The method also includes forming a metal seed layer on the metal-containing thermal and diffusion barrier layer. The method also includes forming a metal conductor layer on the metal seed layer. The method also includes laser welding the metal conductor layer to the metal seed layer. The metal-containing thermal and diffusion barrier layer protects the plurality of semiconductor regions during the laser welding.

Abstract: A semiconductor structure includes a thin-film device layer, an optoelectronic device disposed in the thin-film device layer, and a surrogate substrate permanently attached to the thin film device layer. The surrogate substrate is optically transparent and has a thermal conductivity of at least 300 W/m-K. The optoelectronic device excitable by visible light transmitted through the surrogate substrate. A method of fabricating the semiconductor structure includes fabricating the optoelectronic device in a device layer thin-film of SiC on a silicon wafer of a first diameter, transferring the device layer thin-film of SiC from the silicon wafer, and permanently bonding the device layer thin-film to a SiC surrogate substrate of a second diameter.

Abstract: A solar cell device and a method of fabricating the same are described. The method of fabricating a solar cell includes forming a photovoltaic substructure including a substrate, back contact, absorber and buffer, forming a transparent cover separate from the photovoltaic substructure including a transparent layer and a plasmonic nanostructured layer in contact with the transparent layer, and adhering the transparent cover on top of the photovoltaic substructure. The plasmonic nanostructured layer can include metal nanoparticles.

Abstract: Disclosed herein is an electrically conductive adhesive composition and its use in solar cell modules, wherein the electrically conductive adhesive comprises a polymer matrix and dispersed in the polymer matrix about 40-90 wt % of conductive particles, with the wt % of all components comprised in the compositions totaling to 100 wt %, and wherein the polymer matrix comprises or is formed of a blend of at least one ethylene/alkyl (meth)acrylate copolymer elastomer and at least one ethylene vinyl acetate copolymer at a weight ratio ranging from about 10:90 to about 70:30.

Abstract: A system or device for concentrating the light radiation of the type to be used for converting the solar radiation into electric current and/or thermal energy is disclosed. The device mainly having a primary optics apt to be exposed to the solar radiation and to allow the passage thereof therethrough, the primary optics being positioned on a hollow spacer member, which is perfectly aligned and at the same time locked, by means of a joint member.

Abstract: A light concentrator includes a luminescent concentrator and a gain medium. The luminescent concentrator includes a semiconductor material and the semiconductor material absorbs first photons. The first photons have energy greater than or equal to a threshold energy, and the semiconductor material emits second photons through a spontaneous emission process where the second photons have less energy than the first photons. The gain medium is optically coupled to the luminescent concentrator to receive the second photons. The gain medium absorbs the second photons, and in response to absorbing the second photons, the gain medium emits third photons through a stimulated emission process. The third photons have less energy than the second photons.

Abstract: A solar battery module is provided with a plurality of solar cells, a wiring material for connecting adjacent solar cells in the longitudinal directors to form strings, and a reflective body disposed on the rear-surface side of the solar cells, said body reflecting at least some incident light toward the solar cells. In the solar battery module, the strings are multiply disposed in the horizontal direction to constitute string groups, intervals D20 between adjacent strings being formed wider in the longitudinal center section of the string groups than in the longitudinal end sections.

Abstract: Photovoltaic devices based on an Ag2ZnSn(S,Se)4 (AZTSSe) absorber and techniques for formation thereof are provided. In one aspect, a method for forming a photovoltaic device includes the steps of: coating a substrate with a conductive layer; contacting the substrate with an Ag source, a Zn source, a Sn source, and at least one of a S source and a Se source under conditions sufficient to form an absorber layer on the conductive layer having Ag, Zn, Sn, and at least one of S and Se; and annealing the absorber layer. Methods of doping the AZTSSe are provided. A photovoltaic device is also provided.

Abstract: An avalanche photodiode, and related method of manufacture and method of use thereof, that includes a first contact layer; a multiplication layer, wherein the multiplication layer includes AlInAsSb; a charge, wherein the charge layer includes AlInAsSb; an absorption, wherein the absorption layer includes AlInAsSb; a blocking layer; and a second contact layer.