Abstract: Capacitive coupling of integrated circuit die components and other conductive areas is provided. Each component to be coupled has a surface that includes at least one conductive area, such as a metal pad or plate. An ultrathin layer of dielectric is formed on at least one surface to be coupled. When the two components, e.g., one from each die, are permanently contacted together, the ultrathin layer of dielectric remains between the two surfaces, forming a capacitor or capacitive interface between the conductive areas of each respective component. The ultrathin layer of dielectric may be composed of multiple layers of various dielectrics, but in one implementation, the overall thickness is less than approximately 50 nanometers. The capacitance per unit area of the capacitive interface formed depends on the particular dielectric constants ? of the dielectric materials employed in the ultrathin layer and their respective thicknesses.

Abstract: A microelectronic assembly can include a microelectronic package connected with a circuit panel. The package has a microelectronic element having a front face facing away from a substrate of the package, and electrically connected with the substrate through conductive structure extending above the front face. First terminals provided in first and second parallel grids or in first and second individual columns can be configured to carry address information usable to determine an addressable memory location from among all the available addressable memory locations of the memory storage array. The first terminals in the first grid can have signal assignments which are a mirror image of the signal assignments of the first terminals in the second grid.

Abstract: A flexible lighting array, comprising: a flexible substrate; a pair of first electrical connectors formed on the flexible substrate; a pair of second electrical connectors formed on the flexible substrate; an isolation element formed on the flexible substrate between the pair of first electrical connectors and the pair of second electrical connectors; a plurality of first light-emitting elements formed over the pair of first electrical connectors; one or more second light-emitting elements formed over the pair of second electrical connectors; and a transparent covering layer formed over the plurality of first light-emitting elements and the one or more second light-emitting elements, wherein, the plurality of first light-emitting elements are configured to emit visible light in a wavelength range of 200 nm to 800 nm, and the one or more second light-emitting elements are configured to emit infrared light in a wavelength range of 800 nm to 1200 nm.

Abstract: A method of manufacturing a light-emitting apparatus includes mounting a first light-emitting element and a second light-emitting element on a substrate. A sealing layer is formed above the first light-emitting element and the second light-emitting element for sealing the first light-emitting element and the second light-emitting element. A first phosphor layer is applied above a first portion of the sealing layer, in which the first phosphor layer includes at least one first phosphor. A second phosphor layer is applied above a second portion of the sealing layer, in which the second phosphor layer includes at least one second phosphor.

Abstract: A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current terminal for a load current output. At least one outer load current terminal and at least one inner load current terminal per load current direction include a load current input and a load current output. At least one contacting device for common electrical contacting all of the load current terminals of the same load current direction includes a load current input and a load current output. The contacting device includes a plurality of terminal tongues which are respectively fastened on an associated load current terminal. The geometry and/or profile of the terminal tongue of an outer load current terminal differs from the geometry and/or profile of the terminal tongue of an inner load current terminal of the same contacting device.

Abstract: A semiconductor package assembly is provided. The semiconductor package assembly includes a first semiconductor package. The first semiconductor package includes a first semiconductor die. A first redistribution layer (RDL) structure is coupled to the first semiconductor die and includes a first conductive trace. The semiconductor package assembly also includes a second semiconductor package bonded to the first semiconductor package. The second semiconductor package includes a second semiconductor die. An active surface of the second semiconductor die faces an active surface of the first semiconductor die. A second RDL structure is coupled to the second semiconductor die and includes a second conductive trace. The first conductive trace is in direct contact with the second conductive trace.

Abstract: A light-emitting diode (LED) projector includes an LED display panel and a projection lens arranged in front of LED display panel and configured to collect and project light emitted by the LED display panel. The LED display panel includes an LED panel and a micro lens array arranged over the LED panel. The LED panel includes a substrate, a driver circuit array on the substrate and including a plurality of pixel driver circuits arranged in an array, and an LED array including a plurality of LED dies each being coupled to one of the pixel driver circuits. The micro lens array includes a plurality of micro lenses each corresponding to and being arranged over at least one of the LED dies.

Abstract: According to one embodiment, at first, a compound semiconductor layer is bonded to a position straddling a plurality of chip formation regions arranged on a substrate. One of the chip formation regions has a first size, and the compound semiconductor layer has a second size smaller than the first size. Thereafter, the compound semiconductor layer is processed to provide compound semiconductor elements on the chip formation regions. Then, the substrate is divided to correspond to the chip formation regions.

Abstract: A method of manufacturing a semiconductor device includes providing a material above a substrate and respectively forming separate gate electrode lines on opposite sidewalls of the material. As such, a width of cut between the gate electrode lines can be minimized. This shortens a height of cell of the semiconductor device, increasing a cell density of the semiconductor device.

Abstract: A semiconductor device includes an annular-shaped first frame comprised of a ceramic and forming an inner cavity in which semiconductor elements are disposed. A first electrode is on one side and a second electrode is on another. A second frame in the inner cavity holds the semiconductor elements and is comprised of a resin. A first metallic member is on one side, has an annular shape, and connects the first frame and first electrode. A second metallic member is on the other side, has an annular shape, and connects the first frame and the second electrode. A first elastic body has a first portion between the first metallic member and the second frame and a second portion abutting an inner sidewall of the first frame or overlapping the first frame. A second elastic body has a first portion between the second metallic member and the second frame.

Abstract: Electronic devices and methods of producing such electronic devices are provided. In an exemplary embodiment, a method of producing an electronic device includes forming a protected circuit and an ESD circuit, where the ESD circuit is configured to discharge an electrostatic discharge (ESD) to a ground such that the ESD bypasses the protected circuit. An ESD transistor is formed in the ESD circuit, where the ESD transistor includes a source and a drain. The ESD transistor also includes a gate with a gate width perpendicular to a gate length, where the gate length is measured across the gate from the source to the drain. A trigger voltage of the ESD transistor is set by adjusting the gate width.

Abstract: A semiconductor device includes a first diode having a cathode connected to a first terminal, a second diode having a cathode connected to a second terminal and an anode connected to an anode of the first diode, a third diode having an anode connected to the first terminal and the cathode of the first diode, a fourth diode having an anode connected to the second terminal and the anode of the second diode and a cathode connected to a cathode of the third diode, and a fifth diode having an anode connected to the anode of the first diode and the anode of the second diode and a cathode connected to the cathode of the third diode and the fourth diode. A breakdown voltage of the fifth diode is lower than the breakdown voltages of the first diode, the second diode, the third diode, and the fourth diode.

Abstract: In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS transistor and an nMOS transistor. The MOS device may include a first set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The first set of transistor body connections may couple a first voltage source to the pMOS transistor body. The first set of transistor body connections may further couple a second voltage source to the nMOS transistor body. The MOS device may include a second set of transistor body connections adjacent the pMOS transistor and the nMOS transistor. The second set of transistor body connections may couple the nMOS transistor gate to the pMOS transistor body. The second set of transistor body connections may further couple the pMOS transistor gate to the nMOS transistor body.

Abstract: In some embodiments, a field effect transistor structure includes a substrate, a fin structure and a gate structure. The fin structure is formed over the substrate. The fin structure includes a first channel region, a first source or drain region and a second source or drain region. The first source or drain region and the second source or drain region are formed on opposite ends of the first channel region, respectively. The well region is formed of the same conductivity type as the second source or drain region, connected to the second source or drain region, and extended to the substrate. The first gate structure wraps around the first channel region in the fin structure.

Abstract: Integrated circuits and methods of producing such integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a deep well with a drain well overlying the deep well. A first source well also overlies the deep well, where the first source well includes a first source well concentration of conductivity determining impurities. A second source well overlies the first source well, where the second source well includes a second concentration of conductivity determining impurities that is higher than the first source well concentration. A drain overlies the drain well and a source overlies the second source well. A channel is defined between the source and the drain and a gate overlies the channel.

Abstract: VDMOS transistors, Bipolar-CMOS-DMOS (BCD) devices including VDMOS transistors, and methods for fabricating integrated circuits with such devices are provided. In an example, a BCD device having a VDMOS transistor includes a buried layer over a substrate and an epitaxial layer over the buried layer and having an upper surface. Deep trench isolation regions extend from the upper surface of the epitaxial layer, into the substrate, and isolate a VDMOS region from a device region. In the VDMOS region, a source region is adjacent the upper surface, a vertical gate structure extends into the epitaxial layer, a body region is located adjacent the vertical gate structure and forms a channel, and a VDMOS conductive structure extends through the epitaxial layer and into the buried layer, which is a drain for the VDMOS transistor. The VDMOS conductive structure is a drain contact to the buried layer.

Abstract: According to an embodiment of a semiconductor device, the semiconductor device includes a semiconductor body having a main surface, the semiconductor body including a drift region of a first band-gap material, the drift region being of a first conductivity type, and a metallization arranged at the main surface. In a cross-section which is substantially orthogonal to the main surface, the semiconductor body further includes a contact region of the first band-gap material directly adjoining the drift region and the metallization, and an anode region of a second band-gap material having a lower band-gap than the first band-gap material. The contact region is of a second conductivity type. The anode region is in ohmic contact with the metallization and forms a heterojunction with the drift region.

Abstract: A semiconductor device includes an antenna functioning as a coil, a capacitor electrically connected to the antenna in parallel, a passive element forming a resonance circuit with the antenna and the capacitor by being electrically connected to the antenna and the capacitor in parallel, a first field effect transistor controlling whether the passive element is electrically connected to the antenna and the capacitor in parallel or not, and a memory circuit. The memory circuit includes a second field effect transistor which includes an oxide semiconductor layer where a channel is formed and in which a data signal is input to one of a source and a drain. The gate voltage of the first field effect transistor is set depending on the voltage of the other of the source and the drain of the second field effect transistor.

Abstract: A semiconductor device includes dummy gate structures formed on a dielectric layer over a substrate and forming a gap therebetween. A trench silicide structure is formed in the gap on the dielectric layer and extends longitudinally beyond the gap on end portions. The trench silicide structure forms a resistive element. Self-aligned contacts are formed through an interlevel dielectric layer and land on the trench silicide structure beyond the gap on the end portions.

Abstract: A multi-layered semiconductor device and method of manufacture are provided. In an embodiment a first semiconductor layer, a first insulator layer, a second semiconductor layer, a second insulator layer, and a third semiconductor layer are formed over a substrate. A first transistor comprises the first semiconductor layer, the first insulator layer, and the second semiconductor layer, and a second transistor comprises the second semiconductor layer, the second insulator layer, and the third semiconductor layer.

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first capacitor with a first gate overlying a first gate dielectric that in turn overlies a first channel. a second capacitor includes a second gate overlying a second gate dielectric that in turn overlies a second channel. The second gate dielectric has a different composition than the first gate dielectric. A capacitor interconnect is in electrical communication with the first capacitor and with the second capacitor.

Abstract: Methods of fabricating integrated circuits and integrated circuits fabricated by those methods are provided. In an exemplary embodiment, a method includes providing a substrate having a first and second device wells, a gate dielectric overlying the first and second device wells, a first gate electrode layer overlying the gate dielectric, and a shallow trench isolation structure between the first and second device wells. An insulating dielectric layer is formed only partially overlying the first gate electrode layer. A second gate electrode material is deposited overlying at least the insulating dielectric layer to form a second gate electrode layer. The layers are patterned to form a second gate structure overlying the second device well. A contact is formed on the second gate electrode layer of the second gate structure with the contact overlying dielectric material of at least one of the insulating dielectric layer or the shallow trench isolation structure.

Abstract: A structure including a plurality of fins etched from a semiconductor substrate, a gate electrode above and perpendicular to the plurality of fins, a pair of sidewall spacers disposed on opposing sides of the gate electrode, a gap fill material above the semiconductor substrate and between the plurality of fins, the gap fill material is directly below the gate electrode and directly below the pair of sidewall spacers, wherein the gate electrode separates the gap fill material from each of the plurality of fins, and an epitaxially grown region above a portion of the plurality of fins not covered by the gate electrode, the EPI region separates the gap fill material from each of the plurality of fins.

Abstract: A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate stack includes at least one work function conductor and a filling conductor. The work function conductor has a recess therein. The filling conductor includes a plug portion and a cap portion. The plug portion is present in the recess of the work function conductor. The cap portion caps the work function conductor.

Abstract: The invention relates to a switching device for switching radio frequency signals. The switching devices comprises at least a first field effect transistor that comprises a first source node, a first gate node and a first drain node, wherein the first gate node is arranged between a first drain region and a first source region on a semiconductor substrate. The switching device comprises at least a second field effect transistor that comprises a second source node, a second gate node and a second drain node, wherein the second gate node is arranged between a second drain region and a second source region on the same semiconductor substrate. The first source region of the first transistor is directly connected to the second drain region of the second transistor to build a common node of the switching device. An input node and an output node of the switching device are directly connected to the common node.

Abstract: Methods of maintaining a state of a memory cell without interrupting access to the memory cell are provided, including applying a back bias to the cell to offset charge leakage out of a floating body of the cell, wherein a charge level of the floating body indicates a state of the memory cell; and accessing the cell.

Abstract: An array of dynamic random access memory cells includes a first set of memory cell pairs in a first row, a second set of memory cells in a second row, and a first set of bit line contacts in the first row. The second set of memory cell pairs are disposed adjacent to the first set of memory cell pairs, and each two of the memory cell pairs in the second row include a common S/D region. Each of the first set of bit line contacts is electrically coupled to each of the common S/D regions of the memory cell pairs in the second row respectively.

Abstract: A semiconductor device includes a substrate, a plurality of lower electrodes disposed on the substrate and are repeatedly arranged in a first direction and in a second direction that crosses the first direction, and a first electrode support contacting a sidewall of at least one of the lower electrodes. The first electrode support includes a first support region including a first opening and a second support region disposed at a border of the first support region. An outer sidewall of the first electrode support includes a first sidewall extending in the first direction, a second sidewall extending in the second direction, and a connecting sidewall connecting the first and second sidewalls. The second support region includes the connecting sidewall. In a first portion of the second support region, a width of the first portion of the second support region decreases in a direction away from the first support region.

Abstract: An increase in chip area and a deterioration of delay performance are reduced without dummy cells or dummy gates for plasma damage, suppressing an increase in the capacitance of dummy cells or dummy gates and a deterioration of wiring. In the case where bit wires or bit contacts used for the DRAM cell region of a circuit block are used as wires and contacts for a logic circuit region, gate electrodes affected by plasma damage are automatically analyzed after the completion of placement and routing. The well contact region (well potential diffusion layer) of the logic circuit region contains dummy contacts for plasma damage.

Abstract: A semiconductor device may include a plurality of dummy wirings formed on a substrate at different vertical levels and electrically floated and a plurality of dummy contact plugs each electrically connected between two adjacent dummy wirings of the plurality of dummy wiring of the plurality of dummy wirings. No dummy wiring of the plurality of dummy wirings is electrically connected to a terminal of any one of a plurality of transistors included in the substrate.

Abstract: In a region just below an access gate electrode in an SRAM memory cell, a second halo region is formed adjacent to a source-drain region and a first halo region is formed adjacent to a first source-drain region. In a region just below a drive gate electrode, a third halo region is formed adjacent to the third source-drain region and a fourth halo region is formed adjacent to a fourth source-drain region. The second halo region is set to have an impurity concentration higher than the impurity concentration of the first halo region. The third halo region is set to have an impurity concentration higher than the impurity concentration of the fourth halo region. The impurity concentration of the first halo region and the impurity concentration of the fourth halo region are different from each other.

Abstract: A static random access memory (SRAM) cell includes first through fourth transistors being first type transistors and fifth and sixth transistors being second type transistors. Source regions of the first and second transistors are formed by a first source diffusion region, source regions of the fifth and sixth transistors are formed by second and third source diffusion regions, respectively, and source regions of the third and fourth transistors are formed by a fourth source diffusion region. The SRAM cell further includes a first data storage electrode linearly extending from a first gate line of the third and sixth transistors and electrically connecting the first gate line and the first and second source diffusion regions, and a second data storage electrode linearly extending from a second gate line of the second and fifth transistors and electrically connecting the second gate line and the third and fourth source diffusion regions.

Abstract: Integrated circuits and methods of forming the same are provided. An exemplary integrated circuit includes a semiconductor substrate and an anti-fuse device having a select transistor, a bitline contact, and a split channel transistor. The select transistor includes a select gate structure, a bitline source/drain region, and a shared source/drain region. The bitline contact is disposed over and in electrical communication with the bitline source/drain region. The split channel transistor is in electrical communication with the select transistor through the shared source/drain region. The split channel transistor includes an anti-fuse gate structure having an anti-fuse gate and an anti-fuse dielectric layer and a stepped gate structure disposed between the anti-fuse gate structure and the shared source/drain region and having a stepped gate and a stepped dielectric layer. The stepped dielectric layer has a greater thickness than the anti-fuse dielectric layer.

Abstract: An OTP memory device includes a first and a second doped region of the same polarity in a semiconductor substrate. The second doped region has a higher doping concentration than the first doped region. A source region and a drain region of an opposite polarity are also in the semiconductor substrate. The source is positioned over the lower doped region, and the drain is positioned over the higher doped region. A plurality of anti-fuse devices, separated from each other by a portion of the lower doped region, are each positioned at least partially above a respective portion of the source region (and, in turn, above the lower doped region). A first metal line is coupled to a first subset of the anti-fuse devices, and a second metal line is coupled to a different, second subset of the anti-fuse devices arranged between the anti-fuses in the first subset.

Abstract: A pair of floating gates disposed to be spaced apart from each other by a first distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a memory region. Also, a pair of floating gates disposed to be spaced apart from each other by a second distance and a pair of spacer insulating films disposed on each of the pair of floating gates are provided in a monitor region. Then, the second distance is smaller than the first distance. Thus, by narrowing a distance between the floating gates in the monitor region, a tapered portion can be provided on a side surface portion of the floating gate in the monitor region. Then, by checking this tapered portion, it is possible to understand the shape of the floating gate in the memory region.

Abstract: In a method of manufacturing a semiconductor device including a non-volatile memory formed in a memory cell area and a logic circuit formed in a peripheral area, a mask layer is formed over a substrate in the memory cell area and the peripheral area. A resist mask is formed over the peripheral area. The mask layer in the memory cell area is patterned by using the resist mask as an etching mask. The substrate is etched in the memory cell area. After etching the substrate, a memory cell structure in the memory cell area and a gate structure for the logic circuit are formed. A dielectric layer is formed to cover the memory cell structure and the gate structure. A planarization operation is performed on the dielectric layer. An upper portion of the memory cell structure is planarized during the planarization operation.

Abstract: A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions. The stacked structures are disposed on a semiconductor layer of a first conductivity type. Each stacked structure includes electrodes vertically stacked on each other and is extended in a first direction. The vertical semiconductor patterns penetrate the stacked structures. The common source regions of a second conductivity type are disposed in the semiconductor layer. At least one common source region is disposed between two adjacent stacked structures. The at least one common source region is extended in the first direction. The well pickup regions of the first conductivity type are disposed in the semiconductor layer. At least one well pickup region is adjacent to both ends of at least one stacked structure.

Abstract: A semiconductor memory device according to an embodiment includes a semiconductor layer, a control gate electrode, and an organic molecular layer provided between the semiconductor layer and the control gate electrode, and the organic molecular layer having an organic molecule that includes a molecular structure described by a molecular formula (1):

Abstract: Provided is a three-dimensional semiconductor memory device including a peripheral logic structure on a semiconductor substrate to include peripheral logic circuits and a lower insulating gapfill layer, a horizontal semiconductor layer on the peripheral logic structure, stacks on the horizontal semiconductor layer, each of the stacks including a plurality of electrodes vertically stacked on the horizontal semiconductor layer, and a plurality of vertical structures passing through the stacks and connected to the horizontal semiconductor layer. The horizontal semiconductor layer may include a first semiconductor layer disposed on the lower insulating gapfill layer and co-doped with an anti-diffusion material and first conductivity type impurities of a first impurity concentration, and a second semiconductor layer disposed on the first semiconductor layer and doped with first conductivity type impurities of a second impurity concentration lower than the first impurity concentration or undoped.

Abstract: According to one embodiment, a semiconductor device includes a substrate; a stacked body; a columnar portion; and a plate portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers include first to third electrode layers. The first electrode layer is most proximal to the substrate. The second electrode layer is most distal to the substrate. The columnar portion and the plate portion are provided inside the stacked body. The plate portion extends along the stacking direction of the stacked body and along a first direction orthogonal to the stacking direction. The plate portion includes first to third portions. The third portion is provided between the first portion and the second portion. Widths of the first portion and the second portion along a second direction are narrower than a width of the third portion along the second direction.

Abstract: A three-dimensional semiconductor memory device includes a substrate including a cell array region and a connection region and an electrode structure including first and second electrodes alternatingly and vertically stacked on the substrate and having a stair-step structure on the connection region. Each of the first and second electrodes may include electrode portions provided on the cell array region to extend in a first direction and to be spaced apart from each other in a second direction perpendicular to the first direction, an electrode connecting portion provided on the connection region to extend in the second direction and to horizontally connect the electrode portions to each other, and protrusions provided on the connection region to extend from the electrode connecting portion in the first direction and to be spaced apart from each other in the second direction.

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

Abstract: A method for forming a semiconductor device. It includes forming fin structures on a substrate, where the fin structure defines source and drain regions. It also includes forming a gate stack in contact with the fin structure, depositing an insulator on the substrate, and applying an etching process to remove portions of the insulator to form a trench to the source region. It also includes implanting a damaged epitaxial material into the trench and to the source regions, and applying a second etching process to remove portions of the insulator to form a trench in the insulator to the drain regions. Finally, the method includes growing an epitaxial junction material over the source and drain regions, and depositing a metal over the substrate.

Abstract: A semiconductor device includes a plurality of gates formed upon a semiconductor substrate that includes a plurality of outer active areas (e.g. CMOS/PMOS areas, source/drain regions, etc.) and one or more inner active areas. An isolator is formed upon one or more inner gates associated with the one or more inner active areas. A contact bar electrically connects the outer active areas and/or outer gates and is formed upon the isolator. The isolator electrically insulates the contact bar from the one or more inner active areas and/or the one or more inner gates.

Abstract: Disclosed is a display device that includes a display element including a plurality of thin film transistors; and a hard coating film on the display element, the hard coating film including: a base film; and a hard coating layer on the base film, the hard coating layer including a photo-curable resin composition and a plurality of porous particles.

Abstract: A display device includes a pixel portion in which a pixel electrode layer is arranged in a matrix, and an inverted staggered thin film transistor having a combination of at least two kinds of oxide semiconductor layers with different amounts of oxygen is provided corresponding to the pixel electrode layer. In the periphery of the pixel portion in this display device, a pad portion is provided to be electrically connected to a common electrode layer formed on a counter substrate through a conductive layer made of the same material as the pixel electrode layer. One objection of our invention to prevent a defect due to separation of a thin film in various kinds of display devices is realized, by providing a structure suitable for a pad portion provided in a display panel.

Abstract: Disclosed are an oxide semiconductor-based transistor and a method of manufacturing the same. The oxide semiconductor-based transistor includes: a substrate provided with a bottom electrode; an insulator layer formed on the substrate; an active layer formed on the insulator layer; an electron transport layer formed on the active layer; and a top electrode formed on the electron transport layer. Since the oxide semiconductor-based transistor has a hybrid channel of PBD formed along with indium-zinc oxide (IZO), it is possible to improve mobility of electric charges and stability of electric devices and control a threshold value.

Abstract: An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.

Abstract: Provided is a semiconductor device including: a first transistor over a substrate, the first transistor having a gate electrode, an oxide semiconductor film, and a gate insulating film between the gate electrode and the oxide semiconductor film; an insulating film over the first transistor, the insulating film having a first film and a second film over the first film; and a terminal electrically connected to the oxide semiconductor film through an opening portion in the insulating film. The insulating film has a first region in contact with the terminal, and the first region has an oxygen composition larger than that in another region of the insulating film.

Abstract: The invention provides an array substrate and a display device. The array substrate comprises a plurality of gate lines and a plurality of data lines which are arranged crosswise and are insulated from each other, and a plurality of pixel units, wherein each pixel unit comprises a control section and a display section, each of which is symmetrically distributed with the central line of a corresponding gate line as a symmetry axis, the control section is located at a cross-point of the gate line and the data line, and is at least partially overlapped with the gate line and the data line, the display section is located at a region defined by the gate line and the data line; and the control section is connected to the display section to control the display section for display. In the present invention, the aperture ratio of the array substrate is increased.