Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer and a second III-V compound layer disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A capping layer is disposed on the second III-V compound layer.

Abstract: In one aspect a semiconductor device as set forth herein can include a spacer having a first section of a first material and a second section of a second material, the second section disposed above a certain elevation and the first section disposed below the certain elevation. In one aspect a semiconductor device as set forth herein can include a conductive gate structure having a first length at elevations below a certain elevation and a second length at elevations above the certain elevation, the second length being less than the first length. A semiconductor device having one or more of a plural material spacer or a reduced length upper elevation conductive gate structure can feature a reduced likelihood of electrical shorting.

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

Abstract: Replacement metal gate structures with improved chamfered workfunction metal and self-aligned contact and methods of manufacture are provided. The method includes forming a replacement metal gate structure in a dielectric material. The replacement metal gate structure is formed with a lower spacer and an upper spacer above the lower spacer. The upper spacer having material is different than material of the lower spacer. The method further includes forming a self-aligned contact adjacent to the replacement metal gate structure by patterning an opening within the dielectric material and filling the opening with contact material. The upper spacer prevents shorting with the contact material.

Abstract: To enhance reliability and performance of a semiconductor device that has a fully-depleted SOI transistor, while a width of an offset spacer formed on side walls of a gate electrode is configured to be larger than or equal to a thickness of a semiconductor layer and smaller than or equal to a thickness of a sum total of a thickness of the semiconductor layer and a thickness of an insulation film, an impurity is ion-implanted into the semiconductor layer that is not covered by the gate electrode and the offset spacer. Thus, an extension layer formed by ion implantation of an impurity is kept from entering into a channel from a position lower than the end part of the gate electrode.

Abstract: A nanowire structure includes successive crystalline nanowire segments formed over a semiconductor substrate. A first crystalline segment formed directly on the semiconductor substrate provides electrical isolation between the substrate and the second crystalline segment. Second and fourth crystalline segments are each formed from a p-type or an n-type semiconductor material, while the third crystalline segment is formed from a semiconductor material that is oppositely doped with respect to the second and fourth crystalline segments.

Abstract: A method for producing a semiconductor device includes forming a semiconductor-pillar on a substrate and forming a laminated-structure of at least two composite layers, each including a metal layer and a semiconductor layer in contact with the metal layer, the semiconductor layer containing donor or acceptor atoms, and two interlayer insulating layers sandwiching the composite layers, such that a side surface of at least one of the two interlayer insulating layers is separated from a side surface of the semiconductor pillar. The laminated-structure surrounds the semiconductor pillar. A first heat treatment causes a reaction between the metal layer and the semiconductor layer to form an alloy layer, and brings the alloy layer into contact with the side surface of the semiconductor pillar. A second heat treatment to expands the alloy layer into the semiconductor pillar and diffuses dopant atoms into the semiconductor pillar to form an impurity region therein.

Abstract: Methods of forming a structure for a vertical-transport field-effect transistor and structures for a vertical-transport field-effect transistor. A semiconductor fin is formed on a sacrificial layer, and trench isolation is formed in which the semiconductor fin is embedded. The trench isolation is removed at opposite sidewalls of the semiconductor fin. After the trench isolation is removed at opposite sidewalls of the semiconductor fin, the sacrificial layer is removed to form a cavity extending beneath the semiconductor fin while the semiconductor fin is supported by the trench isolation adjacent to opposite end surfaces of the semiconductor fin. A semiconductor material is formed in the cavity to provide a source/drain region.

Abstract: A method comprises providing a substrate with a second conductivity type, growing a first epitaxial layer having the second conductivity type, growing a second epitaxial layer having a first conductivity type, forming a trench in the first epitaxial layer and the second epitaxial layer, forming a gate electrode in the trench, applying an ion implantation process using first gate electrode as an ion implantation mask to form a drain-drift region, forming a field plate in the trench, forming a drain region in the second epitaxial layer, wherein the drain region has the first conductivity type and forming a source region in the first epitaxial layer, wherein the source region has the first conductivity type, and wherein the source region is electrically coupled to the field plate.

Abstract: An array substrate for a display device is disclosed. The array substrate includes a substrate comprising a plurality of subpixels, at least one of which is a white subpixel. The array substrate also includes an insulating layer disposed on the substrate in each of the subpixels and a plurality of color filter layers disposed on the insulating layer, each of the color filter layers being disposed respectively in a corresponding one of the subpixels. At least two of the color filter layers have a same color and are respectively disposed in the white subpixel and in at least one of the subpixels adjacent to the white subpixel. The insulating layer has a slope at a boundary between the white subpixel and the at least one of the subpixels adjacent to the white subpixel.

Abstract: In some embodiments, a field effect transistor structure includes a first semiconductor structure and a gate structure. The first semiconductor structure includes a channel region, and a source region and a drain region. The source region and the drain region are formed on opposite ends of the channel region, respectively. The gate structure includes a central region and footing regions. The central region is formed over the first semiconductor structure. The footing regions are formed on opposite sides of the central region and along where the central region is adjacent to the first semiconductor structure.

Abstract: A method of forming fine patterns including forming a plurality of first sacrificial patterns on a target layer, the target layer on a substrate, forming first spacers on respective sidewalls of the first sacrificial patterns, removing the first sacrificial patterns, forming a plurality of second sacrificial patterns, the second sacrificial patterns intersecting with the first spacers, each of the second sacrificial patterns including a line portion and a tab portion, and the tab portion having a width wider than the line portion, forming second spacers on respective sidewalls of the second sacrificial patterns, removing the second sacrificial patterns, and etching the target layer through hole regions, the hole regions defined by the first spacers and the second spacers, to expose the substrate may be provided.

Abstract: The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary fabrication method includes providing a semiconductor substrate; forming a plurality of fins on the semiconductor substrate, each fin having a first sidewall surface and an opposing second sidewall surface; performing an asymmetric oxidation process on the fins to oxidize the first sidewall surfaces of the fins to form a first oxide layer, and to oxidize the second sidewall surfaces of the fins to form a second oxide layer, a thickness of the first oxide layer being different from a thickness of the second oxide layer, and un-oxidized portions of the fins between the first oxide layer and the second oxide layer being configured as channel layers; removing the second oxide layer and a partial thickness of the first oxide layer; and forming a gate structure crossing over the channel layers over the semiconductor substrate.

Abstract: Methods of fabricating a memory cell of a semiconductor device, e.g., an EEPROM cell, having a sidewall oxide are disclosed. A memory cell structure may be formed including a floating gate and an ONO film over the conductive layer. A sidewall oxide may be formed on a side surface of the floating gate by a process including depositing a thin high temperature oxide (HTO) film on the side surface of the conductive layer, and performing a rapid thermal oxidation (RTO) anneal. The thin HTO film may be deposited before or after performing the RTO anneal. The sidewall oxide formation process may provide an improved memory cell as compared with known prior art techniques, e.g., in terms of endurance and data retention.

Abstract: A change in electrical characteristics is suppressed and reliability in a semiconductor device using a transistor including an oxide semiconductor is improved. One feature resides in forming an oxide semiconductor film over an oxygen-introduced insulating film, and then forming the source and drain electrodes with an antioxidant film thereunder. Here, in the antioxidant film, the width of a region overlapping with the source and drain electrodes is longer than the width of a region not overlapping with them. The transistor formed as such has less defects in the channel region, which will improve reliability of the semiconductor device.

Abstract: In a pin diode, a new means for a soft recovery other than the means for the soft recovery using an anode layer with a low concentration and a local lifetime control is provided. A semiconductor device comprising a drift layer of a first conductivity type provided on a semiconductor substrate of a first conductivity type, a front-surface-side region of a second conductivity type provided on a front surface side of the drift layer, an insulating-film layer provided on a front surface side of the front-surface-side region with a thickness thinner than a natural oxide film, and a metal layer provided on a front surface side of the insulating-film layer is provided.

Abstract: A method for fabricating an anode-shorted field stop insulated gate bipolar transistor (IGBT) comprises selectively forming first and second semiconductor implant regions of opposite conductivity types. A field stop layer of a second conductivity type can be grown onto or implanted into the substrate. An epitaxial layer can be grown on the substrate or on the field stop layer. One or more insulated gate bipolar transistors (IGBT) component cells are formed within the epitaxial layer.

Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer of a first conductivity type, a second semiconductor layer of a second conductivity type, a third semiconductor layer of the first conductivity type, a fourth semiconductor layer of the second conductivity type, a first electrode connected to the second semiconductor layer and the fourth semiconductor layer, a second electrode facing the second semiconductor layer with an insulating film interposed, a fifth semiconductor layer of the second conductivity type, a sixth semiconductor layer of the first conductivity type, a seventh semiconductor layer of the second conductivity type, a third electrode connected to the fifth semiconductor layer and the seventh semiconductor layer, and a fourth electrode facing the fifth semiconductor layer with an insulating film interposed.

Abstract: In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source electrodes are formed in the wafer, on different sides of the gate region. A dielectric layer is formed over the gate region and over the passivation layer. Selective portions of the dielectric layer are removed by a plurality of etches so as to form one or more cavities between the gate region and the drain electrode. The one or more cavities have a plurality of steps at an increasing distance from the wafer moving from the gate region to the drain electrode. The cavity is then filled with conductive material to form a field plate coupled to the source electrode, extending over the gate region, and having a surface facing the wafer and having a plurality of steps.

Abstract: A high electron mobility field-effect transistor of normally-off type, including a first layer of GaN with P-type doping; a second layer of GaN with N-type doping formed on the first layer of GaN; a third layer of unintentionally doped GaN formed on the second layer of GaN; a semiconductor layer formed to form an electron gas layer; a cavity formed through the third layer of GaN, without reaching the bottom of the second layer of GaN; a gate including a conductive gate material and a gate insulation layer arranged in the cavity, the gate insulation layer electrically insulating the conductive gate material relative to the second and third layers of GaN.

Abstract: A nitride semiconductor device according to the present disclosure includes a substrate; a first nitride semiconductor layer which is formed on the substrate, and which has a C-plane as a main surface; a second nitride semiconductor layer which is formed on the first nitride semiconductor layer, and which has p-type conductivity; and a first opening which is formed in the second nitride semiconductor layer, and which reaches the first nitride semiconductor layer. The nitride semiconductor device further includes a third nitride semiconductor layer which is formed so as to cover the first opening in the second nitride semiconductor layer; a first electrode which is formed on the third nitride semiconductor layer so as to include a region of the first opening; and a second electrode which is formed on the rear surface of the substrate.

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor in the front surface, and a metallization structure arranged on the front surface. The metallization structure includes at least one cavity arranged in at least one dielectric layer.

Abstract: A pseudo-Schottky diode has an n-channel trench MOSFET which includes: a cathode, an anode, and located between the cathode and the anode, the following elements: a highly n+-doped silicon substrate; an n-doped epilayer having a trench extending into the n-doped epilayer from above; p-doped body regions provided above the n-doped epilayer and between the trenches. Highly n+-doped regions and highly p+-doped regions are provided on the upper surface of the p-doped body regions. Dielectric layers are provided on the side walls of the trench. The trench is filled with a first p-doped polysilicon layer, and the bottom of the trench is formed by a second p-doped layer which is in contact with the first p-doped polysilicon layer, and the second p-doped layer determines the breakdown voltage of the pseudo-Schottky diode.

Abstract: A transistor includes a vertical channel fin directly on a bottom source/drain region. A gate stack is formed on sidewalls of the vertical channel fin. Spacers are formed directly above the gate stack, one above each sidewall of the vertical channel fin. A top source/drain region is formed directly on a top surface of the vertical channel fin, between the spacers.

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.

Abstract: A replacement gate structure (i.e., functional gate structure) is formed and recessed to provide a capacitor cavity located above the recessed functional gate structure. A ferroelectric capacitor is formed in the capacitor cavity and includes a bottom electrode structure, a U-shaped ferroelectric material liner and a top electrode structure. The bottom electrode structure has a topmost surface that does not extend above the U-shaped ferroelectric material liner. A contact structure is formed above and in contact with the U-shaped ferroelectric material liner and the top electrode structure of the ferroelectric capacitor.

Abstract: A method of forming a strained channel for a field effect transistor, including forming a sacrificial layer on a substrate, forming a channel layer on the sacrificial layer, forming a stressor layer on the channel layer, wherein the stressor layer applies a stress to the channel layer, forming at least one etching trench by removing at least a portion of the stressor layer, channel layer, and sacrificial layer, wherein the etching trench exposes at least a portion of a sidewall of the sacrificial layer, and separates the stressor layer, channel layer, and sacrificial layer into two or more stressor islands, channel blocks, and sacrificial slabs, and removing the sacrificial slabs to release the channel blocks from the substrate using a selective etch, wherein the channel blocks adhere to the substrate surface.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. A structure includes a relaxed substrate including a bulk material, a strained layer directly on the relaxed substrate, where a strain of the strained layer is not induced by the relaxed substrate, and a transistor formed on the strained layer.

Abstract: A method of forming a semiconductor device is provided. At least one stacked structure is provided on a substrate. A first spacer material layer, a second spacer material layer, and a third spacer material layer are sequentially formed on the substrate and cover the stacked structure. The first, second, and third spacer material layers are etched to form a tri-layer spacer structure on the sidewall of the stacked structure. The tri-layer spacer structure includes, from one side of the stacked structure, a first spacer, a second spacer, and a third spacer, and a dielectric constant of the second spacer is less than each of a dielectric constant of the first spacer and a dielectric constant of the third spacer.

Abstract: A method of semiconductor fabrication includes forming a dielectric layer over a substrate. A dummy gate structure is formed on the dielectric layer, which defines a dummy gate dielectric region. A portion of the dielectric layer not included in the dummy gate dielectric region is etched to form a dielectric etch back region. A spacer element is formed on a portion of the dielectric etch back region, which abuts the dummy gate structure, and defines a spacer dielectric region A height of the dummy gate dielectric region is greater than the height of the spacer dielectric region. A recessed portion is formed in the substrate, over which a strained material is selectively grown to form a strained recessed region adjacent the spacer dielectric region. The dummy gate structure and the dummy gate dielectric region are removed. A gate electrode layer and a gate dielectric layer are formed.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. A topmost location of the epitaxy structure has an n-type impurity concentration lower than an n-type impurity concentration of a location of the epitaxy structure below the topmost location.

Abstract: A method of forming a semiconductor device includes forming a source/drain region and spacers on a substrate. The method further includes forming an etch stop layer on the spacers and the source/drain region and forming a gate structure between the spacers. The method further includes etching back the gate structure, etching back the spacers and the etch back layer, and forming a gate capping structure on the etched back gate structure, spacers, and etch stop layer.

Abstract: A thin-film transistor includes: an oxide semiconductor layer having a channel region, a source region, and a drain region; a gate insulating layer disposed above the oxide semiconductor layer; a gate electrode disposed at a position that is above the gate insulating layer and opposing the channel region; and a metal oxide layer stacked on the oxide semiconductor layer and in contact with the source region and the drain region. The metal oxide layer includes, as a main component, an oxide of a second metal whose bond dissociation energy with oxygen is greater than that of a first metal included in the oxide semiconductor layer. A first concentration ratio of oxygen to the second metal in an interface layer between the metal oxide layer and the oxide semiconductor layer is greater than a second concentration ratio of the same in a bulk layer of the metal oxide layer.

Abstract: A dual-gate TFT array substrate and manufacturing method thereof and a display device are provided. The manufacturing method includes: forming a common electrode and a top-gate electrode through one patterning process. The manufacturing method reduces the times of patterning process and simplifies the process flow.

Abstract: To provide a transistor with favorable electrical characteristics, a transistor with stable electrical characteristics, or a highly integrated semiconductor device. An electrode is provided over an oxide semiconductor layer A, the oxide semiconductor layer A and the electrode are covered with a layer C, and then heat treatment is performed; thus, oxidation of the electrode which is caused in the heat treatment is prevented. For the layer C, for example, an oxide semiconductor can be used. By covering a side surface of the oxide semiconductor layer A where a channel is formed with the layer C and the oxide semiconductor layer B, diffusion of impurities from the side surface of the oxide semiconductor layer A into the oxide semiconductor layer A is prevented.

Abstract: To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280° C. or higher and 400° C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150° C. to 400° C. inclusive, preferably 300° C. to 400° C. inclusive, further preferably 320° C. to 370° C. inclusive.

Abstract: A vertical JFET with a ladder termination may be made by a method using a limited number of masks. A first mask is used to form mesas and trenches in active cell and termination regions simultaneously. A mask-less self-aligned process is used to form silicide source and gate contacts. A second mask is used to open windows to the contacts. A third mask is used to pattern overlay metallization. An optional fourth mask is used to pattern passivation. Optionally the channel may be doped via angled implantation, and the width of the trenches and mesas in the active cell region may be varied from those in the termination region.

Abstract: This document discusses, among other things, a cap wafer and a via wafer configured to encapsulate a single proof-mass 3-axis gyroscope formed in an x-y plane of a device layer. The single proof-mass 3-axis gyroscope can include a main proof-mass section suspended about a single, central anchor, the main proof-mass section including a radial portion extending outward towards an edge of the 3-axis gyroscope sensor, a central suspension system configured to suspend the 3-axis gyroscope from the single, central anchor, and a drive electrode including a moving portion and a stationary portion, the moving portion coupled to the radial portion, wherein the drive electrode and the central suspension system are configured to oscillate the 3-axis gyroscope about a z-axis normal to the x-y plane at a drive frequency.

Abstract: A resistive memory element includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. When a bias voltage higher than a reset voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a reset state. When the bias voltage lower than a set voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a set state.

Abstract: A rectifying diode. The diode comprises a first conductor region and a second conductor region. The diode further comprises a diode conductive path between the first conductor region and the second conductor region. The path comprises a first semiconductor volume having a non-uniform distribution of ions and a second semiconductor volume having a uniform distribution of ions relative to the first semiconductor volume.

Abstract: An optical device manufacturing apparatus includes an encapsulating device for encapsulating an optical semiconductor element mounted on a substrate by a liquid resin R in a lens shape, and a curing device for curing the liquid resin R, wherein the encapsulating device includes a dispenser capable of vertically moving a nozzle for supplying the liquid resin R, and brings the tip of the nozzle close to the optical semiconductor element and then supplies the liquid resin R while raising the nozzle. According to this optical device manufacturing apparatus, an optical device having the desired optical properties can be obtained promptly and easily.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. In the method for fabricating the semiconductor device, at first, a dielectric layer is provided. Then, trenches are formed in the dielectric layer. Thereafter, the trenches are filled with spacer material to form a spacer structure in the dielectric layer for defining pixel regions. Then, lens structures are formed on the pixel regions. Each of the lens structures includes a first curved lens layer, a second curved lens layer and a curved color filter layer. The curved color filter layer is disposed on the second curved lens layer or between the first curved lens layer and the second curved lens layer.

Abstract: A Cu—Ga alloy sintered-compact sputtering target having a Ga concentration of 40 to 50 at % and Cu as the balance, wherein the sintered-compact sputtering target is characterized in that the relative density is 80% or higher, and the compositional deviation of the Ga concentration is within ±0.5 at % of the intended composition. A method of producing a Cu—Ga alloy sintered-compact sputtering target having a Ga concentration of 40 to 50 at % and Cu as the balance, wherein the method thereof is characterized in that Cu and Ga raw materials are melted and cooled/pulverized to produce a Cu—Ga alloy raw material powder, and the obtained material powder is further hot-pressed with a retention temperature being between the melting point of the mixed raw material powder and a temperature 15° C. lower than the melting point and with a pressure of 400 kgf/cm2 or more applied to the sintered mixed raw material powder.

Abstract: A semiconductor film, including: an assembly of semiconductor quantum dots containing a metal atom; and at least one ligand that is coordinated to the semiconductor quantum dots and that is selected from a ligand represented by Formula (A), a ligand represented by Formula (B), and a ligand represented by Formula (C): wherein, in Formula (A), X1 represents —SH, —NH2, or —OH; and each of A1 and B1 independently represents a hydrogen atom or a substituent having from 1 to 10 atoms; provided that when A1 and B1 are both hydrogen atoms, X1 represents —SH or —OH; in Formula (B), X2 represents —SH, —NH2, or —OH; and each of A2 and B2 independently represents a hydrogen atom or a substituent having from 1 to 10 atoms; and in Formula (C), A3 represents a hydrogen atom or a substituent having from 1 to 10 atoms.

Abstract: An artificial tree for generating hybrid energy is described, having an elevated structure connected to and supported by a base structure integral with the ground (G). The base structure including a central modular trunk integral with the ground and formed by vertically superimposed tubular members joined to one another.

Abstract: A solar cell apparatus in which contamination of solar cells is suppressed and a power generation quantity of the solar cells is maintained for a long period of time, even if the solar cell apparatus is disposed outside. The apparatus is provided with: a light transmitting plastic material; a light transmitting back sheet; a plurality of bifacial solar cells that are electrically connected to each other by means of interconnectors; and a transparent filled resin that surrounds the solar cells. The light transmitting plastic material has a curved surface, and is capable of constituting a hermetically closed space by being fixed to a disposition region of a body having the solar cell apparatus disposed thereon. The light transmitting back sheet, the solar cells, and the transparent filled resin are disposed in the hermetically closed space.

Abstract: The invention relates to a photovoltaic module for capturing and using solar radiation having as a backsheet a composition containing polyvinylidene fluoride. The polyvinylidene fluoride backsheet layer is exposed to the environment and provides chemical resistance, low water vapor transmission, electrical insulation, and UV light protection.

Abstract: One or more embodiments of the present invention are directed to a photovoltaic system. The system comprises photovoltaic cells, arranged side-by-side to form an array of photovoltaic cells. It further involves a cooling device, which comprises one or more layers, wherein the layers extend opposite to the array of photovoltaic cells and in thermal communication therewith, for cooling the cells, in operation. The one or more layers are structured such that a thermal resistance of the photovoltaic system varies across the array of photovoltaic cells, so as to remove heat from photovoltaic cells of the array with different heat removal rates, in operation. One or more embodiments of the present invention are further directed to related systems and methods for cooling such photovoltaic systems.

Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.

Abstract: Embodiments relate to the detection of semiconductor tampering with a light-sensitive circuit. A tamper detection device for an integrated circuit includes a light-sensitive circuit disposed within a package of an integrated circuit. The light-sensitive circuit closes in response to an exposure to a light source, indicating a tamper condition.