Abstract: A display device including a semiconductor element is provided.

Abstract: A laser crystallization apparatus includes a laser generating module configured to generate a laser beam, an optical module configured to guide the laser beam, an annealing chamber comprising a stage on which a target substrate comprising an amorphous thin film formed therein is disposed, the stage being movable along an X-axis direction and a Y-axis direction, and a tilt refractive lens configured to transform the laser beam having a cross-sectional area of a rectangle shape into a tilted laser beam having a cross-sectional area of a non-rectangular parallelogram shape and to irradiate the tilted laser beam perpendicular to the stage.

Abstract: A fabrication method of an array substrate, an array substrate, and a display device are provided, the array substrate comprising a pixel region, an alignment region and a pixel test region. The alignment region includes an alignment gate layer, an alignment insulating layer and an alignment pixel electrode layer sequentially formed on a substrate, the pixel test region includes a test gate layer, a test insulating layer and a test pixel electrode layer sequentially formed on the substrate, the alignment gate layer and the test gate layer are disposed on a same layer with the gate layer in the pixel region, the alignment pixel electrode layer and the test pixel electrode layer are disposed on a same layer with the pixel electrode layer in the pixel region.

Abstract: A photodiode array has a plurality of photodetector channels formed on an n-type substrate having an n-type semiconductor layer, with a light to be detected being incident to the photodetector channels. The array comprises: a p?-type semiconductor layer on the n-type semiconductor layer of the substrate; resistors is provided to each of the photodetector channels and is connected to a signal conductor at one end thereof; and an n-type separating part between the plurality of photodetector channels. The p?-type semiconductor layer forms a pn junction at the interface between the substrate, and comprises a plurality of multiplication regions for avalanche multiplication of carriers produced by the incidence of the light to be detected so that each of the multiplication regions corresponds to each of the photodetector channels.

Abstract: A semiconductor device includes a plurality of pixels arranged in a two-dimensional array, each pixel of the plurality of pixels including a photoelectric conversion film configured to photoelectrically convert light of a first wavelength and pass light of a second wavelength, and a photoelectric conversion unit configured to photoelectrically convert the light of the second wavelength. The semiconductor device may further include a charge storage unit configured to store charge received from the photoelectric conversion unit of each pixel in a pixel group, wherein the pixel group includes adjacent pixels among the plurality of pixels, a plurality of through electrodes, and a wiring layer coupled to the photoelectric conversion film of each pixel of the plurality of pixels by at least one through electrode of the plurality of through electrodes. The present technology can be applied to a solid-state imaging element.

Abstract: To obtain an imaging unit, a lens barrel, and a portable terminal which can effectively suppress spring-back of solid-state imaging elements, while facilitating height lowering thereof. An imaging unit includes: a solid-state imaging element; and an imaging lens for forming a subject image on a photoelectric conversion part of the solid-state imaging element. An imaging surface of the solid-state imaging element is curved in a manner that a peripheral side is inclined toward an object side relative to a screen center. The imaging lens constrains the solid-state imaging element to prevent a radius of curvature of the imaging surface from varying. Thus, field curvature, distortion aberration, and comatic aberration are appropriately corrected.

Abstract: Imaging sensors, imaging apparatuses, and methods of driving an image sensor are provided. An image sensor can include a semiconductor substrate with a photoelectric conversion element and a charge-conversion element. The sensor can further include a capacitance switch. A charge accumulation element is located adjacent the photoelectric conversion element. At least a portion of the charge accumulation element overlaps a charge accumulation region of the photoelectric conversion element. The charge accumulation element is selectively connected to the charge-voltage conversion element by the capacitance switch.

Abstract: A solid-state imaging device including an imaging area where a plurality of unit pixels are disposed to capture a color image, wherein each of the unit pixels includes: a plurality of photoelectric conversion portions; a plurality of transfer gates, each of which is disposed in each of the photoelectric conversion portions to transfer signal charges from the photoelectric conversion portion; and a floating diffusion to which the signal charges are transferred from the plurality of the photoelectric conversion portions by the plurality of the transfer gates, wherein the plurality of the photoelectric conversion portions receive light of the same color to generate the signal charges, and wherein the signal charges transferred from the plurality of the photoelectric conversion portions to the floating diffusion are added to be output as an electrical signal.

Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.

Abstract: Systems, devices, and methods for an extraordinary optical transmission (EOT) image capture system comprising optical components to capture light corresponding to an object, an EOT filter device to receive the captured light and transmit wavelengths of interest, and an image sensor to receive the wavelengths of interest and capture an image corresponding to the object. The EOT filter device comprising a first EOT film with thickness TEOT1 and including upper and lower surfaces and a plurality of apertures having a pitch P1, a second EOT film with thickness TEOT2 and including upper and lower surfaces and a plurality of apertures having a pitch P2; and an optical cavity disposed between the first and second EOT films, the optical cavity having a thickness TOC and a refractive index RIOC, wherein the EOT filter device transmits wavelengths of interest based on thicknesses TEOT1 and TEOT2, pitches P1 and P2, and thickness TOC.

Abstract: Various embodiments of a 3D high resolution X-ray sensor are described. In one aspect, an indirect X-ray sensor includes a silicon wafer that includes an array of photodiodes thereon with each of the photodiodes having a contact on a front side of the silicon wafer and self-aligned with a respective grid hole of an array of grid holes that are on a back side of the silicon wafer. Each of the grid holes is filled with a scintillator configured to convert beams of X-ray into light. The indirect X-ray sensor also includes one or more silicon dies with an array of photo-sensing circuits each of which including a contact at a top surface of the one or more silicon dies. Contact on each of the photodiodes is aligned and bonded to contact of a respective photo-sensing circuit of the array of photo-sensing circuits of the one or more silicon dies.

Abstract: A device including a substrate and an imaging element layer having a plurality of imaging elements is provided, where the imaging element layer is located between the substrate and a wiring layer having a plurality of wiring lines (41), and wiring lines of the wiring layer are arranged in pixel regions (Z) configured to receive light having a wavelength less than a predetermined wavelength (B, G). Accordingly, by more uniformly distributing the wiring layer throughout, it is possible to reduce an unevenness that occurs at a polishing film. Moreover, because wiring lines are not disposed in pixel regions (Z) configured to receive light having a wavelength greater than the predetermined wavelength (R), irregularities may be reduced.

Abstract: A first substrate includes a plurality of unit pixel regions. A deep trench isolation structure is disposed in the first substrate and isolates each of the plurality of the unit pixel regions from each other. Each of a plurality of photoelectric converters is disposed in one of the plurality of unit pixel regions. A plurality of micro lenses are disposed on the first substrate. A plurality of light splitters are disposed on the first substrate. Each of the plurality of light splitters is disposed between one of the plurality of micro lenses and one of the plurality of photoelectric converters. Each of a plurality of photoelectric-conversion-enhancing layers is disposed between one of the plurality of light splitters and one of the plurality of photoelectric converters.

Abstract: The invention relates to an optoelectronic device (50) including: a semiconductor substrate (14) doped with a first conductivity type; semiconductor contact pads (54) or a semiconductor layer, in contact with a surface of the substrate, doped with a second conductivity type opposite to the first type; conical or frusto-conical wired semiconductor elements (26), doped with the first conductivity type, each element being in contact with one of the contact pads or with the layer; light-emitting semiconductor portions (30), each portion at least partially covering one of the semiconductor elements; and a circuit (S) for polarizing the contact pads (54) or the layer. The contact pads or the layer are selected among: aluminum nitride, boron nitride, silicon carbide, magnesium nitride, gallium and magnesium nitride, or a combination of same and the nitride compounds thereof.

Abstract: A light-emitting device includes a substrate and a first light-emitting unit. The first light-emitting unit is disposed on the substrate, and includes a first semiconductor layer, a first light-emitting layer, and a second semiconductor layer. The first semiconductor layer is disposed on the substrate. The first light-emitting layer is disposed between the first semiconductor layer and the second semiconductor layer. The second semiconductor layer is disposed on the first light-emitting layer. The first semiconductor layer has a first sidewall and a second sidewall. A first angle is between the substrate and the first sidewall. A second angle is between the substrate and the second sidewall. The first angle is smaller than the second angle.

Abstract: A method of forming a 3D Hall effect sensor and the resulting device are provided. Embodiments include forming a shallow trench isolation (STI) region and a deep trench isolation (DTI) region in a substrate; forming a p-type well in the substrate surrounded by the STI region in top view; forming a first n-type well and a second n-type well surrounded by the p-type well and DTI region in top view; forming n-type dopant in the first n-type well and the second n-type well; and forming p-type dopant in the p-type well.

Abstract: The present invention is directed to an MTJ memory element, which comprises a magnetic fixed layer structure formed on top of a seed layer structure that includes a first seed layer and a second seed layer. The first seed layer includes one or more layers of nickel interleaved with one or more layers of a transition metal, which may be tantalum, titanium, or vanadium. The second seed layer is made of an alloy or compound comprising nickel and another transition metal, which may be chromium, tantalum, or titanium. The magnetic fixed layer structure has a first invariable magnetization direction substantially perpendicular to a layer plane thereof and includes layers of a first type material interleaved with layers of a second type material with at least one of the first and second type materials being magnetic. The first and second type materials may be cobalt and nickel, respectively.

Abstract: Methods of forming memory cells comprising phase change and/or chalcogenide materials are disclosed. In one aspect, the method includes providing a lower line stack extending in a first direction, the lower line stack comprising a sacrificial line over a lower conductive line. The method further includes forming a chalcogenide line extending in the first direction by selectively removing the sacrificial material of the sacrificial line and replacing the sacrificial line with a chalcogenide material.

Abstract: Three-dimensional memory structures that are configured to use area efficiently, and methods for providing three-dimensional memory structures that use area efficiently are provided. The vertical memory structure can include a number of bit line bits that is greater than a number of word line bits. In addition, the ratio of bit line bits to word line bits can be equal to a ratio of a first side a memory cell included in a memory array of the memory structure to a dimension of a second side of the memory cell.

Abstract: A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

Abstract: A semiconductor memory device according to an embodiment includes: a substrate having a surface extending in a first direction and a second direction intersecting the first direction; and a memory cell array disposed above the substrate, the memory cell array having: a first wiring line extending in the first direction; a second wiring line extending in a third direction intersecting the first and second directions; a third wiring line extending in the second direction; a memory cell including a first layer provided in an intersection region of the first wiring line and the second wiring line; and a select transistor including a channel layer provided between the second wiring line and the third wiring line, the first layer of the memory cell including a first material which is an oxide, and the channel layer of the select transistor including the first material.

Abstract: An organic light-emitting diode (OLED) display panel and an OLED display device are provided. The OLED display panel comprises a first substrate; a first electrode layer disposed on the first substrate and including a plurality of first electrodes; a first hole transport layer disposed on a surface of the first electrode layer far away from the first substrate, and including a plurality of hole transport units, wherein the plurality of hole transport units are arranged in correspondence with the plurality of first electrodes respectively; a plurality of light-emitting devices disposed on a surface of the first hole transport layer far away from the first electrode layer, wherein the plurality of the light-emitting devices are arranged in correspondence with the plurality of hole transport units respectively, and the hole transport units corresponding to the light-emitting devices of two different colors have different mobility; and a second electrode layer.

Abstract: An organic light-emitting display panel may prevent current leakage to an adjacent sub-pixel through a common layer having high hole mobility via the arrangement of an auxiliary pattern. The organic light-emitting display panel includes a bank provided in a non-emission portion so as to overlap an edge of a first electrode, a first common layer located on the first electrode in an emission portion and the bank in the non-emission portion, and an auxiliary pattern in contact with the first common layer on the bank.

Abstract: An organic EL display device provided with a display portion includes a flexible base material (substrate) in which the display portion is provided, an inorganic film provided on the base material, a display element portion that is provided on the inorganic film and is provided to form the display portion, and a suppression portion that is provided outside the display portion and suppresses progression of cracking that has occurred in a peripheral portion of the base material.

Abstract: A display device includes a display panel displaying an image. A light source unit provides light to the display panel. A cover member covers a portion of an upper surface of the display panel and a side surface of the display panel. The cover member exposes a display area of the display panel. A thermoelectric device is disposed between the cover member and the light source unit. The thermoelectric device contacts the cover member, and the thermoelectric device generates an electromotive force due to a difference in temperature between the light source unit and the cover member.

Abstract: An array substrate, a manufacturing method thereof and a display device are disclosed. The array substrate includes a substrate (10) and first thin-film transistors (TFTs) (21) and first electrodes (40) formed on the substrate (10). The first TFT (21) includes a gate electrode (200), an active layer (202), a source electrode (205) and a drain electrode (204). The first electrode (40) is electrically connected with the drain electrode (204) of the first TFT (21), at least covers an area of the active layer (202) of the first TFT, not overlapped with the source electrode (205) and the drain electrode (204), and can absorb ultraviolet (UV) light. The array substrate can solve the problem of reducing the display performance of the display device as the performances degrade and even fail due to UV irradiation of the TFTs.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a stretchable substrate, a unit pixel over the stretchable substrate and including a plurality of emission layers emitting red light, green light, and blue light separately, and a plurality of interconnection lines connected to a corner portion of the unit pixel. The unit pixel has at least four corners, and the interconnection lines are respectively connected to the four corners.

Abstract: Provided is a display device including a plurality of pixels at least one of which has a first transistor and a light-emitting element. The first transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, and a first terminal and a second terminal electrically connected to the semiconductor film. The second terminal is electrically connected to the light-emitting element. A region in which the first terminal overlaps with the gate electrode can be smaller than a region in which the second terminal overlaps with the gate electrode.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the OLED display includes a substrate having a main surface and a pixel provided over the main surface of the substrate and defined by a first region configured to display an image and a second region configured to transmit external light. The pixel includes a first electrode electrically provided in the first region, and a pixel defining layer provided in at least the first region, wherein the pixel defining layer has a first opening exposing a part of the first electrode and a second opening disposed in the second region. The pixel also includes a second electrode facing the first electrode and an intermediate layer disposed between the first and second electrodes and comprising an organic emission layer. The first capacitor at least partially overlaps the second opening along a direction perpendicular to the main surface.

Abstract: An organic light-emitting diode display device includes a first substrate that includes a display region with a plurality of pixels and a non-display region in a periphery of the display region, a first electrode disposed on the first substrate, a second electrode opposed to the first electrode, an organic light-emitting layer disposed between the first electrode and the second electrode, and at least one light sensing member disposed on a rear surface of the first substrate that overlaps the display region.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate, a plurality of OLEDs provided over the substrate, and a plurality of pixel circuits provided between the substrate and the OLEDs. Each of the pixel circuits comprises a plurality of transistors each including an active pattern electrically connected to the respective OLEDs. A shield layer overlaps the pixel circuits and the active patterns of the transistors in the depth dimension of the OLED display.

Abstract: An organic light-emitting display device and a method of fabricating the same are provided. The organic light-emitting display device includes a substrate having a plurality of trenches; a thin film transistor on the substrate; a light-emitting diode connected to the thin film transistor; an upper auxiliary electrode connected to one of an anode and a cathode of the light-emitting diode; and a lower auxiliary electrode in an auxiliary electrode trench among the plurality of trenches of the substrate and connected to the upper auxiliary electrode.

Abstract: An organic light-emitting diode (OLED) display and a method of manufacturing the same are disclosed. In one aspect, the OLED display includes a pixel disposed over a substrate, the pixel including a first region configured to generate an image and a second region configured to transmit external light. The pixel also includes a first transistor including a first active layer disposed in the first region, a first gate electrode disposed over the first active layer and insulated from the first active layer, and at least one electrode pattern disposed over the first gate electrode and electrically connected to the first active layer. A first insulation layer is disposed between the first gate electrode and the electrode pattern, the first insulation layer including a lower insulation layer and an upper insulation layer disposed over the lower insulation layer.

Abstract: A display apparatus includes a substrate including a display area displaying an image and a peripheral area outside the display area, a main wiring and an auxiliary wiring disposed in an identical layer in the peripheral area, the main wiring being disposed closer to the display area than the auxiliary wiring, a dam configured to cover at least a part of the main wiring, the auxiliary wiring being spaced apart from the dam, and a connecting wiring configured to connect the main wiring to the auxiliary wiring, and a thin-film encapsulation layer configured to seal the display area and the peripheral area.

Abstract: A semiconductor arrangement comprising; a die of III-V semiconductor material; a resistor element integrated in the die, the resistor element comprising a track defined by a first implant material in the III-V semiconductor material of the die, said track electrically isolated from substantially the remainder of the die by an isolation region that surrounds the track.

Abstract: Semiconductor devices and manufacturing method thereof are disclosed. The semiconductor device includes a substrate, a device layer, first and second conductive layers, first and second vias, and a MIM capacitor structure. The substrate includes active and passive regions. The device layer is in the active region. The first conductive layer is over the device layer. The second conductive layer is over the first conductive layer, wherein the first conductive layer is disposed between the device layer and the second conductive layer. The first via electrically connects the first and the second conductive layers. The MIM capacitor structure is between the first and the second conductive layers and in the passive region, and includes first and second electrodes and a capacitor dielectric layer therebetween. The capacitor dielectric layer includes Group IIIA-metal oxide or nitride. The second via electrically connects the second conductive layer and one of the first and second electrodes.

Abstract: A method of making a metal insulator metal (MIM) capacitor includes forming a copper bulk layer in a base layer, wherein the copper bulk layer includes a hillock extending from a top surface thereof. The method further includes depositing an etch stop layer over the base layer and the copper bulk layer. The method further includes depositing an oxide-based dielectric layer over the etch stop layer. The method further includes forming a capacitor over the oxide-based dielectric layer. The method further includes forming a contact extending through the oxide-based dielectric layer and the etch stop layer to contact the copper bulk layer, wherein the forming of the contact removes the hillock.

Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.

Abstract: To provide an optimal structure for electrically connecting an MOSFET region, a FWD region, and an IGBT region in parallel within one semiconductor chip by mitigating electric field concentration between a SJ column and a drift region, a semiconductor device is provided, the semiconductor device including: a semiconductor substrate: a super junction MOSFET having a repetitive structure of a first column and a second column; a parallel device having a drift region including second conductivity-type impurities, and being provided separately from the super junction MOSFET in the semiconductor substrate; and a boundary portion located between the super junction MOSFET and the parallel device in the semiconductor substrate, wherein the boundary portion extends from one main surface side to the other main surface side, and has at least one third column having first conductivity-type impurities, and the third column is shallower than the first column and the second column.

Abstract: A p+ collector layer is provided in a rear surface of a semiconductor substrate which will be an n? drift layer and an n+ field stop layer is provided in a region which is deeper than the p+ collector layer formed on the rear surface side. A front surface element structure is formed on the front surface of the semiconductor substrate and then protons are radiated to the rear surface of the semiconductor substrate at an acceleration voltage corresponding to the depth at which the n+ field stop layer is formed. A first annealing process is performed at an annealing temperature corresponding to the proton irradiation to change the protons into donors, thereby forming a field stop layer. Then, annealing is performed using annealing conditions suitable for the conditions of a plurality of proton irradiation processes to recover each crystal defect formed by each proton irradiation process.

Abstract: A method of forming a semiconductor device and resulting device. The method may form a first gate on a gate region of a starting substrate. The starting substrate includes alternating sacrificial layers and semiconductor layers above a buffer sacrificial layer located on a bulk substrate. The method may remove the starting substrate located between the gates. Etching the starting substrate creates a trench into the bulk substrate. The method may form an insulating layer on the inside of the trench. The method may form a masking layer over in the trench in the starting substrate covering a portion of the insulating layer, but below a top surface of the buffer layer. The method may remove the unmasked portion of the insulating layer. The method may form a source/drain in the trench. The method may remove the buffer sacrificial layer, and the sacrificial layers in the layered nanosheet.

Abstract: A semiconductor device may include a semiconductor layer, an insulation gate section, and a first conductivity-type semiconductor region; wherein the semiconductor layer may include a vertical drift region being of a second conductivity type and disposed at the one of main surfaces; a body region being of the first conductivity type, adjoining the vertical drift region, and disposed at the one of main surfaces; and a source region being of the second conductivity type, separated from the vertical drift region by the body region, and disposed at the one of main surfaces, wherein the insulation gate section is opposed to a portion of the body region which separates the vertical drift region and the source region; and the first conductivity-type semiconductor region is opposed to at least a part of a portion of the vertical drift region which is disposed at the one of main surfaces.

Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface. The silicon carbide semiconductor substrate has an amount of warpage of not less than ?100 ?m and not more than 100 ?m when a substrate temperature is a room temperature and has an amount of warpage of not less than ?1.5 mm and not more than 1.5 mm when the substrate temperature is 400° C.

Abstract: Techniques for device isolation for III-V semiconductor substrates are provided. In one aspect, a method of fabricating a III-V semiconductor device is provided. The method includes the steps of: providing a substrate having an indium phosphide (InP)-ready layer; forming an iron (Fe)-doped InP layer on the InP-ready layer; forming an epitaxial III-V semiconductor material layer on the Fe-doped InP layer; and patterning the epitaxial III-V semiconductor material layer to form one or more active areas of the device. A III-V semiconductor device is also provided.

Abstract: A system and method for a channel region is disclosed. An embodiment comprises a channel region with multiple bi-layers comprising alternating complementary materials such as layers of InAs and layers of GaSb. The alternating layers of complementary materials provide desirable band gap characteristics for the channel region as a whole that individual layers of material may not.

Abstract: A high electron mobility heterojunction transistor, including a first GaN layer; a second, p-doped GaN layer on top of the first layer, including magnesium as a p-type dopant, the concentration of which is at least equal to 5*1016 cm?3 and at most equal to 2*1018 cm?3, the thickness of the second GaN layer being between 20 and 50 nm; a third, n-doped GaN layer on top of the second GaN layer in order to form a depleted p-n junction; a fourth GaN layer, which is not intentionally doped, on top of the third GaN layer; a semiconductor layer plumb with the fourth GaN layer, which is not intentionally doped, in order to form an electron gas layer.

Abstract: A semiconductor device includes needle-shaped field plate structures extending from a first surface into transistor sections of a semiconductor portion in a transistor cell area. A grid structure separates the transistor sections from each other. The grid structure includes: stripe-shaped gate edge portions extending along one edge of the transistor sections, respectively; gate node portions wider than the gate edge portions and connecting two or more of the gate edge portions, respectively; and one or more connection sections of the semiconductor portion, wherein the one or more connection sections extend between neighboring transistor sections.

Abstract: A semiconductor device includes an active region in a shape of a fin extending in a first direction, the fin having source/drain regions spaced apart therein, gate structures crossing the fin between the source/drain regions, each including a gate electrode, a first contact structure in electrical contact with a first source/drain region, the first contact structure including a first lower contact and a first upper contact directly thereon, a second contact structure in electrical contact with a gate electrode of a gate structure, the second contact structure including a second lower contact and a second upper contact directly thereon, and a third contact structure in electrical contact with a gate electrode of a second gate structure and in electrical contact with a second source drain region, the third contact structure including a third lower contact and a third upper contact directly thereon.

Abstract: Approaches for LDMOS devices are provided. A method of forming a semiconductor structure includes forming a gate dielectric including a first portion having a first uniform thickness, a second portion having a second uniform thickness different than the first uniform thickness, and a transition portion having tapered surface extending from the first portion to the second portion. The gate dielectric is formed on a planar upper surface of a substrate. The tapered surface is at an acute angle relative to the upper surface of the substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.