Abstract: Embodiments of the present disclosure describe multi-device flexible systems on a chip (SOCs) and methods for making such SOCs. A multi-material stack may be processed sequentially to form multiple integrated circuit (IC) devices in a single flexible SOC. By forming the IC devices from a single stack, it is possible to form contacts for multiple devices through a single metallization process and for those contacts to be located in a common back-plane of the SOC. Stack layers may be ordered and processed according to processing temperature, such that higher temperature processes are performed earlier. In this manner, intervening layers of the stack may shield some stack layers from elevated processing temperatures associated with processing upper layers of the stack. Other embodiments may be described and/or claimed.

Abstract: A fan-out semiconductor package includes: a first connection member having a through-hole; a first component disposed in the through-hole; a second component disposed in the through-hole and attached to the first component; an encapsulant filling at least portions of spaces between walls of the through-hole and side surfaces of the first component and side surfaces of the second component; a second connection member disposed on the first connection member and the first component; and a third connection member disposed on the first connection member and the second component. A number of at least one of the first or second components is plural, the second and third connection members are connected to each other through the first connection member, and the first connection member includes a redistribution layer electrically connected to a redistribution layer of the second connection member and a redistribution layer of the third connection member.

Abstract: A semiconductor apparatus may include a package substrate, and a plurality of semiconductor chips. Wherein the package substrate and the semiconductor chips may be configured based on a load value of the semiconductor apparatus.

Abstract: A method is provided. The method includes providing a first wafer having a plurality of first dummy pads exposed along a first surface of the first wafer. The first dummy pads contact a first metallization layer of the first water. The method also includes providing a second wafer having a plurality of second dummy pads exposed along a first surface of the second wafer. The second dummy pads contact a second metallization layer of the second wafer. The method also includes bonding the first wafer to the second wafer in a manner that the first surface of the first wafer contacts the first surface of the second wafer and the plurality of first dummy pads are interleaved with the plurality of second dummy pads but do not contact the plurality of second dummy pads.

Abstract: Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy wafer, and forming a molding layer and a mold covering layer. A second semiconductor die may be stacked on the first semiconductor die and a photosensitive dielectric layer may be formed. Conductive vias penetrating the photosensitive dielectric layer may be plated.

Abstract: A semiconductor package includes a lower package including a lower package substrate, a lower semiconductor chip disposed on the lower package substrate, and a lower mold layer disposed on the lower package substrate, and an upper package disposed on the lower package. The upper package includes an upper package substrate and an upper semiconductor chip disposed on the upper package substrate. The semiconductor package additionally includes connection terminals disposed between the lower and upper package substrates. The connection terminals comprise outermost connection terminals and inner connection terminals. The inner connection terminals are disposed between the lower semiconductor chip and outermost connection terminals. The semiconductor package further includes a first under-fill layer disposed between the lower package substrate and the upper package substrate. At least one of the outermost connection terminals is disposed outside of the lower mold layer.

Abstract: A die device includes a die including an active layer; and an interconnect feature configured for electrical connection of the active layer, wherein the interconnect feature is in contact with a substrate in the die; and a bump, independent of the die, configured for electrical connection of the active layer.

Abstract: An optoelectronic component for mixing electromagnetic radiation having different wavelengths, for example, for the far field is disclosed. In an embodiment the optoelectronic component includes a carrier, at least one first semiconductor chip arranged on the carrier and having a first radiation exit surface for emitting electromagnetic radiation in a first spectral range and at least one second semiconductor chip arranged on the carrier and having a second radiation exit surface for emitting electromagnetic radiation in a second spectral range, wherein a diffusing layer is arranged on the first and second radiation exit surfaces of the semiconductor chips that face away from the carrier and wherein a reflecting layer is arranged between the first semiconductor chip and the second semiconductor chip, the first and second radiation exit surfaces being free from the reflecting layer at least in regions.

Abstract: Solid state lighting (SSL) devices and methods of manufacturing such devices. One embodiment of an SSL device comprises a support and an emitter array having a plurality of SSL emitters carried by the support. The emitter array has a central region and a peripheral region outward from the central region. Individual SSL emitters in both the central and the peripheral regions have a primary emission direction along which an intensity of light from the SSL emitters is highest, and the primary emission direction of the SSL emitters in the central region is at least substantially the same direction as the primary emission direction of the SSL emitters in the peripheral region. Additionally, a first coverage area ratio of the SSL emitters in the central region is different than a second coverage area ratio of the SSL emitters in the peripheral region.

Abstract: The present disclosure provides a semiconductor package, including a first layer, a second layer, and a conductive array. The first layer includes a packaged die having a carrier surface and a molding surface, and a first die structure in proximity to the carrier surface. An active region of the first die structure is electrically coupled to the packaged die through a solder. The second layer includes a second die structure, the second die structure being connected to the active region of the first die structure by a first redistributed layer (RDL). The conductive array is connected to an active region of the second die structure by a second RDL. The present disclosure also provides a method for manufacturing the aforesaid semiconductor package.

Abstract: A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.

Abstract: A display apparatus includes a light emitting diode part and a thin film (TFT) panel configured to drive the light emitting diode part. The light emitting diode part includes a transparent support substrate, a plurality of light emitting diodes, a plurality of phosphor layers disposed on the support substrate covering at a first portion of the plurality of light emitting diodes and configured to emit light through a conversion of introduced light. Another display apparatus includes a light emitting diode part including a plurality of light emitting diodes and a TFT panel configured to drive the light emitting diode part. The TFT panel includes a panel substrate including a TFT driving circuit and a plurality of grooves formed on the panel substrate. The TFT panel also includes a plurality of phosphor layers the plurality of grooves and configured to emit light through wavelength conversion of introduced light.

Abstract: First and second integrated devices each have an optical component and a plurality of interconnect structures disposed one edge thereon. The first edge surface of the second integrated device is positioned contiguous to the first edge surface of the first integrated device. The interconnect structures disposed on the first integrated device are in physical contact with the interconnect structures disposed on the edge surface of the second integrated device so as to provide alignment for conveying at least one signal between the optical components on the first and second integrated devices.

Abstract: An integrated circuit includes a substrate and a first set of functional cell units formed over the substrate. Each of the functional cell units includes a pair of functional cells that have different threshold voltages and a filler cell between the functional cells thereof. A number of the functional cell units in the first set is equal to or greater than a number of a second set of functional cell units, each of which includes a pair of functional cells that have different threshold voltages and that abut against each other. As such, a leakage current of the integrated circuit is reduced.

Abstract: A semiconductor device for driving a load includes: a protection circuit configured to be connected to the load, the protection circuit including a protection diode, a diode-connected unipolar protection element, and a diode-connected bipolar protection element, all of which are connected in parallel so that when connected to the load, the protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in parallel to the load; and a switching circuit that is connected in series to the protection circuit and that performs a switching operation so as to drive the load. The protection diode, the diode-connected unipolar protection element, and the diode-connected bipolar protection element are connected in such a polarity that each is reverse-biased when the switching circuit is turned ON, and consume a discharge current resulting from a counter-electromotive force from the load when the switching circuit is turned OFF.

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

Abstract: A power converter includes a semiconductor element disposed on a substrate, a thermistor element for detecting the temperature of the substrate, the thermistor element being disposed on the substrate, a current detection resistor having one end connected to a ground side node and another end that is grounded, a first voltage detection unit configured to detect a first potential at the other end of the current detection resistor and a second potential at the ground side node, and output a first detection signal, a control unit configured to control the semiconductor element based on the first detection signal, a temperature detection resistor having one end that is connected to a reference potential and another end that is connected to a detection node, and a temperature detection unit configured to detect a temperature based on a third potential at the detection node, and output a temperature information signal.

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

Abstract: The present disclosure relates to an integrated circuit (IC) and a method of formation. In some embodiments, a first oxide component is disposed on a substrate within a medium voltage region. A first high-k dielectric component is disposed on the substrate within a low voltage region and a second high-k dielectric component disposed on the first oxide component within the medium voltage region. A first gate electrode separates from the substrate by the first high-k dielectric component. A second gate electrode separates from the substrate by the first oxide component and the second high-k dielectric component.

Abstract: A semiconductor device comprising: a die-source-terminal, a die-drain-terminal and a die-gate-terminal; a semiconductor-die; an insulated-gate-depletion-mode-transistor provided on the semiconductor-die, the insulated-gate-depletion-mode-transistor comprising a depletion-source-terminal, a depletion-drain-terminal and a depletion-gate-terminal, wherein the depletion-drain-terminal is coupled to the die-drain-terminal and the depletion-gate-terminal is coupled to the die-source-terminal; an enhancement-mode-transistor comprising an enhancement-source-terminal, an enhancement-drain-terminal and an enhancement-gate-terminal, wherein the enhancement-source-terminal is coupled to the die-source-terminal, the enhancement-gate-terminal is coupled to the die-gate-terminal and the enhancement-drain-terminal is coupled to the depletion-source-terminal; and a clamp-circuit coupled between the depletion-source-terminal and the depletion-gate-terminal.

Abstract: A method includes forming a first polysilicon structure over a first portion of a substrate. A second polysilicon structure is formed over a second portion of the substrate. Two spacers are formed on opposite sidewalls of the second polysilicon structure. A layer of protective material is formed to cover the first and second portions of the substrate. The layer of protective material has a first thickness over the second polysilicon structure and a second thickness over the two spacers. The first thickness is equal to or greater than 500 ?, and the second thickness is equal to or less than 110% of the first thickness. A patterned photo resist layer is formed to cover a first portion of the layer of protective material that covers the first portion of the substrate. The second portion of the layer of protective material is removed.

Abstract: Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same.

Abstract: The disclosure concerns an integrated circuit comprising: a plurality of circuit domains, each circuit domain comprising: a plurality of transistor devices positioned over p-type and n-type wells, the transistor devices defining one or more data paths of the circuit domain; a monitoring circuit adapted to detect when the slack time of at least one of the data paths in the circuit domain falls below a threshold level and to generate an output signal on an output line based on said detection; and a biasing circuit adapted to modify a biasing voltage of the n-type and/or p-type well of the circuit domain.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate, and a source/drain region in the substrate. Moreover, the semiconductor device includes a gate structure in a recess in the substrate. The gate structure includes a liner that includes a first portion and a second portion on the first portion. The second portion is closer, than the first portion, to the source/drain region. The second portion includes a metal alloy. Methods of forming a semiconductor device are also provided.

Abstract: An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

Abstract: A semiconductor device that can evacuate the information in a DRAM automatically at the time of power supply cutoff is provided. A memory cell includes a DRAM cell that holds information at a storage node, a nonvolatile memory cell, and a transistor. The nonvolatile memory cell holds information by use of the first threshold voltage as an erase state and the second threshold voltage as a write state, and shifts to the write state by a write voltage being applied in the erase state. The transistor selects whether or not to apply the write voltage (voltage of a write voltage line) to the nonvolatile memory cell according to the voltage level at the storage node of the DRAM cell.

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.

Abstract: An embodiment is an integrated circuit structure including a static random access memory (SRAM) cell having a first number of semiconductor fins, the SRAM cell having a first boundary and a second boundary parallel to each other, and a third boundary and a fourth boundary parallel to each other, the SRAM cell having a first cell height as measured from the third boundary to the fourth boundary, and a logic cell having the first number of semiconductor fins and the first cell height.

Abstract: In a method of manufacturing a semiconductor device, a first FinFET including a first fin structure, a first gate electrode structure disposed over the first fin structure and a first source/drain region is formed. A second FinFET including one second fin structure, a second gate electrode structure disposed over the second fin structure and a second source/drain region is formed. A first epitaxial layer is formed on the first fin structure in the first source/drain region, and a second epitaxial layer is formed on the second fin structure in the second source/drain region. A width of the first fin structure is smaller than a width of the second fin structure.

Abstract: The present invention proposes a static random-access memory device (SRAM). The static random-access memory device is composed of two P-channel gates of loading transistor, two N-channel gates of driving transistor and two N-channel gates of accessing transistor in a memory cell. A dummy gate is disposed adjacent to the N-channel gate of accessing transistor with a bit line node disposed therebetween, wherein the dummy gate is electrically connected to a ground voltage through a metal layer.

Abstract: An SRAM cell includes first through fifth active regions. The first through fourth active regions comprise channel regions and source/drain (S/D) regions of first through fourth transistors respectively, and the fifth active region comprises channel regions and S/D regions of fifth and sixth transistors. The SRAM cell further includes first through sixth gates configured to engage the channel regions of the first through sixth transistors. The first and second gates are electrically connected. The third and fourth gates are electrically connected. The SRAM cell further includes first conductive features that electrically connect one of the S/D regions of the first transistor, one of the S/D regions of the second transistor, and the third gate. The SRAM cell further includes second conductive features that electrically connect the second gate, one of the S/D regions of the third transistor, one of the S/D regions of the fourth transistor, and the fifth gate.

Abstract: A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein the fin structures include a plurality of active fins and a plurality of dummy fins, each PG (pass-gate) FinFET shares at least one of the active fins with a PD (pull-down) FinFET, and at least one dummy fin is disposed between the two active fins having two adjacent PU (pull-up) FinFETs thereover in a static random-access memory cell. At least a part of the dummy fins are removed. The present invention also provides a static random-access memory (SRAM) cell array formed by said method.

Abstract: The present disclosure relates a method for manufacturing an integrated circuit. In some embodiments, a semiconductor substrate is provided and made up of a memory array region and a boundary region surrounding the memory array region. A hard mask layer is formed over the memory array region and the boundary region. The hard mask layer is patterned to form a boundary hard mask having one or more slots to expose some portions of the boundary region while the remaining regions of the boundary region are covered by the boundary hard mask. A floating gate layer is formed within the memory array region and extending over the hard mask layer. Then, a planarization is performed to reduce a height of the floating gate layer and form a plurality of floating gates.

Abstract: A semiconductor memory device includes a substrate having a memory region and a peripheral region that are adjacent to each other, and a plurality of insulating layers and a plurality of wiring layers that are alternately formed on the memory region and the peripheral region of the substrate. On the memory region, the insulating layers and the wiring layers are alternately formed along a thickness direction of the memory device. On the peripheral region, first portions of the insulating layers and first portions of the wiring layers are alternately formed along the thickness direction and second portions of the insulating layers and second portions of the wiring layers are alternately formed along a lateral direction. A width of the second portion of each of the wiring layers in the lateral direction is greater than a thickness of the first portion of the wiring layer.

Abstract: Various apparatuses, including three-dimensional (3D) memory devices and systems including the same, are described herein. In one embodiment, a 3D memory device can include at least two sources; at least two memory arrays respectively formed over and coupled to the at least two sources; and a source conductor electrically respectively coupled to the at least two sources using source contacts adjacent one or more edges of the source. Each of the at least two memory arrays can include memory cells, control gates, and data lines. There is no data line between an edge of a source and the source contacts adjacent the edge.

Abstract: A semiconductor device includes a substrate, at least one split gate memory device, and at least one logic device. The split gate memory device is disposed on the substrate. The logic device is disposed on the substrate. A select gate or a main gate of the split gate memory device and a logic gate of the logic device are both made of metal, and the other gate of the split gate memory device is made of nonmetal.

Abstract: A memory device includes memory includes a multi-layers stack includes a plurality of insulating layers and a plurality conductive layers alternatively stacked on a semiconductor device, a plurality of memory cells formed on the conductive layers, a contact plug passing through the insulating layers and the conductive layers, and a dielectric layer including a plurality of extending parts each of which is inserted between each adjacent two ones of the insulating layers to isolate the conductive layer from the contact plug, wherein any one of the extending parts that has a shorter distance departed from the semiconductor substrate has a size substantially greater than a size of the others that has a longer distance departed from the semiconductor substrate.

Abstract: A semiconductor device includes interlayer insulating layers and conductive patterns alternately stacked over a pipe gate, a first slit and a second slit penetrating the interlayer insulating layers and the conductive patterns and crossing each other, an etch stop pad groove overlapping an intersection of the first slit and the second slit, arranged in the pipe gate, and connected to the first slit or the second slit, and slit insulating layers filling the first slit, the second slit and the etch stop pad groove.

Abstract: According to one embodiment, a semiconductor device includes a substrate and a multilayer body provided on the substrate. The multilayer body has electrode films and insulating films. The electrode films contain silicon, the insulating films contain silicon oxide. Each of the electrode films and each of the insulating films are alternately stacked. A hole is formed in the multilayer body, and the hole vertically extends in the multilayer body. The electrode films include a first electrode film and a second electrode film located below the first electrode film. Carbon concentration of the first electrode film is higher than carbon concentration of the second electrode film.

Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.

Abstract: According to one embodiment, a semiconductor device includes: a substrate; a stacked body; a columnar portion; and a plate portion. The substrate has a major surface. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The columnar portion includes a semiconductor body and a memory film. The memory film includes a charge storage portion. The plate portion is provided in the stacked body. The plate portion extends along the stacking direction of the stacked body and a major surface direction of the substrate. The plate portion includes a plate conductor and a sidewall insulating film. The sidewall insulating film provided between the plate conductor and the stacked body. The stacked body includes an air gap. The air gap is provided between the sidewall insulating film and the electrode layer.

Abstract: Provided herein is a semiconductor device including: a channel layer; a data storage layer surrounding the channel layer and extending along the channel layer; interlayer insulating layers surrounding the data storage layer and stacked along the channel layer, wherein the interlayer insulating layers are spaced apart from each other, wherein a conductive area is disposed between the interlayer insulating layers; a conductive pattern disposed in the conductive area and surrounding the data storage layer; buffer patterns disposed between the interlayer insulating layers and the data storage layer and surrounding the data storage layer, wherein each of the buffer patterns includes a densified area, wherein the buffer patterns are separated from each other by the conductive area; and a blocking insulating pattern disposed between the conductive pattern and the data storage layer and surrounding the data storage layer.

Abstract: A semiconductor device includes bit lines extending along a first direction, the bit lines being arranged along a second direction intersecting the first direction, a plurality of channel layers disposed under the bit lines, the plurality of channel layers extending in a third direction perpendicular to a plane extending along the first and second directions and spaced apart along the second direction, so that each channel layer is at least partially overlapped with at least two of the bit lines, and a contact plug extending, from the channel layer, toward one of the bit lines overlapped with the channel layer.

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

Abstract: A thin film transistor substrate includes: a gate insulating film that covers a gate electrode and a common electrode; a transparent oxide film selectively disposed on the gate insulating film; a source electrode and a drain electrode that are spaced from each other on the transparent oxide film; and a light transmissive pixel electrode electrically connected to the drain electrode. The transparent oxide film includes a conductive region and a semiconductor region. The conductive region is disposed in a lower portion of the source electrode and the drain electrode and disposed in a portion that continues from the lower portion of the drain electrode, extends to part of an upper portion of the common electrode, and forms the pixel electrode. The semiconductor region is disposed in a portion corresponding to a lower layer in a region between the source electrode and the drain electrode.

Abstract: To provide a semiconductor device with excellent electrical characteristics or a semiconductor device with stable electrical characteristics. A semiconductor device includes a first transistor, a second transistor, a first insulator, a second insulator, a first wiring, and a first plug. The first transistor includes silicon. The second transistor includes an oxide semiconductor. The first insulator is located over the first transistor. The second insulator is located over the first insulator. The second transistor is located over the second insulator. The first wiring is located over the second insulator and the first plug. The first transistor and the second transistor are electrically connected to each other through the first wiring and the first plug. The first wiring has low hydrogen permeability. The hydrogen permeability of the second insulator is lower than the hydrogen permeability of the first insulator.

Abstract: An array substrate, a manufacturing method of the array substrate and a display device including the array substrate are disclosed. The array substrate includes a substrate (1), a common electrode layer (401) located on the substrate (1) and a conductive layer (2) provided on a surface of the substrate (1), the conductive layer (2) and the common electrode layer (401) are electrically connected in parallel. The common electrode and the conductive layer are formed into a parallel structure, so that the resistance can be decreased, and in turn, crosstalk, greenish and other phenomenon of the array substrate are reduced, thereby promoting the picture quality of the display device.

Abstract: A semiconductor device that occupies a small area and has a high degree of integration is provided. The semiconductor device includes a first insulating layer, a conductive layer, and a second insulating layer. The conductive layer is between the first insulating layer and the second insulating layer. The first insulating layer, the conductive layer, and the second insulating layer overlap with each other in a region. A contact plug penetrates the first insulating layer, the conductive layer, and the second insulating layer. In a depth direction from the second insulating layer to the first insulating layer, a diameter of the contact plug changes to a smaller value at an interface between the second insulating layer and the conductive layer.

Abstract: A display apparatus includes a substrate, a circuit, and a pixel electrode. The substrate includes a display area and a peripheral area outside the display area. The circuit is disposed in the display area. The circuit includes a plurality of conductive layers, and each conductive layer contacts a corresponding inorganic layer arranged directly below the each conductive layer. The pixel electrode is arranged over the circuit and is electrically connected to at least one of the conductive layers.

Abstract: In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.