Abstract: An electronic memory array includes a plurality of memory domains, a current controller, and a selector device. Each memory domain includes a plurality of bit cells. The current controller includes a current controller output electrically connectable to said plurality of memory domains and is configured to control a bit cell current. The selector device is electrically connected to the current controller and the plurality of memory domains. The selector device is configured to selectively electrically connect the current controller output to only a select one of said memory domains, such that the current controller controls only the bit cell current of the bit cells of the select memory domain.

Abstract: An apparatus includes an interface circuit coupled to an electronic device. The interface circuit provides source synchronous communication with the electronic device using a strobe signal. The interface circuit is configured to gate the strobe signal in order to successfully communicate with the electronic device.

Abstract: Memory array, system and method for storing data. The memory array has a flash memory array, a random access memory array coupled to the flash memory and configured to receive the data, a memory management module and a data bus. The memory management module is coupled to the random access memory array and to the flash memory array, the memory management module being configured to transfer at least a portion of the data stored in the random access memory array to the flash memory array. The data bus is coupled to the flash memory array and configured to output at least a portion of the data originally stored in the random access memory array from the flash memory array.

Abstract: Techniques for writing magnetic random access memory (MRAM) using the spin hall effect with a self-reference read are provided. In one aspect, an MRAM device is provided. The MRAM device includes: a plurality of first spin hall wires oriented orthogonal to a plurality of second spin hall wires; a plurality of magnetic memory cells configured in an array between the first spin hall wires and the second spin hall wires; and a plurality of transistors connected to the magnetic memory cells by the first spin hall wires. Methods of operating an MRAM device are also provided.

Abstract: Disclosed is a ferroelectric material and methods for its use in capacitors that includes a polymer blend of at least two polymers, wherein the first polymer is a ferroelectric polymer and the second polymer has a low dielectric constant.

Abstract: A refresh command is communicated to a memory device to initiate an interruptible refresh which contains multiple segment refreshes separated by interrupt boundaries. A command is communicated to the memory device before execution of a segment refresh and the segment refresh is delayed at an interrupt boundary. Alternatively, a first number of commands in a queue is determined. A first number of segment refreshes to execute is determined based on the first number of commands. The first number of segment refreshes to execute is communicated to the memory device to cause execution of the first number of segment refreshes. A second number of commands in the queue is determined. A second number of segment refreshes to execute is determined based on the second number of commands. The second number of segment refreshes to execute is communicated to the memory device to cause execution of the second number of segment refreshes.

Abstract: A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.

Abstract: A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.

Abstract: According to one embodiment, a memory device includes a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first memory cell and the second memory cell; a first circuit configured to control a connection between the first bit line and a first node; and a second circuit configured to control a connection between the second bit line and the first node.

Abstract: The present invention provides a data storage device including a flash memory and a controller. The controller checks whether a first number of a first page in the flash memory is greater than a predetermined threshold when the data storage device resumes operation after a power-off event, and stops writing data into a first TLC block when the first number of the first page is greater than the predetermined threshold, wherein the first TLC block was undergoing a first write operation which was unfinished when the power-off event occurred, and the first page was the last one being written in the first TLC block.

Abstract: A memory cell array is configured to have a plurality of memory cells arranged in a matrix, each of the memory cells being connected to a word line and a bit line and being capable of storing n values (n is a natural number equal to or larger than 3). A control circuit controls the potentials of the word line and bit line according to input data and writes data into a memory cell. The control circuit writes data into the memory cell to a k-valued threshold voltage (k<=n) in a write operation, precharges the bit line once, and then changes the potential of the word line an i number of times to verify whether the memory cell has reached an i-valued (i<=k) threshold voltage.

Abstract: A nonvolatile memory device includes: resistive memory cells each of which takes either a variable state or an initial state, the resistive memory cells including at least one resistive memory cell in the initial state; and a read circuit that includes a resistance detection circuit that obtains resistance value information of the at least one resistive memory cell, and a data generation circuit that generates digital data corresponding to the resistance value information. The resistance detection circuit applies a second read voltage to the at least one resistive memory cell to obtain the resistance value information. The second read voltage is larger than a first read voltage and smaller than a voltage of a forming pulse that is an electrical stress for changing from the initial state to the variable state. The first read voltage is for reading a resistive memory cell in the variable state.

Abstract: In one example, a current limited device is coupled between a source line of a memory cell array and a supply voltage, and configured to operate in a constant current mode during an access operation of a memory cell.

Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a non-volatile memory device may be placed in any one of multiple memory states in a write operation by controlling a current and a voltage applied to terminals of the non-volatile memory device. For example, a write operation may apply a programming signal across terminals of non-volatile memory device having a particular current and a particular voltage for placing the non-volatile memory device in a particular memory state.

Abstract: A configuration bit for a switching block routing array comprising a non-volatile memory cell is provided. By way of example, the configuration bit and switching block routing array can be utilized for a field programmable gate array, or other suitable circuit(s), integrated circuit(s), application specific integrated circuit(s), electronic device or the like. The configuration bit can comprise a switch that selectively connects or disconnects a node of the switching block routing array. A non-volatile memory cell connected to the switch can be utilized to activate or deactivate the switch. In one or more embodiments, the non-volatile memory cell can comprise a volatile resistance switching device connected in serial to a gate node of the switch, configured to trap charge at the gate node to activate the switch, or release the charge at the gate node to deactivate the switch.

Abstract: Nanotube films and articles and methods of making the same are disclosed. A conductive article or a substrate comprises at least two unaligned nanotubes extending substantially parallel to the substrate and each contacting end points of the article but each unaligned relative to the other, the nanotubes providing a conductive pathway within a predefined space.

Abstract: A memory structure, includes (a) active columns of polysilicon formed above a semiconductor substrate, each active column extending vertically from the substrate and including a first heavily doped region, a second heavily doped region, and one or more lightly doped regions each adjacent both the first and second heavily doped region, wherein the active columns are arranged in a two-dimensional array extending in second and third directions parallel to the planar surface of the semiconductor substrate; (b) charge-trapping material provided over one or more surfaces of each active column; and (c) conductors each extending lengthwise along the third direction.

Abstract: Various embodiments comprise apparatuses such as those having a block of memory divided into sub-blocks that share a common data line. Each of the sub-blocks of the block of memory corresponds to a respective one of a number of segmented sources. Each of the segmented sources is electrically isolated from the other segmented sources of the block of memory. Additional apparatuses and methods of operation are described.

Abstract: A memory system of an embodiment includes a memory device including a first set of cell transistors and a second set of cell transistors; and a controller configured to transmit to the memory device a first instruction and transmit to the memory device a second instruction after reception of a first request without receiving the first request again. The first instruction instructs parallel reads from the first and second sets of cell transistors, and the second instruction instructs a read from the first set of cell transistors.

Abstract: A power supply circuit and a semiconductor storage device that can achieve low power consumption of the power supply circuit that includes a charge pump circuit are provided. The semiconductor storage device includes a charge pump unit which generates and outputs a boosted voltage by boosting a source voltage, a voltage monitoring unit that performs comparison and determination on magnitudes of a divided voltage obtained by dividing the boosted voltage and a predetermined reference voltage, a charge pump control unit that causes the charge pump unit to operate when the divided voltage is equal to or lower than the reference voltage and causes the charge pump unit to stop when the divided voltage is higher than the reference voltage based on a result of the comparison and determination, and a voltage monitoring control unit that causes the voltage monitoring unit to intermittently stop.

Abstract: A non-volatile memory includes a power switch circuit and a non-volatile cell array. The power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first transistor receive a first supply voltage and a second supply voltage, respectively. A second source/drain terminal and a body terminal of the first transistor are connected with a node z. A first source/drain terminal and a gate terminal of the second transistor receive the second supply voltage and the first supply voltage, respectively. A second source/drain terminal and a body terminal of the second transistor are connected with the node z. The current source is connected between a bias voltage and the node z. A power terminal of the non-volatile cell is connected with the node z for receiving an output signal.

Abstract: A semiconductor device including a voltage generation circuit, and voltage generation circuit generates a required voltage according to internal data requested in response to an operation are provided. The voltage generating circuit includes a plurality of registers A-1, B-1, C-1, D-1, voltage generating blocks A-2, B-2, C-2 and a voltage switch. The registers A-1, B-1, C-1, D-1 hold data provided from control logic. The voltage generating blocks A-2, B-2, C-2 generate voltage based on voltage control data held by the registers A-1, B-1, C-1. The voltage switch selects voltages based on selection control data held by the register D-1. The connecting element includes signal lines for sequentially transmitting the voltage control data or the selection control data, signal lines for sequentially transmitting a clock signal CLK and signal lines for controlling output of data held by the registers.

Abstract: Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition.

Abstract: A data storage device includes a nonvolatile memory device; a voltage detector suitable for detecting an operating voltage of the nonvolatile memory device; and a control unit suitable for making a first determination whether the operating voltage is dropped intentionally or unintentionally based on a first reference time and an elapsed time for which the operating voltage decreases from a first reference voltage to a second reference voltage.

Abstract: A shift register and a display apparatus are provided. The shift register includes a pre-charge unit, a pull-up unit, a first pull-down unit and a second pull-down unit. The pre-charge unit receives first and second input signals, and outputs a pre-charge signal via a first node. The pull-up unit receives a pre-charge signal and a clock signal, and outputs a scanning signal via a second node. The first pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to pull-down the scanning signal to a reference voltage level. The second pull-down unit receives the pre-charge signal, first and second pull-down control signals, and controls whether to keep the scanning signal at the reference voltage level. The duty cycle of the clock signal is less than 50 percent.

Abstract: A shift register, a method for driving a shift register, a gate driver on array (GOA) circuit and a display device are provided. It relates to the field of display technology and solves nonuniform display due to inadequate gate signal in large-sized GOA display products. The shift register for the GOA circuit includes a pulling up (PU) node, a capacitor and an output control module. The output control module comprises a first thin film transistor. A control end of the first thin film transistor is connected to a first end of the capacitor via the PU node, a first clock signal is input to a first end of the first thin film transistor, and a second end of the first thin film transistor is connected to a second end of the capacitor. The shift register further includes a pre-charging module, used to receive a signal from the PU node and output, before the shift register outputs a valid voltage, a pre-charging voltage having an identical polarity to the valid voltage to an output terminal of the shift register.

Abstract: The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.

Abstract: A shift register unit comprises an input subcircuit for a first node to be a first level when a scan pulse is of the first level, an output subcircuit for driving an output terminal to be a first clock signal level when the first node is at the first level, a second node control subcircuit for connecting the second node with a second level when either of the scan pulse and the output terminal is of the first level, and connecting the second node with the first level when each of the scan pulse and the output signal is of the second level, a first reset subcircuit for driving the first node to be the second level when the second node is at the first level, and a second reset subcircuit for driving the output signal to be the second level when the second node is at the first level.

Abstract: A device for the storage and/or processing of quantum information comprises: a body (6), formed from a material having negligible net nuclear or electronic magnetic field; a set of data entities (4) embedded in said body, each having a plurality of magnetic field states; a set of probes (2), offset from the body, arranged to acquire internal phase shifts due to the magnetic fields of said data entities; wherein the probes (2) are each arranged to move relative to a plurality of data entities (4) in order that each probe (2) acquires an internal phase shift from the plurality of data entities (4); and means for reading each probe (2), thereby establishing a parity of the plurality of data entities (4).

Abstract: Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

Abstract: A capacitance measurement test vehicle comprises multiple product layers which are used to build memories except interconnect layers, and one or more customized interconnect layers to connect memory-bit-line-under-tests (MBLUTs), memory-world-line-under-tests (MWLUTs) and memory-bit-cell-under-tests (MUTs). By introducing two transistors, one PMOS and one NMOS, at two opposite sides or the same side of a bit-line or a world-line, the capacitance of the bit-line or the world-line can be measured by a parametric tester. The PMOS device is for pumping in current, and the NMOS device is for draining out the current. By applying a non-overlapping clocked signal at the PMOS and NMOS transistors, the capacitance of bit-line, word-line and bit-cell can be measured as current signal. The PMOS and NMOS transistors are selected from on-chip transistors that are already in the memory design layout.

Abstract: A memory controller performs a reliability test only on a memory array out of the memory array and a random number generator on receipt of a memory test command from a testing device while performing a reliability test only on the random number generator out of the memory array and the random number generator on receipt of a random number test command from the testing device.

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine readable mediums for performing an erase page check. For example, in response to an unexpected (e.g., an asynchronous) shutdown, the memory device may have one or more cells that did not finish programming. The memory device may detect these cells and erase them or mark them for erasure.

Abstract: Methods, systems, and computer-readable media are provided for facilitating record matching and entity resolution and for enabling improvements in record linkage. A power-spectrum-based temporal pattern-specific weight may be incorporated into record linkage methods to enhance the record linkage accuracy and statistical performance. For example, in embodiments, a value-specific weight may be calculated from a population-based frequency of field-specific values or dichotomized values of selected phenotypic variables, and provides an opportunity to capture and measure the relative importance of specific values found in a field. A phenotypic bit-vector “fingerprint” pattern-specific weight or Bayesian power spectrum weight may be determined and incorporated into record linkage methods.

Abstract: A medical imaging system (10) comprises one or more displays (66). A viewer device (86) generates an interactive user interface screen (80) on the display (66), which viewer device (86) enables a user to simultaneously inspect selected image data of multiple patients or multiple images.

Abstract: Approaches presented herein enable performing a health analysis of a user using a smart floor mat. Specifically, a sensory array of the smart floor mat collects static and dynamic pressure data for capturing the movement and force exerted by a user's feet as the user walks across the smart floor mat. A healthcare analysis is then performed by comparing this current measurement data against the user's historical measurement data and expected results to generate a healthcare insight such as a trend, pattern, or deviation. The healthcare insight can predict or indicate a health issue. If a deviation exceeding a predefined permissible threshold exists, a healthcare professional can be notified.

Abstract: Systems and methods are disclosed that access over a network a set of codes and respective code descriptions from a first data store. Course data for courses is accessed over a network from a second data store. Code descriptions and course data are compared, and the comparison is used to generate a mapping of courses to codes. The network interface is used to access codes associated with patient records for a plurality of patients from an electronic medical record system associated with a medical service provider. Relevancy values are calculated for codes using the codes associated with patient records. The calculated relevancy values and the accessed mapping of courses to codes are used to generate a first ranked presentation of recommended courses. A course selection is detected. Using the selection, a second ranked presentation of recommended courses is generated by a learning engine with updated learning engine weights.

Abstract: Described is a system for controlling epidural spinal cord stimulation. Using an Unscented Kalman Filter (UKF), the system receives sensed physiological signals from a subject and, based on the sensed physiological signals, estimating an unobservable state of a target area on the subject. A central pattern generator is then used to generate a stimulation pattern based on the unobservable state. The stimulation pattern is applied to the target area (e.g., spinal cord) of the subject using an electrode array. Receiving feedback, the UKF continuously updates a model of the spinal cord, which results in adjustment of the stimulation pattern as necessary.

Abstract: Systems and methods for model-based optimization of spinal cord stimulation electrodes and devices are disclosed. According to an aspect a method includes providing a patient-specific electroanatomical model including the spine, spinal cord, and a map of target neural elements and non-target neural elements. The method also includes using model electrodes to stimulate the target neural elements. Further, the method includes determining differences in activation thresholds between the target neural elements and the non-target neural elements in a plurality of different configurations of the model electrodes. The method also includes generating an optimal spinal cord stimulation electrode configuration based on the determined differences in activation thresholds.

Abstract: A self-regulating inherently safe apparatus for generating neutrons is described herein that includes a reaction chamber that sustains neutron generation when filled with a liquid fissionable material and an expansion chamber that dampens neutron generation from the liquid fissionable material in response to expansion of the liquid fissionable material into the expansion chamber. Consequently, the apparatus may substantially dampen neutron generation for operating temperatures above a nominal operating temperature without requiring active or external control and inherently limit neutron generation to a maximum desired output power. Also described herein is a self-regulating system and corresponding method for extracting energy from fissionable material that includes a neutron generator that generates neutrons from a liquid fissionable material and a sub-critical collection of fissionable material that generates a non-sustaining plurality of fission events from neutrons received from the neutron generator.

Abstract: A control rod guide frame has a central passage of constant cross-section as a function of position along a central axis that passes through the central passage. The central passage is sized and shaped to guide a traveling assembly including at least one control rod as it moves along the central axis. The control rod guide frame comprises at least two radial guide frame sections secured around and defining the central passage. Each radial guide frame section may comprise an extruded radial guide frame section, which may be made of extruded steel. The central passage may include control rod guidance channels parallel the central axis and machined into the extruded radial guide frame sections. The at least two radial guide frame sections may be interchangeable. In some embodiments the at least two radial guide frame sections consist of between four and eight radial guide frame sections.

Abstract: A nuclear reactor cooling system with passive cooling capabilities operable during a loss-of-coolant accident (LOCA) without available electric power. The system includes a reactor vessel with nuclear fuel core located in a reactor well. An in-containment water storage tank is fluidly coupled to the reactor well and holds an inventory of cooling water. During a LOCA event, the tank floods the reactor well with water. Eventually, the water heated by decay heat from the reactor vaporizes producing steam. The steam flows to an in-containment heat exchanger and condenses. The condensate is returned to the reactor well in a closed flow loop system in which flow may circulate solely via gravity from changes in phase and density of the water. In one embodiment, the heat exchanger may be an array of heat dissipater ducts mounted on the wall of the inner containment vessel surrounded by a heat sink.

Abstract: A method for determining positions of elements of fuel assemblies arranged in a nuclear vessel is described herein. According to an implementation, the method involves capturing a plurality of images of a nuclear vessel and using the plurality of images to estimate a first set of positions of S-holes of a fuel assembly of the nuclear vessel. The method further involves determining a value representative of differences between: (a) the distances from the estimated set of positions to a location on a face of the fuel assembly and (b) known actual distances between the S-holes and the location on the face of the fuel assembly.

Abstract: Gamma-ray sensing probes operating under the Cerenkov effect measure the burnup of spent nuclear fuel assemblies. The probes include an optical fiber that reacts to gamma rays coming from the spent nuclear fuel assembly and emit light via the Cerenkov effect. A scatterer surrounds the optical fiber to increase the light emitting efficiency of the optical fiber by the Compton electron scattering. A collimator composed of shielding material surrounds the scatterer. The collimator has a slit groove which is open in one direction for directing the gamma rays from the spent fuel assembly to the scatterer.

Abstract: An ion exchange system includes one or more strategies to reduce the amount of hydrogen gas inside an ion exchange column when the column is offline or disposed of. The ion exchange system comprises an ion exchange column including a housing and ion exchange media positioned in the housing. The ion exchange column can include one or more of the following: (1) an oxide material that limits the production of hydrogen gas from radiolysis, (2) a hydrogen scavenging material that removes or scavenges hydrogen gas inside the column, and (3) a hydrogen catalytic material that catalyzes the reaction of hydrogen and oxygen inside the column.

Abstract: Various embodiments of a nuclear radiation particle power converter and method of forming such power converter are disclosed. In one or more embodiments, the power converter can include first and second electrodes, a three-dimensional current collector disposed between the first and second electrodes and electrically coupled to the first electrode, and a charge carrier separator disposed on at least a portion of a surface of the three-dimensional current collector. The power converter can also include a hole conductor layer disposed on at least a portion of the charge carrier separator and electrically coupled to the second electrode, and nuclear radiation-emitting material disposed such that at least one nuclear radiation particle emitted by the nuclear radiation-emitting material is incident upon the charge carrier separator.

Abstract: An aluminum alloy wire rod having a composition including Mg: 0.10-1.00 mass %, Si: 0.10-1.00 mass %, Fe: 0.01-1.40 mass %, Ti: 0-0.100 mass %, B: 0-0.030 mass %, Cu: 0-1.00 mass %, Ag: 0-0.50 mass %, Au: 0-0.50 mass %, Mn: 0-1.00 mass %, Cr: 0-1.00 mass %, Zr: 0-0.50 mass %, Hf: 0-0.50 mass %, V: 0-0.50 mass %, Sc: 0-0.50 mass %, Sn: 0-0.50 mass %, Co: 0-0.50 mass %, Ni: 0-0.50 mass %, and the balance: Al and inevitable impurities, wherein a ratio of (standard deviation of crystal grain size of the aluminum alloy wire rod)/(average crystal grain size of the aluminum alloy wire rod) is less than or equal to 0.57, and a ratio of (diameter of the aluminum alloy wire rod)/(average crystal grain size of the aluminum alloy wire rod) is greater than or equal to 10.

Abstract: The present invention relates to a conductor having a substrate and a conductive coating film laminated on the substrate, wherein, the surface resistance value of the conductive coating film is 5×1010?/? or less, the Ra1 of the conductive coating film is 0.7 nm or less, the Ra2 value of the conductive coating film scanning probe microscopies 0.35 nm or less, and the conductive coating film is formed with a conductive composition containing a conductive polymer (A). In addition, the present invention relates to a conductive composition which contains a conductive polymer (A) and a surfactant (B), wherein the surfactant (B) contains a specific water-soluble polymer (C), and the content of a compound (D1) with an octanol-water partition coefficient (Log Pow) of 4 or more in the conductive composition is 0.001 mass % or less, relative to the total mass of the conductive composition.

Abstract: A method of manufacturing a composite material may include providing one or more layers of reinforcement material penetrated with viscous matrix material that is doped with electrically conductive particles. The method may further include applying a magnetic field to arrange the particles into one or more electrically conductive pathways, and curing the matrix material to secure the pathways in position relative to the reinforcement material.

Abstract: Provided is a method for manufacturing a molded plastic products having copper-based compound particulates. The method includes the steps of: reacting copper sulfate with sulfuric salt, at a molar ratio of 1:1 in an aqueous solution at a temperature of 10˜80° C., thereby synthesizing copper sulfide particulates; forming a sheet comprising the copper sulfide particulates dispersed in a thermoplastic resin.