Abstract: An electromagnetic lens for charged particle beam exhibits positive spherical aberration. A complicated combination of electromagnetic lenses had been necessary for correcting this spherical aberration. One of a circular aperture or a ring-shaped aperture is provided on an incident plate arranged on an incident side of charged particle beam, another of the circular aperture or the ring-shaped aperture is provided on a plate arranged on an emission side thereof, and a voltage is applied between the incident plate and the emission plate. By so doing, an electric field generated in the ring-shaped aperture emanates, which resolves the positive spherical aberration. The spherical aberration can be corrected by an extremely simple and easily implemented structure.

Abstract: A cross-section processing-and-observation method includes: a cross-section exposure step of irradiating a sample with a focused ion beam to expose a cross-section of the sample; a cross-sectional image acquisition step of irradiating the cross-section with an electron beam to acquire a cross-sectional image of the cross-section; and a step of repeatedly performing the cross-section exposure step and the cross-sectional image acquisition step along a predetermined direction of the sample at a setting interval to acquire a plurality of cross-sectional images of the sample. In the cross-sectional image acquisition step, a cross-sectional image is acquired under different condition settings for a plurality of regions of the cross-section.

Abstract: A method for initializing a first operation in a first module at a first start time value in a first time base, the method comprising generating a clock signal, generating a second time base in the first module based on the clock signal, determining a second sync value in the second time base, determining a first sync value in the first time base corresponding to a second sync value in the second time base, determining a start trigger value in the second time base based on the first sync value and the start time value in the first time base, and initializing the first operation in the first module based on the start trigger value and a current value of the second time base in the first module.

Abstract: The present invention is: a pattern measurement device that, regardless of increased fineness, deviation, or the like of a pattern, accurately and stably performs measurement on the basis of edge identification or pattern or edge judgment; and a computer program. The pattern measurement device classifies pattern sites (G1, G2, G3, G4), which are repeatedly arrayed at a specific interval, in accordance with the position of the pattern sites, and executes a pattern edge type identification, a pattern type identification, or a measurement of the dimensions between predetermined pattern sites on the basis of an association between the classified pattern sites and information pertaining to the pattern edge type or information pertaining to the pattern type. The computer program causes a computer to execute the abovementioned process.

Abstract: In one embodiment, a data processing method is for creating write data from design data, and registering the write data into a writing apparatus. The method includes applying, to a plurality of pieces of first frame data into which first chip data of the design data is divided, a plurality of conversion processes to create the write data, and applying a plurality of pre-processes to a plurality of pieces of second frame data into which second chip data of the write data is divided, and registering the second chip data into the writing apparatus. The plurality of conversion processes and the plurality of pre-processes are each performed in a pipeline processing on a per-frame basis. The write data is registered into the writing apparatus on a per-chip basis, on a per-virtual chip basis, or on a per-frame basis. The virtual chip includes a plurality of chips combined together.

Abstract: A plasma etching apparatus includes an etching chamber and at least one processor. The etching chamber is configured to support a target therein. The at least one processor is configured to: determine a process condition for plasma etching the target before execution of a plasma etching process; and control an aspect of the chamber according to the process condition. The process condition includes a unit etching time over which the plasma etching process is to be continuously performed.

Abstract: A resonance frequency can be adjusted by shifting the resonance frequency without reducing an impedance function or a withstanding voltage characteristic against a high frequency noise, when blocking, by using a multiple parallel resonance characteristic of a distributed constant line, the high frequency noise introduced into a power feed line from an electrical member other than a high frequency electrode within a processing vessel. Comb teeth M of a comb-teeth member 114 are inserted into winding gaps of air core coils 104(1) and 104(2). For example, first comb teeth M? having a thickness m? smaller than a standard thickness ts are mainly inserted in an effective zone A in a central portion of the air core coils. Further, in non-effective zones B at both sides or both end portions thereof, second comb teeth M+ having a thickness m+ equal to or larger than the standard thickness ts are arranged.

Abstract: Apparatus for physical vapor deposition are provided. In some embodiments, an apparatus for use in a physical vapor deposition substrate processing chamber includes a process shield having a central opening passing through a body of the process shield and defining a processing volume of the substrate processing chamber, wherein the process shield comprises an annular dark space shield fabricated from a ceramic material and an annular ground shield fabricated from a conductive material, and wherein a ratio of a length of the annular dark space shield to a length of the annular ground shield is about 1:2 to about 1:1.6.

Abstract: A low temperature plasma probe, a mass spectrometry system, and a method for using a low temperature plasma probe are described. In an embodiment, a low temperature plasma probe includes an intake capillary that provides an ion flow from a sample surface to a mass spectrometer; at least one low temperature plasma tube that provides low temperature plasma gas; at least one heated gas tube that provides heated gas to the sample surface, where the heated gas enhances desorption and ionization of a sample on the sample surface.

Abstract: Certain embodiments described herein are directed to induction devices comprising an oxidation resistant material. In certain examples, the induction device comprises a coil of wire that is produced from the oxidation resistant material. In some examples, the oxidation resistant induction device can be used to sustain an inductively coupled plasma in a torch.

Abstract: A miniature mass spectrometer is disclosed comprising an atmospheric pressure ionization source, a first vacuum chamber having an atmospheric pressure sampling orifice or capillary, a second vacuum chamber located downstream of the first vacuum chamber and a third vacuum chamber located downstream of the second vacuum chamber. A first vacuum pump is arranged and adapted to pump the first vacuum chamber, wherein the first vacuum pump is arranged and adapted to maintain the first vacuum chamber at a pressure <10 mbar. A first RF ion guide is located within the first vacuum chamber and an ion detector is located in the third vacuum chamber. The ion path length from the atmospheric pressure sampling orifice or capillary to an ion detecting surface of the ion detector is ?400 mm.

Abstract: Systems and methods for filtering a continuous beam of ions are provided. An acceleration electric field is applied to a continuous beam of ions using an accelerator to produce an accelerated beam of ions. A field is applied to the accelerated beam to separate ions in time and space using a deflector producing a separated beam of ions. The field applied by the deflector is a rotating field or a circulant rastering field. The rotating field can be a rotating magnetic or electric field. Only accept those ions from the separated beam whose m/z values lie within a range centered around a target m/z value using an aperture. The aperture can include a pinhole aperture in a rotating disk or an annular aperture in a first stationary disk, a second deflector, and a pinhole aperture in the center of a second stationary disk.

Abstract: A semiconductor wafer has a base material. The semiconductor wafer may have an edge support ring. A grinding phase of a surface of the semiconductor wafer removes a portion of the base material. The grinder is removed from or lifted off the surface of the semiconductor wafer during a separation phase. The surface of the semiconductor wafer and under the grinder is rinsed during the grinding phase and separation phase to remove particles. A rinsing solution is dispensed from a rinsing solution source to rinse the surface of the semiconductor wafer. The rinsing solution source can move in position while dispensing the rinsing solution to rinse the surface of the semiconductor wafer. The grinding phase and separation phase are repeated during the entire grinding operation, when grinding conductive TSVs, or during the final grinding stages, until the final thickness of the semiconductor wafer is achieved.

Abstract: An EUV cleaner system and process for cleaning a EUV carrier. The EUV cleaner system comprises separate dirty and cleaned environments, separate cleaning chambers for different components of the double container carrier, gripper arms for picking and placing different components using a same robot handler, gripper arms for holding different components at different locations, horizontal spin cleaning and drying for outer container, hot water and hot air (70 C) cleaning process, vertical nozzles and rasterizing megasonic nozzles for cleaning inner container with hot air nozzles for drying, separate vacuum decontamination chambers for outgassing different components, for example, one for inner and one for outer container with high vacuum (e.g., <10?6 Torr) with purge gas, heaters and RGA sensors inside the vacuum chamber, purge gas assembling station, and purge gas loading and unloading station.

Abstract: A substrate processing method and apparatus for preventing evaporation of an anti-drying fluorine-containing organic solvent from a substrate during transportation of the substrate into a processing container and can prevent decomposition of a fluorine-containing organic solvent in the processing container. A substrate, the surface of which is covered with a first fluorine-containing organic solvent, is carried into a processing container. The first fluorine-containing organic solvent is removed from the substrate surface by forming a high-pressure fluid atmosphere of a mixture of the first fluorine-containing organic solvent and a second fluorine-containing organic solvent, having a lower boiling point than the first fluorine-containing organic solvent, in the processing container e.g. by supplying a high-pressure fluid of the second fluorine-containing organic solvent into the processing container.

Abstract: A method of manufacturing a semiconductor device includes: forming a film on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing: supplying a precursor from a first nozzle to a substrate and exhausting the precursor from an exhaust port; supplying a first reactant from a second nozzle to the substrate and exhausting the first reactant from the exhaust port; and supplying a second reactant from a third nozzle to the substrate and exhausting the second reactant from the exhaust port. A substrate in-plane film thickness distribution of the film formed on the substrate is controlled by controlling a balance between a flow rate of an inert gas supplied from the second nozzle, a flow rate of an inert gas supplied from the third nozzle, and a flow rate of an inert gas supplied from the first nozzle in supplying the precursor.

Abstract: Atomic layer deposition methods for the low temperature deposition of silicon dioxide films having low nitrogen content and low wet etch rates. Silicon dioxide films are deposited and treated with plasma and re-oxidized resulting in low nitrogen content films.

Abstract: A substrate processing method includes applying a solution of a compound containing a metal oxide to a surface of a wafer to form a liquid film of the solution on the surface of the wafer, heating the liquid film at a first temperature lower than a crosslinking temperature of the compound, and irradiating the liquid film with energy rays to form a coating film containing the metal oxide on the surface, after heating the liquid film at the first temperature.

Abstract: Methods of processing a substrate are provided herein. In some embodiments, a method of processing a substrate disposed in a processing chamber includes: (a) depositing a layer of material on a substrate by exposing the substrate to a first reactive species generated from a remote plasma source and to a first precursor, wherein the first reactive species reacts with the first precursor; and (b) treating all, or substantially all, of the deposited layer of material by exposing the substrate to a plasma generated within the processing chamber from a second plasma source; wherein at least one of the remote plasma source or the second plasma source is pulsed to control periods of depositing and periods of treating.

Abstract: In an LCD driver, in a high voltage resistant MISFET, end portions of a gate electrode run onto electric field relaxing insulation regions. Wires to become source wires or drain wires are formed on an interlayer insulation film of the first layer over the high voltage resistant MISFET. At this moment, when a distance from an interface between a semiconductor substrate and a gate insulation film to an upper portion of the gate electrode is defined as “a”, and a distance from the upper portion of the gate electrode to an upper portion of the interlayer insulation film on which the wires are formed is defined as “b”, a relation of a>b is established. In such a high voltage resistant MISFET structured in this manner, the wires are arranged so as not to be overlapped planarly with the gate electrode of the high voltage resistant MISFET.

Abstract: A method is for improving adhesion between a semiconductor substrate and a dielectric layer. The method includes depositing a silicon dioxide adhesion layer onto the semiconductor substrate by a first plasma enhanced chemical vapor deposition (PECVD) process, and depositing the dielectric layer onto the adhesion layer by a second PECVD process. The first PECVD process is performed in a gaseous atmosphere comprising tetraethyl orthosilicate (TEOS) either in the absence of O2 or with O2 introduced into the process at a flow rate of 250 sccm or less.

Abstract: According to exemplary embodiments, a method of synthesizing tin (Sn)-doped Zinc Sulfide (ZnS) nanostructures for electroluminescent white light source includes coating a substrate, including a silicon oxide layer, with Sn by vacuuming depositing Sn as catalyst nanostructures on the substrate, placing the substrate coated with Sn in a furnace, introducing a carrier flow gas into the furnace, adding a ZnS power to the furnace, growing ZnS nanostructures, and dissolving Sn in the growing ZnS nanostructures. The S vacancies are on a surface of the ZnS nanostructures. The ZnS nanostructures are grown on the substrate having a temperature in a range of 750° C. to 850° C.

Abstract: A method of growing a single-crystal, silicon carbide epitaxial film on a silicon carbide substrate by chemical vapor deposition is disclosed that results in a stress value of the epitaxial film within ±7.8 MPa. For example, from the start of the growth of the epitaxial film until completion, introduction of a source gas including a gas containing silicon, a gas containing carbon, and a gas containing chlorine into a reaction chamber and performing epitaxial growth is alternately performed with suspension of the supply of the gas containing silicon and the gas containing carbon into the reaction chamber while furnace temperature is maintained as is during performing processing in a gas atmosphere containing only hydrogen, or hydrogen and hydrogen chloride, whereby the epitaxial film is grown. Employing such a method enables manufacture of a substrate having a silicon carbide epitaxial film with minimal warpage.

Abstract: A method for fabricating a structure having surfaces exposed to plasma in a substrate processing system includes providing a sacrificial substrate having a first shape, machining the substrate into a second shape, the second shape having dimensions corresponding to a desired final shape of the structure, depositing a layer of material on the substrate, machining first selected portions of the layer of material to expose the substrate within the layer of material, removing remaining portions of the substrate, and machining second selected portions of the layer of material into the structure having the desired final shape without machining the surfaces of the structure that are exposed to plasma during processing.

Abstract: Various embodiments may provide a low temperature (i.e., less than 850° C.) method of Silicon-Germanium (SiGe) on sapphire (Al2O3) (SiGe/sapphire) growth that may produce a single crystal film with less thermal loading effort to the substrate than conventional high temperature (i.e., temperatures above 850° C.) methods. The various embodiments may alleviate the thermal loading requirement of the substrate, which in conventional high temperature (i.e., temperatures above 850° C.) methods had surface temperatures within the range of 850° C.-900° C. The various embodiments may provide a new thermal loading requirement of the sapphire substrate for growing single crystal SiGe on the sapphire substrate in the range of about 450° C. to about 500° C.

Abstract: Described herein are techniques for forming an epitaxial III-V layer on a substrate. In a pre-clean chamber, a native oxygen layer may be replaced with a passivation layer by treating the substrate with a hydrogen plasma (or products of a plasma decomposition). In a deposition chamber, the temperature of the substrate may be elevated to a temperature less than 700° C. While the substrate temperature is elevated, a group V precursor may be flowed into the deposition chamber in order to transform the hydrogen terminated (Si—H) surface of the passivation layer into an Arsenic terminated (Si—As) surface. After the substrate has been cooled, a group III precursor and the group V precursor may be flowed in order to form a nucleation layer. Finally, at an elevated temperature, the group III precursor and group V precursor may be flowed in order to form a bulk III-V layer.

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

Abstract: A method for depositing a hardmask layer on a substrate includes nitridating a first layer of the substrate. The first layer is selected from a group consisting of silicon dioxide and silicon nitride. An amorphous carbon layer is deposited on the nitridated first layer via plasma-enhanced chemical vapor deposition (PECVD). A monolayer is deposited on the amorphous carbon layer using gas mixture including a metal precursor gas with a reducing agent and without plasma. A bulk metal-doped carbon hardmask layer is deposited on the monolayer.

Abstract: A composition for manufacturing a semiconductor device includes at least one carbon-based compound that includes at least one of an alkyne group and an azide group, and a solvent. A method of manufacturing a semiconductor device includes forming a feature layer on a substrate, coating the feature layer with a composition including alkyne and azide, forming a carbon-containing layer including a triazole compound by performing a heat treatment on the coated composition, forming a photoresist film on the carbon-containing layer, forming photoresist patterns by exposing and developing the photoresist film, and patterning the carbon-containing layer and the feature layer using the photoresist patterns.

Abstract: An etch process that includes removing an oxide containing surface layer from a semiconductor surface to be etched by applying a hydrofluoric (HF) based chemistry, wherein the hydrofluoric (HF) based chemistry terminates the semiconductor surface to be etched with silicon-hydrogen bonds, and applying a vapor priming agent bearing chemical functionality based on the group consisting of alkynes, alcohols and a combination thereof to convert the silane terminated surface to a hydrophobic organic surface. The method continues with forming a photoresist layer on the hydrophobic organic surface; and patterning the photoresist layer. Thereafter, the patterned portions of the photoresist are developed to provide an etch mask. The portions of the semiconductor surface exposed by the etch mask are then etched.

Abstract: The present invention for imaging sensor rejuvenation may include a rejuvenation illumination system configured to selectably illuminate a portion of an imaging sensor of an imaging system with illumination suitable for at least partially rejuvenating the imaging sensor degraded by exposure to at least one of extreme ultraviolet light or deep ultraviolet light; and a controller communicatively coupled to the rejuvenation illumination system and configured to direct the rejuvenation illumination system to illuminate the imaging sensor for one or more illumination cycles during a non-imaging state of the imaging sensor.

Abstract: Provided is a method of fabricating a semiconductor device. In the method, a double patterning technology is used to form various patterns with different widths.

Abstract: A method for controlling the temperature profile of phosphoric acid process over a wafer surface through the dynamic control of radial dispensing of sulfuric acid at a selected temperature, which includes providing a substrate with a layer formed thereupon; dispensing a first chemical and second chemicals onto the layer while adjusting at least one parameter of the second chemical dispense to vary the etch rate across a region of the substrate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a bottom layer over a substrate and forming a middle layer over the bottom layer. The middle layer includes a carbon backbone and a first side chain bonded to the carbon backbone, and the first side chain has a hydrophilic group. The method includes forming a top layer over the middle layer and patterning the top layer to form a patterned top layer. The method includes patterning the middle layer by using the patterned top layer as a mask to form a patterned middle layer. The method includes patterning the bottom layer to form a patterned bottom layer. The method also includes removing the patterned middle layer by a base solution, and the middle layer is soluble in the base solution by the hydrophilic group.

Abstract: An apparatus and method for providing target thickness and surface profile uniformity control of a multi-head chemical mechanical polishing (CMP) process is disclosed. An exemplary method includes providing at least two wafers; determining a surface profile of each of the at least two wafers; determining an operation mode for a chemical mechanical polishing (CMP) process based on the surface profiles of the at least two wafers; determining a CMP polishing recipe for each of the at least two wafers based on the operation mode; and performing the CMP process on the at least two wafers based on the determined CMP polishing recipes.

Abstract: A method for patterning a layer increases the density of features formed over an initial patterning layer using a series of self-aligned spacers. A layer to be etched is provided, then an initial sacrificial patterning layer, for example formed using optical lithography, is formed over the layer to be etched. Depending on the embodiment, the patterning layer may be trimmed, then a series of spacer layers formed and etched. The number of spacer layers and their target dimensions depends on the desired increase in feature density. An in-process semiconductor device and electronic system is also described.

Abstract: A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer, the sacrificial layer disposed on hardmask arranged on a substrate, and the substrate including a bulk semiconductor layer, a buried oxide layer arranged on the bulk semiconductor layer, and a semiconductor layer arranged on the buried oxide layer; forming oxide spacers on sidewalls of the opening in the sacrificial layer; using the oxide spacers as a pattern to etch a trench through the substrate, the trench stopping at a region within the bulk semiconductor layer; and depositing a conductive material in the trench to form the substrate contact.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes forming a plug in a first insulator, forming a first film on the first insulator and the plug, and forming an opening in the first film. The method further includes forming a second insulator in the opening to form an air gap in the opening, removing the first film after forming the second insulator, to expose the plug, and forming an interconnect on the exposed plug.

Abstract: In one embodiment, a substrate processing liquid contains phosphoric acid as a primary component and contains water and ketone. In another embodiment, a substrate processing method includes processing a substrate in a substrate processing bath with a substrate processing liquid containing phosphoric acid, water and ketone. The method further includes discharging the substrate processing liquid from the substrate processing bath to a circulating flow channel, heating the substrate processing liquid flowing through the circulating flow channel at a temperature between 50° C. and 90° C., and supplying the substrate processing liquid again from the circulating flow channel to the substrate processing bath to circulate the substrate processing liquid under heating.

Abstract: Provided herein are methods of atomic layer etching (ALE) of metals including tungsten (W) and cobalt (Co). The methods disclosed herein provide precise etch control down to the atomic level, with etching a low as 1 ? to 10 ? per cycle in some embodiments. In some embodiments, directional control is provided without damage to the surface of interest. The methods may include cycles of a modification operation to form a reactive layer, followed by a removal operation to etch only this modified layer. The modification is performed without spontaneously etching the surface of the metal.

Abstract: The invention provides a method of forming a semiconductor structure, which include: providing an intermediate semiconductor structure having semiconductor substrate, a fin having an EG oxide layer in contact with at least a portion of the fin, and a gate stack disposed over a portion of the fin; forming a silicon nitride layer over portions of the fin that are not located under the gate stack; and after forming the silicon nitride layer, performing one or more ion implantation steps on the intermediate semiconductor structure.

Abstract: Provided is a method for manufacturing a semiconductor device with favorable electrical characteristics. The following steps are performed in the following order: forming an oxide semiconductor film over a substrate having a substantially planar surface; selectively etching the oxide semiconductor film to form an oxide semiconductor layer; implanting an oxygen ion on a top surface of the oxide semiconductor layer and a side surface of the oxide semiconductor layer in a cross-section perpendicular to the substantially planar surface in a channel width direction of the oxide semiconductor layer from an angle 0°<?<90°; forming an insulating layer over the oxide semiconductor layer, and performing heat treatment on the oxide semiconductor layer to diffuse oxygen into the oxide semiconductor layer.

Abstract: Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using an inkjet process to create conductive paths on each molding compound layer of the semiconductor package.

Abstract: A method of fabricating a packaging substrate is provided, including: providing a carrier having two carrying portions, each of the carrying portions having a first side and a second side opposite to the first side and the carrying portions are bonded through the second sides thereof; forming a circuit layer on the first side of each of the carrying portions; and separating the two carrying portions from each other to form two packaging substrates. The carrying portions facilitate the thinning of the circuit layers and provide sufficient strength for the packaging substrates to undergo subsequent packaging processes. The carrying portions can be removed after the packaging processes to reduce the thickness of packages and thereby meet the miniaturization requirement.

Abstract: A substrate cleaning apparatus capable of preventing a cleaning vessel from being corroded by a chemical liquid while constituting the cleaning vessel with a low-price material is provided. The substrate cleaning apparatus includes: a cleaning vessel for holding a substrate therein; a substrate holder arranged in the cleaning vessel; a chemical liquid nozzle for supplying a chemical liquid onto the substrate held by the substrate holder; and a plurality of cleaning liquid nozzles for supplying a cleaning liquid onto an inner surface of the cleaning vessel. The inner surface of the cleaning vessel has been subjected to a hydrophilization treatment.

Abstract: The inventive substrate treatment apparatus includes: a rotative treatment control unit which controls a first chemical liquid supplying unit and a second chemical liquid supplying unit to perform a first chemical liquid supplying step of supplying a first chemical liquid to a substrate rotated by a substrate holding and rotating mechanism and a second chemical liquid supplying step of supplying a second chemical liquid to the substrate rotated by the substrate holding and rotating mechanism after the first chemical liquid supplying step; and a cleaning control unit which controls the cleaning liquid supplying unit to spout the cleaning liquid from the cleaning liquid outlet port to supply the cleaning liquid to the cup inner wall and/or the base wall surface before start of the second chemical liquid supplying step after end of the first chemical liquid supplying step, and/or during and/or after the second chemical liquid supplying step.

Abstract: Apparatus for processing a substrate is disclosed herein. In some embodiments, a substrate support may include a substrate support having a support surface for supporting a substrate the substrate support having a central axis; a first electrode disposed within the substrate support to provide RF power to a substrate when disposed on the support surface; an inner conductor coupled to the first electrode about a center of a surface of the first electrode opposing the support surface, wherein the inner conductor is tubular and extends from the first electrode parallel to and about the central axis in a direction away from the support surface of the substrate support; an outer conductor disposed about the inner conductor; and an outer dielectric layer disposed between the inner and outer conductors, the outer dielectric layer electrically isolating the outer conductor from the inner conductor. The outer conductor may be coupled to electrical ground.

Abstract: A substrate processing apparatus includes a processing container configured to air-tightly accommodate substrates, a plurality of mounting stands configured to mount the substrates, a process gas supply part configured to supply a process gas to the mounting stands, an exhaust mechanism configured to evacuate an interior of the processing container, a partition wall configured to independently surround the mounting stands with a gap left between the partition wall and each of the mounting stands, and cylindrical inner walls configured to independently surround the mounting stands with a gap left between each of the inner walls and each of the mounting stands. Slits are formed in the inner walls. The process gas in the processing spaces is exhausted via the slits. The inner walls include partition plates for bypassing the process gas so that the process gas does not directly flow into the slits.

Abstract: Methods and process chambers for etching of low-k and other dielectric films are described. For example, a method includes modifying portions of the low-k dielectric layer with a plasma process. The modified portions of the low-k dielectric layer are etched selectively over a mask layer and unmodified portions of the low-k dielectric layer. Etch chambers having multiple chamber regions for alternately generating distinct plasmas are described. In embodiments, a first charge coupled plasma source is provided to generate an ion flux to a workpiece in one operational mode, while a secondary plasma source is provided to provide reactive species flux without significant ion flux to the workpiece in another operational mode. A controller operates to cycle the operational modes repeatedly over time to remove a desired cumulative amount of the dielectric material.

Abstract: A substrate liquid processing apparatus includes a liquid processing unit configured to process a substrate by a processing liquid, and a controller. The controller processes the substrate in the liquid processing unit, and switches the processing liquid discharged from a discharge line, from a recycling line, to a waste line in which the processing liquid is discarded through the discharge line to the outside, according to a concentration of an elution component eluted from the substrate.