Abstract: Semiconductor devices including an interconnection structure are provided. The devices may include an etch stop layer on a lower structure including a contact structure, a buffer layer on the etch stop layer, an intermetal insulating layer including a low-k dielectric material on the buffer layer. The intermetal insulating layer may include a first region having a first dielectric constant and a second region having a second dielectric constant different from the first dielectric constant. The device may also include interconnection structure including a plug portion electrically connected to the contact structure and an interconnection portion on the plug portion. The plug portion may include a first portion extending through the etch stop layer and a second portion that is in the intermetal insulating layer and has a width greater than a width of the first portion. The interconnection portion may include opposing lateral surfaces surrounded by the intermetal insulating layer.

Abstract: A semiconductor structure having a Group III-N semiconductor layer disposed on a substrate. A multi-layer, electrical contact structure in contact with the Group III-N semiconductor layer includes a gold-free contact layer in contact with the Group III-N semiconductor layer; and a gold-free electrically conductive etch stop layer electrically connected to the gold-free contact layer. An electrically conductive via passes through the substrate to the etch stop layer. The structure includes a plurality of electrode structures, each one providing a corresponding one of a source electrode structure, drain electrode structure and a gate electrode structure. The source electrode structure, drain electrode structure and gate electrode structure include: an electrical contact structure and an electrode contact. The electrode contacts have the same gold-free structure and have co-planar upper surfaces.

Abstract: An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface. A conductive via extends elevationally into the material of the one terminal. The conductive via extends laterally into the material of the one terminal under the upper surface of the one terminal. Material of the one terminal is above at least some of the laterally extending conductive via. Other embodiments, including method embodiments, are disclosed.

Abstract: A fan-out semiconductor package includes: a first semiconductor chip; a first encapsulant; a connection member including first vias and a first redistribution layer; a second semiconductor chip; a second encapsulant; a second redistribution layer; second vias; and third vias. A length of the longest side of a first cut surface of the second via is less than that of the longest side of a second cut surface of the third via, the first cut surface of the second via and the second cut surface of the third via being cut by a plane on any level parallel to the second active surface.

Abstract: A package includes a device die, a molding material molding the device die therein, and a plurality of redistribution lines overlying the device die and the molding material. A laser mark pad is coplanar with one of the plurality of redistribution lines, wherein the laser mark pad and the one of the plurality of redistribution layers are formed of the same conductive material. A polymer layer is over the laser mark pad and the plurality of redistribution lines. A tape is attached over the polymer layer. A laser mark penetrates through the tape and the polymer layer. The laser mark extends to a top surface of the laser mark pad.

Abstract: A mark is formed over the surface of a silicon substrate. The mark includes a silicon oxide film, in which a plurality of rectangular groove patterns are concentrically arranged, and a silicon nitride film formed in the groove patterns. A P-type epitaxial layer is formed over the surface of the silicon substrate. Then, a photoresist pattern is formed. In the photoresist pattern, a rectangular opening pattern is formed in a mark region. Optical superposition inspection is performed for the base of the photoresist pattern.

Abstract: Consistent with an example embodiment, a semiconductor device comprises a device die having bond pads providing connection to device die circuitry and a QFN half-etched lead frame with a package boundary; the QFN half-etched lead frame has a top-side surface and an under-side surface. The QFN half-etched lead frame includes a sub-structure of I/O terminals and a die attach area, the die attach area facilitating device die attachment thereon and the terminal I/O terminals providing connection to the device die bond pads and additional terminals located about the corners of the sub-structure. An envelope of molding compound encapsulates the device die mounted on the top-side surface of the QFN half-etched lead frame. A RF (radio-frequency) shield layer is on the envelope of the molding compound, the RF shield electrically connected to the additional terminals via conductive connections defined in corresponding locations on the envelope of the molding compound.

Abstract: A semiconductor device includes a substrate and a conductive layer. The substrate has an upper surface that is a substantially rectangular shape having a pair of two sides extending in a first direction and a pair of two sides extending in a second direction. The conductive layer is provided on the substrate and extending along a periphery of the substrate. The conductive layer extends and zigzags toward the first direction.

Abstract: Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad structure.

Abstract: A multi-band antenna package structure includes a first redistribution layer; an integrated circuit layer, formed on the first redistribution layer, comprising at least one metal via, at least one metal pillar, an integrated circuit chip, and a molding layer, wherein the molding layer is used to fill openings formed by the metal via, the metal pillar and the integrated circuit chip which are disposed on the first redistribution layer, the metal via is electrically connected to one of the first metal patterns of the first redistribution layer; a second redistribution layer, formed on the integrated circuit layer; and a first antenna unit layer, comprising a first dielectric layer and third metal patterns formed in openings of the first dielectric layer, wherein at least one of the third metal patterns is electrically connected to one of the second metal patterns, and the third metal patterns form a first antenna unit.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed on the first interconnection member, an active surface of the memory chip, and an active surface of the processor chip. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to connection pads of the processor chip and connection pads of the memory chip, and the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a processor chip disposed in the through-hole; a memory chip disposed in the through-hole and including a plurality of dies stacked on each other; an encapsulant encapsulating at least portions of the first interconnection member, the memory chip, and the processor chip; and a second interconnection member disposed on the first interconnection member, an active surface of the memory chip, and an active surface of the processor chip. The first interconnection member and the second interconnection member respectively include redistribution layers electrically connected to connection pads of the processor chip and connection pads of the memory chip, and the connection pads of the processor chip and the connection pads of the memory chip are electrically connected to each other by the redistribution layer of the second interconnection member.

Abstract: An integrated circuit die having at least two bond pads, a redistribution layer, the redistribution layer including at least one solder pad including comprising two portions arranged to enable an electrical connection between each other by a same solder ball placed on the solder pad, but electrically isolated of each other in the absence of a solder ball on the solder pad at least two redistribution wires, each one connecting one of the two portions to one of the two bond pads, a first bond pad connected via a first redistribution wire to a first portion of the solder pad being dedicated to digital ground and a second bond pad connected via a second redistribution wire to a second portion of the solder pad being dedicated to analog ground.

Abstract: A power module package includes a single-layered circuit board, a first electronic component, and a second electronic component. The single-layered circuit board includes an insulating substrate and a conductive layer thereon. A bottom surface of the conductive layer touches a top surface of the insulating substrate. The insulating substrate has plural first openings to allow the conductive layer to be exposed from the bottom surface of the insulating substrate. The first electronic component is disposed on a top surface of the conductive layer. The second electronic component is disposed on the bottom surface of the insulating substrate and received in the first openings. The second electronic component is connected to the conductive layer via the first openings. At least one of the first electronic component and the second electronic component is a bare die.

Abstract: A method of forming a semiconductor package includes receiving a carrier, coating the carrier with a bonding layer, forming a first insulator layer over the bonding layer, forming a backside redistribution layer over the first insulator layer, forming a second insulator layer over the backside redistribution layer, patterning the second insulator layer to form a recess that extends through the second insulator layer and to the backside redistribution layer, filling the recess with a solder, and coupling a surface-mount device (SMD) to the solder.

Abstract: A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top surface thereof, forming a resin insulating layer covering the semiconductor device, forming an opening, exposing the external terminal, in the resin insulating layer, performing plasma treatment on a bottom surface of the opening, performing chemical treatment on the bottom surface of the opening after the plasma treatment, and forming a conductive body to be connected with the external terminal exposed in the opening.

Abstract: A substrate comprising a solid glass core having a first surface and a second surface opposed to the first surface; multiple conductors extending through the solid glass core beginning at the first surface and ending at the second surface, wherein one of the conductors has a third surface and a fourth surface, wherein the third surface and the first surface are substantially coplanar, wherein the second surface and the fourth surface are substantially coplanar, wherein one of the conductors comprise a copper-tungsten alloy material, wherein the solid glass core is directly contact with the conductor; and a first dielectric layer and a first metal layer formed at the first surface, wherein the first metal layer at the first surface is electrically coupled with one of the conductors.

Abstract: A semiconductor device includes a semiconductor module having a semiconductor element, a radiator plate which is connected to the semiconductor element and which has at least one radiator plate through hole formed therein, and resin covering the semiconductor element and the radiator plate with a lower surface of the radiator plate exposed, a cooler, first insulating grease provided between the lower surface of the radiator plate and the cooler to thermally connect the radiator plate and the cooler, and second insulating grease provided in the at least one radiator plate through hole to be connected to the first insulating grease.

Abstract: A package substrate including a carrier, a first patterned conductive layer, a second patterned conductive layer and a 3D-printing conductive wire is provided. The carrier has a first surface, a second surface and a third surface. The first surface is opposite to the second surface, and the third surface is connected between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface. The second patterned conductive layer is disposed on the second surface. The 3D-printing conductive wire is disposed on the third surface and connected between the first patterned conductive layer and the second patterned conductive layer.

Abstract: Disclosed is a die bonding tool comprising: a rigid body; and a collet having a die-holding portion; wherein the collet is mechanically coupled to the rigid body by a flexible element which is configured to angularly deflect relative to the rigid body on application of a torque to the collet and/or to a die held by the collet. Also disclosed is a die bonding system comprising the die bonding tool, and an adhesive dispenser for a die bonding system.

Abstract: The present disclosure relates to a method for manufacturing a semiconductor device. The method includes providing a first electronic component including a first metal contact and a second electronic component including a second metal contact, changing a lattice of the first metal contact, and bonding the first metal contact to the second metal contact under a predetermined pressure and a predetermined temperature.

Abstract: An object of the invention is to provide: a manufacturing method for a highly reliable power semiconductor device which prevents breakage of an conductor pattern and an insulating layer, and has bonding strength higher than that by the conventional bonding between the electrode terminal and the conductor pattern; and that power semiconductor device. Breakage of the conductor pattern and the insulating layer is prevented due to inclusion of: a step of laying an electrode terminal on a protrusion provided on a conductor pattern placed on a circuit-face side of a ceramic board so that a center portion of a surface to be bonded of the electrode terminal makes contact with a head portion of the protrusion; a step of pressurizing and ultrasonically vibrating a surface opposite to the surface to be bonded, of the electrode terminal, using an ultrasonic horn, to thereby bond the electrode terminal to the conductor pattern.

Abstract: A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.

Abstract: A power semiconductor module that comprises plural arrangements of power semiconductor elements comprising a power semiconductor bare chip which one electrode portion thereof is connected to a metal plate which at least one external connecting terminal is formed and other external connecting terminals which are electrically connected to other electrode portions of the power semiconductor bare chip, and that are contained in a same package, comprises wherein the power semiconductor elements are basically same outline, electrodes of the bare chip of the power semiconductor elements are mutually connected between the power semiconductor elements with a metal connector or a wiring, and the package is a resin mold package that seals the power semiconductor elements with an electrical insulating resin.

Abstract: A face-to-face semiconductor assembly is characterized by a semiconductor device positioned in a dielectric recess of a core base and surrounded by an array of metal posts. The recess in the core provides lateral displacement control between the device and the metal posts, and the minimal height of the metal posts needed for the vertical connection between both opposite sides of the core base can be reduced by the amount equal to the depth of the recess. Further, the semiconductor device is face-to-face electrically coupled to another semiconductor device through a buildup circuitry therebetween.

Abstract: A semiconductor device includes a first semiconductor chip including an inorganic protective film, a second semiconductor chip including an organic protective film and a re-wiring layer, the second semiconductor chip being electrically connected to the first semiconductor chip through a through-silicon via and a bump connection, a third semiconductor chip including an inorganic protective film, the third semiconductor chip being electrically connected to the second semiconductor chip through the re-wiring layer and a bump connection, a first resin layer filled between the first semiconductor chip and the second semiconductor chip, the first resin layer being in contact with the inorganic protective film, and a second resin layer filled between the second semiconductor chip and the third semiconductor chip, the second resin layer being in contact with the organic protective film and the inorganic protective film.

Abstract: A semiconductor device package is provided. The package can include a stack of semiconductor dies over a substrate, the substrate including a plurality of electrical contacts, and an annular interposer disposed over the substrate and surrounding the stack of semiconductor dies. The annular interposer can include a plurality of circuit elements each electrically coupled to at least a corresponding one of the plurality of electrical contacts. The package can further include a lid disposed over the annular interposer and the stack of semiconductor dies.

Abstract: A semiconductor memory package includes a base layer that communicates with a memory controller; at least one memory layer that is stacked on the base layer; and at least one through silicon via that penetrates through the at least one memory layer, wherein at least one signal bump for exchanging a signal with the memory controller is disposed in a first area of the base layer located to be adjacent to the memory controller, and wherein the first area corresponds to an edge area of the base layer, and a power bump for receiving power from outside of the semiconductor memory package for performing a signal processing operation on the signal is disposed in a second area of the base layer contacting the at least one through silicon via, wherein the second area corresponds to an area other than edge areas of the base layer.

Abstract: A semiconductor package device includes a substrate, an electronic component disposed on the substrate, and a package body. The electronic component has a first surface adjacent to the substrate and a second surface opposite to the first surface. The second surface has at least five edges, and the package body encapsulates the electronic component and exposes the second surface of the electronic component.

Abstract: Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the stack. In one embodiment, the thermal pads may be in direct contact with the semiconductor dies. Heat dissipation of the semiconductor die stack can be improved by a relatively high thermal conductivity of the thermal pads that directly contact the adjacent silicon dies in the stack without the intervening layers of the low thermal conductivity materials (e.g., passivation materials). In some embodiments, the manufacturing yield of the stack can be improved by having generally coplanar top surfaces of the thermal pads and under-bump metallization (UBM) structures.

Abstract: An illumination assembly includes a substrate, a wiring structure, a reflecting layer and a plurality of light-emitting diodes. The wiring structure is formed on a part of the substrate, and includes a catalyst layer covering the part of the substrate, and a conducting layer formed on the catalyst layer. The reflecting layer is formed on another part of the substrate that is exposed from the wiring structure. The light-emitting diodes are disposed on the wiring structure and are electrically connected to the wiring structure.

Abstract: A light emitting module according to an embodiment includes a first insulation film with a light transmissivity, a second insulation film disposed so as to face the first insulation film, a first double-sided light emitting element disposed between the first insulation film and the second insulation film, and including a pair of electrodes on one surface, a second double-sided light emitting element disposed between the first insulation film and the second insulation film adjacent to the first double-sided light emitting element, comprising a pair of electrodes on one surface, and emitting different light from the first double-sided light emitting element, and a conductor pattern formed on a surface of the first insulation film, and connected to the respective electrodes of the first double-sided light emitting element and the second double-sided light emitting element.

Abstract: Presented herein is a method and apparatus for enhanced power distribution to application specific integrated circuits (ASICs). The apparatus includes a substrate, an ASIC, and a voltage regulator module. The substrate includes a first side, a second side, and a vertical interconnect access (via) extending between the first side and the second side. The ASIC is mounted on the first side of the substrate in alignment with the via. The voltage regulator module is mounted on the second side of the substrate in alignment with the via so that the voltage regulator module is electrically coupled to the ASIC through the via.

Abstract: The present invention relates to a compound semiconductor integrated circuit chip having a front and/or back surface metal layer used for electrical connection to an external circuit. The compound semiconductor integrated circuit chip (first chip) comprises a substrate, an electronic device layer, and a dielectric layer. A first metal layer is formed on the front side of the dielectric layer, and a third metal layer is formed on the back side of the substrate. The first and third metal layer are made essentially of Cu and used for the connection to other electronic circuits. A second chip may be mounted on the first chip with electrical connection made with the first or the third metal layer that extends over the electronic device in the first chip in the three-dimensional manner to make the electrical connection between the two chips having connection nodes away from each other.

Abstract: In order to produce a power semiconductor module, a circuit carrier is populated with a semiconductor chip and with an electrically conductive contact element. After populating, the semiconductor chip and the contact element are embedded into a dielectric embedding compound, and the contact element is exposed. In addition, an electrically conductive base layer is produced which electrically contacts the exposed contact element and which bears on the embedding compound and the exposed contact element. A prefabricated metal film is applied to the base layer by means of an electrically conductive connection layer.

Abstract: A method of manufacturing a light emitting element includes forming a resin film including a phosphor containing layer on a transparent board side surface of a wafer including a transparent board and a plurality of light emitting parts formed on the transparent board, forming a scribing line along a scheduled separation surface in a surface of the transparent board by scribing before or after forming the resin film, cutting the resin film along the scheduled separation surface before or after forming the scribing line, and separating the transparent board along the scheduled separation surface by breaking after forming the scribing line and cutting the resin film.

Abstract: An LED display module is disclosed. The LED display module includes: an active matrix substrate including a plurality of control units; a plurality of pairs of solder bumps arranged in a matrix on the active matrix substrate by transfer printing; a plurality of LED chips including pairs of electrodes connected to the corresponding plurality of pairs of solder bumps and arranged in a matrix on the active matrix substrate by transfer printing; grid barriers formed on the active matrix substrate to isolate the plurality of LED chips into individual chip units; and a multi-color cell layer including a plurality of color cells and aligned with the active matrix substrate such that the plurality of color cells match the plurality of LED chips in a one-to-one relationship. The plurality of color cells include first color cells, second color cells, and third color cells disposed consecutively in one direction.

Abstract: Diode structures and methods of fabricating diode structures. First and second gate structures are formed with the second gate structure arranged parallel to the first gate structure. First and second fins are formed that extend vertically from a top surface of a substrate. The first and second fins are arranged between the first gate structure and the second gate structure. A contact structure is coupled with the first fin and the second fin. The contact structure is laterally arranged between the first gate structure and the second gate structure.

Abstract: A transient voltage suppressing (TVS) device formed in an epitaxial layer of a first conductivity type supported on a semiconductor substrate. The TVS device further comprises a plurality of contact trenches opened and extended to a lower part of the epitaxial layer filled with a doped polysilicon layer of a second conductivity type wherein the trenches are further surrounded by a heavy dopant region of the second conductivity type. The TVS device further includes a metal contact layer disposed on a top surface of the epitaxial layer electrically connected to a Vcc electrode wherein the metal contact layer further directly contacting the doped polysilicon layer and the heavy dopant region of the second conductivity type.

Abstract: A method comprises forming an active region including a first fin and a second fin over a substrate, wherein the first fin and the second fin are separated by an isolation region, depositing an epitaxial growth block layer over the active region, patterning the epitaxial growth block layer to define a first growth area and a second growth area and growing an N+ region in the first growth area and a P+ region in the second growth area.

Abstract: In conventional sensor devices, it has been difficult to achieve both EMC resistance and ESD resistance, which are required at the output terminals of an automobile sensor device. A sensor device 1 of the present embodiment comprises: a power supply terminal 2 that supplies power; a ground terminal 3; a sensor element 4, the electrical characteristics of which change in accordance with a physical quantity; a signal processing integrated circuit 5 that processes an output signal output from the sensor element 4; and an output terminal that outputs the output signal processed by the signal processing integrated circuit 5.

Abstract: In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.

Abstract: An OLED panel having a plurality of OLED circuit elements is provided. Each OLED circuit element may include a fuse or other component that can be ablated or otherwise opened to render the component essentially non-conductive. Each OLED circuit element may comprise a pixel that may include a first electrode, a second electrode, and an organic electroluminescent (EL) material disposed between the first and the second electrodes. Each of the OLED circuit elements may not be electrically connected in series with any other of the OLED circuit elements.

Abstract: Diffusion regions having the same conductivity type are arranged on a side of a second wiring and a side of a third wiring, respectively under a first wiring connected to a signal terminal. Diffusion regions are separated in a whole part or one part of a range in a Y direction. That is, under first wiring, diffusion regions are only formed in parts opposed to diffusion regions formed under the second wiring and third wiring connected to a power supply terminal or a ground terminal, and a diffusion region is not formed in a central part in an X direction. Therefore, terminal capacity of the signal terminal can be reduced without causing ESD resistance to be reduced, in an ESD protection circuit with the signal terminal.

Abstract: A display panel includes: an electrostatic discharge (ESD) protection circuit area in a peripheral area surrounding a display area including pixels, the ESD protection circuit area including ESD protection circuits; a fan-out area in the peripheral area, including fan-out lines to receive data signals and a first pad to receive a first global signal; a common line area between the ESD protection circuit area and the fan-out area, including a first common line extending lengthwise in a pixel row direction; a first transmission line connecting lengthwise from the first pad to the first common line to transmit the first global signal to the first common line; and first global signal lines extending lengthwise in a pixel column direction from the first common line to the display area to concurrently transmit the first global signal to the pixels. The first transmission line is wider than the first global signal lines.

Abstract: At least one method, apparatus and system disclosed involves an antenna diode design for a semiconductor device. A first common diode operatively coupled to a ground node and to a p-well layer serving as an isolated p-well that is formed over a deep n-well that is adjacent to an n-well in a semiconductor device is provided. A first antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a first signal line of the semiconductor device is provided for discharging accumulated charges on the first signal line. A second antenna diode formed on the isolated p-well operatively coupled to the p-well layer and operatively coupled to a second signal line of semiconductor device is provided for discharging accumulated charges on the second signal line.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a first source region, a second source region, a first drain region, and a second drain region. The semiconductor device structure includes a first gate structure over the substrate and between the first source region and the first drain region. The semiconductor device structure includes a second gate structure over the substrate and between the second source region and the second drain region. A first thickness of the first gate structure is greater than a second thickness of the second gate structure. A first gate width of the first gate structure is less than a second gate width of the second gate structure.

Abstract: A semiconductor device and a method for fabricating the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, a gate structure including a gate dielectric layer and a first gate electrode layer, and a second gate electrode layer. In the method for fabricating the semiconductor device, at first, the semiconductor substrate is provided. The semiconductor substrate includes fin portions. Then, a gate dielectric layer is formed on the fin portions. Thereafter, a first gate electrode layer is formed on the gate dielectric layer. Then, the first gate electrode layer is etched. Thereafter, a second electrode layer is formed on the first gate electrode layer. Therefore, the gate electrode layer formed on the gate dielectric layer is regrown with easy control.

Abstract: Methods for fabricating Fin field effect transistors (FinFETs) are disclosed. First and second semiconductor fins and an insulator therebetween are formed. First and second dummy gates and an opening therebetween over the insulator are formed, wherein the first and second dummy gates cross over the first and second semiconductor fins respectively. A first dielectric material with an air gap therein is formed in the opening. A portion of the first dielectric material is removed to expose the air gap, so as to form a first dielectric layer with a slit therein. The first and second dummy gates are removed. A second dielectric layer is formed to fill the slit. First and second gates are formed to cross over portions of the first and second semiconductor fins respectively, wherein the first and second gates are electrically insulated from each other by the first dielectric layer including the second dielectric layer.

Abstract: Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.