Abstract: An apparatus for radiatively scribing a planar semiconductor substrate along a scribelane that extends between opposing rows of semiconductor devices on a target surface of the substrate. The scribelane extends parallel to a first direction parallel to a second direction, these first and second directions lying respectively parallel to X and Y axes of a Cartesian coordinate system. Such an apparatus may include an illuminator for producing an array of light beams; a projection system for focusing the light beams onto the target surface; an actuator system for causing relative displacement of a substrate holder with respect to light beams parallel to an XY plane; and an adjustable spatial filter located between the illuminator and the substrate holder, and including motorized plates whose position is adjustable so as to at least partially block selectable light beams of the light beam array.

Abstract: A substrate processing method of the present disclosure includes forming a film on a workpiece using a processing gas in a processing chamber with a setting temperature profile including increase or decrease of a temperature; and etching the film. An etching rate of the film in the etching depends on a film formation temperature in the forming. The setting temperature profile is determined based on a first temperature dependence of the etching rate in the etching on the film formation temperature, and a second temperature dependence of a film formation amount in the forming on the film formation temperature.

Abstract: The present invention discloses apparatuses and methods for simultaneous viewing and reading top and bottom images from a workpiece. The present ID reader can comprise an enclosure covering a top and bottom section of the workpiece with optical elements to guide the light from the workpiece images to a camera. The optical element can be disposed to receive images from a high angle with respect to the surface of the workpiece. The present ID reader can further comprise a light source assembly to illuminate the image. The light source assembly can utilize a coaxial light path with the images, preferably for bright field illumination. The light source assembly can also utilize a non-coaxial light path, preferably for dark field illumination.

Abstract: A maintenance method of a substrate processing apparatus includes a first processing step of carrying a first substrate holder holding a substrate into a process chamber and processing the substrate held by the first substrate holder within the process chamber, a second processing step of carrying a second substrate holder holding a substrate into the process chamber and processing the substrate held by the second substrate holder within the process chamber, a determination step of determining a replacement timing of the first substrate holder and the second substrate holder, and a maintenance step of, at the replacement timing determined at the determination step, replacing the first substrate holder and the second substrate holder respectively with a third substrate holder and a fourth substrate holder, if at least one of the first substrate holder and the second substrate holder reaches the replacement timing.

Abstract: An example clamping assembly tray for packaging a semiconductor device includes a frame having a bottom surface and side walls extending from the bottom surface that define a cavity; and a compressible member disposed on the bottom surface of the frame within the cavity, where a top portion of the compressible member provides a support surface for supporting the semiconductor device, the support surface being between the bottom surface and a top edge of the side walls.

Abstract: The present invention provides a stopper for a substrate cassette and a substrate cassette assembly, belonging to the technical field of manufacturing of display devices, which can solve the problem that an existing substrate cassette easily damages a substrate. The stopper for the substrate cassette of the present invention is strip-shaped, and arranged, in a length direction, on an inner side of a mullion of the substrate cassette; the stopper has a contact surface configured to contact the mullion of the substrate cassette and an exposed surface opposite to the contact surface, and the exposed surface, at least on a side facing the outside of the substrate cassette, is a convex cambered surface.

Abstract: A method for managing an atmosphere in a storage container in a processing apparatus including a substrate transfer region and a container transfer region which are partitioned by a partition wall; a load port; a container keeping rack; and a cover opening/closing mechanism, includes substituting the internal atmosphere of the storage container that stores non-processed substrates with the inert gas for using the cover opening/closing mechanism; transferring the storage container of which the internal atmosphere has been substituted with the inert gas, to the container keeping rack and placing and keeping the storage container on the container keeping rack; and putting the storage container on standby on the container keeping rack while maintaining the atmosphere substituted with the inert gas.

Abstract: A wafer cassette includes a case, a plurality of wafer trays, and a plurality of transmission mechanisms. The wafer trays are disposed in the case. Each of the wafer trays includes a central opening, a first groove, and a second groove. The diameter of the second groove is greater than that of the first groove. A bottom surface of the second groove is higher than that of the first groove. The first and second grooves surround the central opening. Each of the transmission mechanisms is connected to the corresponding wafer tray to move the wafer tray between a pick-up position and a received position. Since the wafer tray has grooves with different diameters, the wafer tray is capable of receiving wafers with different sizes.

Abstract: A temperature controller for a substrate processing system includes an interface configured to receive a processing temperature corresponding to a desired processing temperature of a substrate. The temperature controller includes a thermal control element controller configured to selectively control a thermal control element to adjust a temperature of a substrate support. The thermal control element controller is further configured to, prior to the substrate being loaded onto the substrate support, determine at least one of a temperature of the substrate support and a temperature of the substrate and, based on the processing temperature and the at least one of the temperature of the substrate support and the temperature of the substrate, control the thermal control element to adjust the temperature of the substrate support to a setpoint temperature that is different than the processing temperature.

Abstract: In various aspects of the disclosure, a semiconductor substrate processing system may include an electrostatic chuck for holding a semiconductor substrate attached to an electrically insulating carrier; and an AC power supply electrically coupled to the electrostatic chuck.

Abstract: In various embodiments, an assembly for handling a semiconductor die is provided. The assembly may include a carrier with a surface. The assembly may also include an adhesive tape fixed to the surface of the carrier. The adhesive tape may be configured to adhere to the semiconductor die. The adhesive tape may include adhesive, the adhesion of which can be reduced by means of electromagnetic waves. The assembly may further include an electromagnetic source configured to apply electromagnetic waves to the adhesive tape to reduce adhesion of the adhesive tape to the semiconductor die. The assembly may additionally include a die pick-up component configured to pick up the semiconductor die from the adhesive tape.

Abstract: Embodiments disclosed herein generally relate to a substrate carrier system suitable for clamping a substrate and optionally a mask, the substrate carrier system having a stack of removable protective layers. In one embodiment, substrate carrier system is provide that includes a substrate carrier body having a protective layer stack disposed an outer mounting surface of the substrate carrier body. The substrate carrier body is configured to be transported into and out of a processing chamber. The protective layer stack has a plurality of removable protective layers which can be removed as needed to expose a “new” surface for chucking a substrate thereon.

Abstract: To provide a semiconductor device having improved performance. The semiconductor device has a first insulating film formed on the main surface of a semiconductor substrate and a second insulating film formed on the first insulating film. The semiconductor device further has a first opening portion penetrating through the second insulating film and reaching the first insulating film, a second opening portion penetrating through the first insulating film and reaching the semiconductor substrate, and a trench portion formed in the semiconductor substrate. A first opening width of the first opening portion and a second opening width of the second opening portion are greater than a trench width of the trench portion. The trench portion is closed by a third insulating film while leaving a space in the trench portion.

Abstract: According to various embodiments, a carrier may be provided, the carrier including: a hollow chamber spaced apart from a surface of the carrier; a trench structure extending from the surface of the carrier to the hollow chamber and laterally surrounding a first region of the carrier, the trench structure including one or more trenches extending from the surface of the carrier to the hollow chamber, and one or more support structures intersecting the one or more trenches and connecting the first region of the carrier with a second region of the carrier outside the trench structure, wherein the one or more support structures including an electrically insulating material.

Abstract: Implementations described herein relate to methods for forming gap fill materials. After the gap fill material is deposited and before a CMP process is performed on the gap fill material, one or more ion implantation processes are utilized to treat the deposited gap fill material. The one or more ion implantation processes include implanting a first ion species in the gap fill material using a first ion energy, and then implanting a second ion species in the gap fill material using a second ion energy that's lower than the first ion energy. The one or more ion implantation processes minimize CMP dishing and improve recess profile.

Abstract: An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a reaction chamber and depositing a barrier layer over the substrate. The barrier layer includes a metal and a non-metal and the barrier layer exhibits an as-deposited thickness of 4 nm or less. The method further includes densifying the barrier layer by forming plasma from a gas proximate to said barrier layer and reducing the thickness and increasing the density of the barrier layer. In embodiments, during densification 300 Watts or less of power is applied to the plasma at a frequency of 350 kHz to 40 MHz.

Abstract: Methods for filing a feature on a substrate surface comprising depositing a conformal nitride film on the substrate surface and at least one feature on the surface, oxidizing a portion of the nitride film to form an asymmetric oxide film on top of the nitride film and etching the oxide film from the nitride film to leave a v-shaped nitride film in the at least one feature.

Abstract: A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element. The first substrate includes a dielectric block in the first substrate; and a plurality of first conductive features formed in first inter-metal dielectric layers over the first substrate. The stacked IC device also includes a second semiconductor element bonded on the first semiconductor element. The second semiconductor element includes a second substrate and a plurality of second conductive features formed in second inter-metal dielectric layers over the second substrate. The stacked IC device also includes a conductive deep-interconnection-plug coupled between the first conductive features and the second conductive features. The conductive deep-interconnection-plug is isolated by dielectric block, the first inter-metal-dielectric layers and the second inter-metal-dielectric layers.

Abstract: Embodiments of the disclosure generally relate to a method of improving quality of a barrier layer suitable for forming high aspect ratio through substrate vias. In one example, a method for depositing a barrier layer includes depositing a barrier layer in a hole formed in a substrate, exposing the deposited barrier layer to a processing gas at a pressure greater than about 2 bars, and, maintaining a temperature of the substrate between about 150 degrees and about 700 degrees Celsius while in the presence of the processing gas.

Abstract: Disclosed herein is a wafer processing method for dividing a wafer into individual device chips along division lines. The wafer processing method includes a frame supporting step of attaching the wafer to an adhesive tape fixed at its peripheral portion to an annular frame, thereby supporting the wafer through the adhesive tape to the annular frame, a laser processing step of applying a laser beam to each division line to thereby form a strength reduced portion along each division line, and a dividing step of applying a radial tension to the adhesive tape and next applying an external force to the wafer in the condition where the radial tension is kept acting on the adhesive tape, thereby dividing the wafer into the individual device chips along the division lines.

Abstract: Semiconductor structure and fabrication method thereof are provided. An exemplary method includes providing a semiconductor substrate including a plurality of first fin structures, each having a first width, and a plurality of second fin structures, each having a second width greater than the first width. The method further includes forming a first isolation film covering sidewall surfaces of the first fin structures and the second fin structures, forming a trench in the first isolation film to expose at least a top portion of at least one sidewall surface of one or more second fin structures, forming an isolation fluid layer to fill the trenches, and performing an oxygen annealing process to convert a surface layer of the top portion of the at least one sidewall surface of the one or more second fin structures into a by-product layer, and to convert the isolation fluid layer into a second isolation film.

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract: A double sidewall image transfer process for forming FinFET structures having a fin pitch of less than 40 nm generates paired fins with a spacing determined by the width of a sidewall spacer that forms a second mandrel. Here, the fin pairs are created at two different spacings without requiring the minimum space for the standard sidewall structure. An enlarged space between paired fins is created by placing two first mandrel shapes close enough so as to overlap or merge two sidewall spacer shapes so as to form a wider second mandrel upon further processing. The fin pair created from the wider second mandrel is spaced at about 2 times the fin pair created from the narrower second mandrel. For some circuits, such as an SRAM bitcell, the wider second mandrel can be utilized to form an inactive fin not utilized in the circuit structure, which can be removed. In some embodiments, all dummy inactive fins are eliminated for a simpler process.

Abstract: The present disclosure relates to a method of forming an integrated chip having middle-of-the-line (MOL) structures arranged at an irregular pitch, and an associated method of formation. In some embodiments, the integrated chip has a well region with a plurality of source/drain regions. A plurality of gate structures are arranged over the well region at a regular pitch. A plurality of middle-of-the-line (MOL) structures are laterally interleaved between some of the plurality of gate structures and are arranged over the well region at an irregular pitch having a first pitch that is larger than the regular pitch. Since the MOL structures have an irregular pitch with a first pitch that is larger than the regular pitch, one or more of the plurality of gate structures are spaced apart from a closest gate or MOL structure by a space that reduces parasitic capacitance.

Abstract: A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are formed over a substrate. Dielectric layer is formed to cover the first and second conductive structures. Hard mask layer is formed over the dielectric layer. The hard mask layer covers the dielectric layer over the first conductive structure, and the hard mask layer has an opening exposing the dielectric layer over the second conductive structure. The dielectric layer exposed by the hard mask layer is etched to reduce thickness of the dielectric layer. The hard mask layer is removed. The dielectric layer is etched to form first main spacer on sidewall of the first conductive structure and second main spacer on sidewall of the second conductive structure. A first width of the first main spacer is greater than a second width of the second main spacer.

Abstract: Methods are provided for fabricating semiconductor fins having uniform profiles. For example, a method includes forming semiconductor fins on a substrate, including a first semiconductor fin disposed in a first device region, and a second semiconductor fin disposed in a second device region. The first and second semiconductor fins are formed of different types of semiconductor material, and are initially formed to have different widths and heights. A semiconductor fin trimming process is performed, which is selective to the semiconductor material of the second semiconductor fin, so that the fin trimming process results in the formation of semiconductor fins having substantially equal heights and equal widths across the device regions as a result of the fin trimming process. The semiconductor fins in different device regions are initially formed with non-uniform profiles (e.g., differential heights and widths) to compensate for micro-loading and etch rate variations during the fin trimming process.

Abstract: A semiconductor device includes a gate structure disposed over a substrate, and sidewall spacers disposed on both side walls of the gate structure. The sidewall spacers includes at least four spacer layers including first to fourth spacer layers stacked in this order from the gate structure.

Abstract: A bonding method of a die bonder with a single conveyance lane and a single bonding head, or a plurality of conveyance lanes and a plurality of bonding heads includes the steps of generating a classification map of class dies with different electric properties on the wafer, which are classified in accordance with a plurality of grades, picking up the die from the wafer, bonding the die onto a substrate or the die using a bonding head, conveying a class substrate corresponding to the class die on the conveyance lane in a unit of the class substrate, and further bonding the class die to the corresponding class substrate based on the classification map.

Abstract: A system and method for performing corrective processing of a workpiece is described. The system and method includes receiving a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, and receiving a second set of parametric data from a second source different than the first source that diagnostically relates to at least a second portion of the microelectronic workpiece. Thereafter, a corrective process is generated, and a target region of the microelectronic workpiece is processed by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.

Abstract: A method for critical dimension control in which a substrate is received having an underlying layer and a patterned layer formed on the underlying layer, the patterned layer including radiation-sensitive material and a pattern of varying elevation with a first critical dimension. The method further includes applying an overcoat layer over the patterned layer, the overcoat layer containing a photo agent selected from a photosensitizer generator compound, a photosensitizer compound, a photoacid generator compound, a photoactive agent, an acid-containing compound, or a combination of two or more thereof. The overcoat layer is then exposed to electromagnetic radiation, wherein the dose of electromagnetic radiation applied to different regions of the substrate is varied, and then the overcoat layer and patterned layer are heated. The method further includes developing the overcoat layer and the patterned layer to alter the first critical dimension of the patterned layer to a second critical dimension.

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of via opens, and the second DOE contains fill cells configured to enable NC detection of metal island opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of merged-via opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

Abstract: A semiconductor device includes semiconductor body region and a surface region, the semiconductor body region including a first conductivity type first semiconductor region type and a second conductivity type second semiconductor region.

Abstract: A process for encapsulating an apparatus to restrict environmental element permeation between the apparatus and an external environment includes applying multiple barrier layers to the apparatus and preceding each layer application with a separate cleaning of the presently-exposed apparatus surface, resulting in an apparatus which includes an encapsulation stack, where the encapsulation stack includes a multi-layer stack of barrier layers. Each separate cleaning removes particles from the presently-exposed apparatus surface, exposing gaps in the barrier layer formed by the particles, and the subsequently-applied barrier layer at least partially fills the gaps, so that a permeation pathway through the encapsulation stack via gap spaces is restricted. The quantity of barrier layers applied to form the stack can be based on a determined probability that a stack of the particular quantity of barrier layers is independent of at least a certain quantity of continuous permeation pathways through the stack.

Abstract: Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink.

Abstract: Packaged semiconductor die and CTE-engineering die pairs and methods to form packaged semiconductor die and CTE-engineering die pairs are described. For example, a semiconductor package includes a substrate. A semiconductor die is embedded in the substrate and has a surface area. A CTE-engineering die is embedded in the substrate and coupled to the semiconductor die. The CTE-engineering die has a surface area the same and in alignment with the surface area of the semiconductor die.

Abstract: Various technologies presented herein relate to forming one or more heat dissipating structures (e.g., heat spreaders and/or heat sinks) on a substrate, wherein the substrate forms part of an electronic component. The heat dissipating structures are formed from graphene, with advantage being taken of the high thermal conductivity of graphene. The graphene (e.g., in flake form) is attached to a diazonium molecule, and further, the diazonium molecule is utilized to attach the graphene to material forming the substrate. A surface of the substrate is treated to comprise oxide-containing regions and also oxide-free regions having underlying silicon exposed. The diazonium molecule attaches to the oxide-free regions, wherein the diazonium molecule bonds (e.g., covalently) to the exposed silicon. Attachment of the diazonium plus graphene molecule is optionally repeated to enable formation of a heat dissipating structure of a required height.

Abstract: Embodiments of the present invention are directed to heat transfer arrays, cold plates including heat transfer arrays along with inlets and outlets, and thermal management systems including cold-plates, pumps and heat exchangers. These devices and systems may be used to provide thermal management or cooling of semiconductor devices and particularly such devices that produce high heat concentrations. The heat transfer arrays may include microjets, microchannels, fins, and even integrated microjets and fins. Other embodiments of the invention are directed to heat spreaders (e.g. heat pipes or vapor chambers) that provide enhanced thermal management via enhanced wicking structures and/or vapor creation and flow structures. Other embodiments provide enhanced methods for making such arrays and spreaders.

Abstract: A power device comprises at least one power semiconductor module comprising a wide bandgap semiconductor element; and a cooling system for actively cooling the wide bandgap semiconductor element with a cooling medium, wherein the cooling system comprises a refrigeration device for lowering a temperature of the cooling medium below an ambient temperature of the power device; wherein the cooling system is adapted for lowering the temperature of the cooling medium in such a way that a temperature of the wide bandgap semiconductor element is below 100° C.

Abstract: A lead frame includes: a resin portion including an upper surface and a lower surface opposite to the upper surface; and a first terminal formed to penetrate the resin portion. The first terminal includes: a first upper terminal portion disposed to protrude from the upper surface; a first lower terminal portion disposed on the first upper terminal portion to protrude from the lower surface; a first through hole formed in one of the first upper terminal portion and the first lower terminal portion; a first recess defined by an inner wall surface of the first through hole and a surface of the other of the first upper terminal portion and the first lower terminal portion; and a first metal layer formed on an inner surface of the first recess.

Abstract: A semiconductor device has a semiconductor die with an insulation layer formed over an active surface of the semiconductor die. A conductive layer is formed over the first insulating layer electrically connected to the active surface. A plurality of conductive pillars is formed over the conductive layer. A plurality of dummy pillars is formed over the first insulating layer electrically isolated from the conductive layer and conductive pillars. The semiconductor die is mounted to a substrate. A height of the dummy pillars is greater than a height of the conductive pillars to maintain the standoff distance between the semiconductor die and substrate. The dummy pillars can be formed over the substrate. The dummy pillars are disposed at corners of the semiconductor die and a central region of the semiconductor die. A mold underfill material is deposited between the semiconductor die and substrate.

Abstract: A substrate structure is provided, which includes: a substrate body having a first surface and a second surface opposite to the first surface; and a plurality of conductive posts disposed on the first surface of the substrate body and electrically connected to the substrate body. By replacing conventional through silicon vias (TSVs) with the conductive posts, the present disclosure greatly reduces the fabrication cost. The present disclosure further provides an electronic package having the substrate structure and a method for fabricating the electronic package.

Abstract: A substrate includes a first dielectric structure, a first circuit layer, a second dielectric structure and a second circuit layer. The first circuit layer is embedded in the first dielectric structure, and does not protrude from a first surface of the first dielectric structure. The second dielectric structure is disposed on the first surface of the first dielectric structure. The second circuit layer is embedded in the second dielectric structure, and is electrically connected to the first circuit layer. A first surface of the second circuit layer is substantially coplanar with a first surface of the second dielectric structure, and a surface roughness value of a first surface of the first circuit layer is different from a surface roughness value of the first surface of the second circuit layer.

Abstract: The present invention provides a semiconductor capacitor structure. The semiconductor capacitor structure comprises a first metal layer, a second metal layer and a first dielectric layer. The first metal layer is arranged to be a part of a first electrode of the semiconductor capacitor structure, and the first metal layer comprises a first portion and a second portion. The first portion is formed to have a first pattern, and the second portion is connected to the first portion. The second metal layer is arranged to be a part of a second electrode of the semiconductor capacitor structure, and the first dielectric layer is formed between the first metal layer and the second metal layer.

Abstract: The present disclosure provides an interconnect structure for a semiconductor device. The interconnect structure includes a first metal layer that contains a first metal line. The interconnect structure includes a dielectric layer located over the first metal layer. The dielectric layer contains a first sub-via electrically coupled to the first metal line and a second sub-via electrically coupled to the first sub-via. The second sub-via is different from the first sub-via. The interconnect structure includes a second metal layer located over the dielectric layer. The second metal layer contains a second metal line electrically coupled to the second sub-via. No other metal layer is located between the first metal layer and the second metal layer.

Abstract: There is provided an image capturing apparatus including a pixel circuit that generates a pixel signal based on an electric charge generated by photoelectric conversion and a logic circuit that outputs a signal based on the pixel signal. The image capturing apparatus includes a first contact plug connected to a source or a drain of a first transistor constituting the pixel circuit and a second contact plug connected to a source or a drain of a second transistor constituting the logic circuit. A diameter of the first contact plug is smaller than a diameter of the second contact plug.

Abstract: A semiconductor device includes a substrate including PMOSFET and NMOSFET regions, a first gate structure extending in a first direction and crossing the PMOSFET and NMOSFET regions, and a gate contact on and connected to the first gate structure, the gate contact being between the PMOSFET and NMOSFET regions, the gate contact including a first sub contact in contact with a top surface of the first gate structure, the first sub contact including a vertical extending portion extending vertically toward the substrate along one sidewall of the first gate structure, and a second sub contact spaced apart from the first gate structure, a top surface of the second sub contact being positioned at a same level as a top surface of the first sub contact.

Abstract: One embodiment is a semiconductor device including: at least one patterned dielectric layer having at least one opening therein, said at least one opening having sidewalls and bottom; at least one barrier layer disposed over the sidewalls and bottom; a first metallic layer disposed over the at least one barrier layer; a second metallic layer disposed over the first metallic layer; and a metallic filling layer disposed over the second metallic layer; wherein: the first metallic layer is continuous over the sidewalls and bottom, has a thickness in a range from about 10 ? to no more than 40 ? over a sidewall of the at least one opening; and the second metallic layer, and the metallic filling layer are selected from a group consisting of Cu, Ag, and alloys containing one or more of these metals.

Abstract: In a Cu wiring manufacturing method, a MnOx film which becomes a self-formed barrier film by reaction with an interlayer insulating film of a substrate is formed on a surface of a recess formed in the interlayer insulating film by ALD. A hydrogen radical process is performed on a surface of the MnOx film to reduce the surface of the MnOx film. A Ru film is formed by CVD on the surface of the MnOx film which has been reduced by the hydrogen radical process. A Cu-based film is formed on the Ru film by PVD to be filled in the recess. When the Ru film is formed, a film-formation condition of the MnOx film and a condition of the hydrogen radical process are set such that nucleus formation is facilitated and the Ru film is formed in a state where a surface smoothness is high.