Abstract: Low precision computers can be efficient at finding possible answers to search problems. However, sometimes the task demands finding better answers than a single low precision search. A computer system augments low precision computing with a small amount of high precision computing, to improve search quality with little additional computing.

Abstract: A processor and method for performing outer product and outer product accumulation operations on vector operands requiring large numbers of multiplies and accumulations is disclosed.

Abstract: A method of calculating data includes acquiring a difference between first data that is input and second data that was previously stored; determining a method of generating third data corresponding to a result of a calculation of the first data based on the difference; and performing a calculation corresponding to the determined method using a calculator.

Abstract: Methods and leading zero anticipators for estimating the number of leading zeros in a result of a fixed point arithmetic operation which is accurate to within one bit for any signed fixed point numbers. The leading zero anticipator includes an input encoding circuit which generates an encoded input string from the fixed point numbers; a window-based surrogate string generation circuit which generates a surrogate string whose leading one is an estimate of the leading one in the result of the arithmetic operation by examining consecutive windows of the encoded input string and setting corresponding bits of the surrogate string based on the examinations; and a counter circuit configured to estimate the number of leading zeros in the result of the arithmetic operation based on the leading one in the surrogate string.

Abstract: This disclosure relates generally to software development, and more particularly to a system and method for representing software development requirements into standard diagrams. In one embodiment, a method is provided for deriving use case diagrams for software development. The method comprises extracting one or more core components from each of a plurality of software development requirements, determining at least one activity from the one or more core components, extracting at least one of a class and an attribute from the one or more core components, and deriving at least one use case diagram based on the at least one activity and the at least one of the class and the attribute. The one or more core components comprise at least one of a core message and a condition.

Abstract: According to at least one aspect, a system for collecting computer usage information is provided. The system includes a hardware processor, a display coupled to the hardware processor to display a user interface, and a computer-readable storage medium storing processor-executable instructions that cause the hardware processor to receive an indication of an action being performed by a user on the system, cause the system to wait before updating the user interface in response to the action performed by the user, gather contextual information associated with the action while the system is waiting to process the action performed by the user to update the user interface, cause the system to update the user interface in response to the action performed by the user after gathering the contextual information, and store information indicative of the action and the contextual information.

Abstract: A method for domain specific language design includes, with a physical computing system, receiving from a user, a number of annotations for at least one of a set of statements within a problem domain, the annotations identifying a set of elements within the statement. The method further includes forming a set of grammar rules for the problem domain based on the annotations, and parsing the set of statements using the set of grammar rules.

Abstract: Multiple different type hierarchies can communicate in a high performance and seamless manner by sharing a GC and interface dispatch logic. A runtime environment can support multiple independent type hierarchies, each type hierarchy defined by the module which defines the root of a type graph and some other helper functionality. Code that uses the dispatch logic has to follow certain rules in order to maintain GC and type safety. Different types in disjoint type graphs can behave as if they were one type for cross type graph communication purposes.

Abstract: Embodiments of the present invention provide a system for the utilization of a robotic process automation system for functional evaluation and improvement of back end instructional constructs. The system may scan a set of code to identify an exception comprising an exception tag and an exception string located at a first location within the set of code. The system may then transmit the set of code and the identified exception to a robotic process automation system, along with instructions for the robotic process automation system to compare the exception tag and exception string to a replacement code database to identify an exception string. The robotic process automation system can then replace the exception string in the set of code with the identified replacement string.

Abstract: A system has a domain expert component library stored on a computer readable storage device, the component library containing connectable components that create a mobile workflow based application; a domain expert user interface coupled to the domain expert component library to facilitate assembly of components in a workflow sequence; and a developer user interface coupled to: receive an intermediate representation of a workflow application based on the workflow sequence, and provide a software programming language environment to perform data manipulation changes to the intermediate representation to create the mobile workflow based application.

Abstract: A method for realizing reuse among software development tasks is provided. The method includes receiving information data of a completed software development task, and generating a first identification corresponding to the software development task. The method includes receiving program code corresponding to the completed software development task and the first identification, and generating one or more second identifications of the program code.

Abstract: Described is a technique for creating and displaying adaptive user interfaces. The user interface may be provided to an application development environment that provides the ability to allow authoring of a user interface that adapts to a screen size with any first abstracted size class value and any second abstracted size class value. Accordingly, an application that includes the user interface may determine a screen size of a device and adapt the user interface according to the screen size including the first abstracted size clasp value and the second abstracted size class value. Thus, a developer may efficiently develop a user interface based on various abstracted size class values that may be adapted to a particular device.

Abstract: A method of producing launchers for a mobile terminal is disclosed. The method includes: obtaining launcher main code having an architecture of at least two launchers; extracting form the launcher main code a corresponding first parsed XML file and first macro definition .inc file of each of the at least two launchers, and generating a second XML file using the attribute information of all applications in the launcher main code; customizing the first XML file and first .inc file of each launcher and the second XML file to obtain a corresponding second .inc file of the launcher; generating a corresponding third XML file of each of the at least two launchers using the corresponding second .inc file and first XML file of the launcher; and compiling the corresponding third XML file to obtain the at least two launchers. A system for producing launchers for the mobile terminal is disclosed.

Abstract: Embodiments of the present invention provide a method, system and computer program product for multi-flavored software execution from a singular code base. In an embodiment of the invention, a method for multi-flavored software execution from a singular code base is provided. The method includes receiving a request in an interpreter to interpret a version of source code of a computer program the interpreting transforming the source code into byte code executable by a virtual machine. The method thereafter includes responding to the request by performing in the interpreter source code interpretation only of selected portions of the source code being annotated by tags corresponding to the version.

Abstract: A protocol compiler to generate flight code and routing tables is disclosed. In various embodiments, one or more definition files are received. The one or more definition files are parsed to extract flight control system definition data. A communication topology comprising a set of entities of the flight control system and communication links between said entities is determined based on the flight control system definition data. A set of one or more routing tables is generated programmatically based at least in part on the communication topology and message type definition data. Flight code to implement a flight control system defined at least in part by said flight control system definition data is generating programmatically, based at least in part on the flight control system definition data, including code to route messages according to said one or more routing tables.

Abstract: An inter-architecture compatibility apparatus of an aspect includes a control flow transfer reception module to receive a first call procedure operation, intended for a first architecture library module, from a first architecture code module. The first call procedure operation involves a first plurality of input parameters. An application binary interface (ABI) change module is coupled with the control flow transfer reception module. The ABI change module makes ABI changes to convert the first call procedure operation involving the first plurality of input parameters to a corresponding second call procedure operation involving a second plurality of input parameters. The second call procedure operation is compatible with a second architecture library module. A control flow transfer output module is coupled with the ABI change module. The control flow transfer output module provides the second call procedure operation to the second architecture library module.

Abstract: A computer-implemented method includes receiving a set of complete source instructions to process a source code entity, an incremental build part, and a set of file definitions. The method analyzes the set of complete source instructions. The method identifies, from the set of analyzed source instructions, a set of operations that reference the incremental build subset. The method repeats: (i) determining, for each operation, whether any additional files are affected by the operation, the additional files forming a set of affected files; (ii) creating a combined set of files, the combined set of files consisting of the set of affected files and the incremental build subset; and (iii) updating the set of operations to include those from the analyzed source instructions that reference the combined set of files; until no new files are added to the combined set of files. The method generates a set of incremental source instructions.

Abstract: Application source code that includes notation indicating a latency level between methods is evaluated. Based in part on the latency level, scores for method dependencies are calculated. A set of packages is generated for the methods in accordance with a clustering strategy that is based at least in part on the scores. The set of packages is then deployed to at least one host in accordance with an affinity threshold.

Abstract: In an approach for decreasing an execution time of a computer code, one or more processors identify a long-form conditional branch that is included in a first region of a computer code. The one or more processors generate a long-form unconditional branch with a target that is a target of a long-form conditional branch. The one or more processors modify the long-form conditional branch to be a short-form conditional branch. The one or more processors insert the long-form unconditional branch into the computer code within a branch distance of the short-form conditional branch. The one or more processors modify a target of the short-form conditional branch to be a location of the long-form unconditional branch in the computer code.

Abstract: A system, method, and computer program product are disclosed for enabling software components on a device, and for providing selective access to the components. A computer system receives a download request for a software component and an identifier associated with the requesting device and determines whether the software component is pre-installed, but not enabled, on the device. In the event that the system determines, through a registration check, that the software component is pre-installed but not enabled on the device, the system enables the component on the device. In the event that the system determines that the software component is not pre-installed on the device, the system causes the component to be downloaded and enabled on the device. Selective access to software components is granted based on whether the component is accessed by a user or a service provider, with the service provider granted access to remotely install ancillary functionality.

Abstract: Methods and systems that automate a DevOps deployment pipeline and optimize DevOps cost are described. Methods generate a deployment pipeline model based on policies associated with each deployment stage and task. Methods optimize cost of the deployment pipeline model based on model combinations of VMs. The deployment pipeline model may be executed on a cloud computing infrastructure in order to develop an application program.

Abstract: A method for deploying application components to Information Technology (IT) resources using an application platform controller includes requesting a network slice for the application components from a network controller. Priority values are assigned to the application components defining an order in which the application components are planned to be deployed. A deployment plan is computed for the application components. The network slice is reconfigured based on a determination that no deployment plan which meets the requirements is possible using the requested network slice. The application components are deployed sequentially, using the priority values, to host sites of the IT resources using information from the network controller including existing registrations of users of the application to an access network of the host sites such that replicas of the application components are provided at the host sites which provide a minimum latency with respect to a location of the users.

Abstract: At least one application may include instructions comprising application instructions and a plurality of separate pipeline definition instructions. The application instructions may be within a virtual container including at least one program that is generically executable in a plurality of different continuous integration and delivery (CI/CD) environments. Each of the plurality of separate pipeline definition instructions may be configured for each of the plurality of different CI/CD environments such that each pipeline definition may operate only in the CI/CD environment for which it is created. Each pipeline definition may be configured to cause the CI/CD environment for which it is created to execute the at least one program.

Abstract: A computer-implemented method includes saving a copy of a client computing environment to a computer memory on the host system. The processor writes an image of the client computing environment based on the saved copy of the client computing environment. The image includes an application layer, a middleware layer, and a system layer, and is based on the copy of the client computing environment. The image is extractable as a sub-image that includes one or more of the application layer, the middleware layer, and the system layer. The image includes a resource pattern having dependencies that associate two or more of the application layer, the middleware layer, and the system layer, such that the sub-image is combinable with an existing active container operating on a second computing system. The combination results in a functional copy of the client computing system with the changes extracted from the sub-image.

Abstract: The present invention proposes a method for offline upgrading virtual machine mirror images. The method comprises: an mirror image security server collecting virtual machine mirror images, and extracting and storing the information of the collected virtual machine mirror images; and the mirror image security server executing an upgrade operation of virtual machine mirror images in an offline way based on the information of the collected virtual machine mirror images. The method for offline upgrading virtual machine mirror images disclosed in the present invention has higher upgrade efficiency and is capable of upgrading the virtual machine mirror images in an offline way.

Abstract: The invention relates to computer technology, and in particular, to a method for achieving remote updating of application programs in a distributed application environment as well as a terminal management system for realizing the method.

Abstract: An integrated circuit including a ferroelectric random access memory (FRAM) for storing firmware, and a method of updating that firmware. The FRAM is constructed to selectively operate as a 2T2C FRAM memory in a normal operating mode, and as a 1T1C FRAM memory in an update mode. Updating of the stored firmware is performed by placing the FRAM in its update (1T1C) mode and writing the updated code into alternate rows of the 1T1C half-cells at each of a plurality of memory locations, while the other 1T1C half-cells in the other alternate rows retain the original data. Following verification of the updated contents, the original data in the other half-cells are overwritten with the verified updated data, and the operating mode is changed back to the normal (2T2C) operating mode.

Abstract: A system includes at least one data collection device connected to a corresponding data terminal via a primary communication channel; and a central connectivity point connected to each data collection device via a wireless secondary communication channel so as to communicate with the at least one data collection device without disrupting communication between the at least data collection device and the corresponding data terminal via the primary communication channel and to permit remote administration of each data collection device.

Abstract: When a baseboard management controller (BMC) is used to control a fan speed of a fan unit of a server by executing a firmware with fan parameter data stored in one temporary storage region, the fan parameter data is updated by receiving fan parameter update data and storing the fan parameter update data in another temporary storage region, and updating the fan parameter data using the fan parameter update data after determining that the received fan parameter update data is valid.

Abstract: A printer having multiple processor cores, and a firmware rewriting method for the printer, enable rewriting firmware in a short time. A first rewrite controller controls rewriting the firmware of the first core by the boot program of the first core; a second rewrite controller controls rewriting the firmware of a second core, which is one of the multiple cores other than the first core, by the boot program of the first core; and a reset unit resets the printer after rewriting the firmware of the first core and the firmware of the second core by the boot program of the first core ends.

Abstract: System and methods are provided for distributing firmware updates to groups of IHSs (Information Handling Systems) managed by an organization. The organization managing the IHSs specifies categorizations for each IHS that are used to separate the managed IHSs into firmware update groups. A GUID (Global Unique Identifier) is assigned to each IHS, in some scenarios during the manufacture of the IHS. The assigned GUID specifies one or more firmware update groups to which an IHS has been assigned. The organization, or other technical support entity, utilizes a firmware distribution system for delivery of firmware updates to supported IHSs. The organization signals the delivery of updates to a firmware update group by specifying the group's GUID to the firmware distribution service. The IHS, identified by its assigned GUID, queries a firmware distribution services in order to determine whether new firmware updates have been made available to its assigned firmware update group.

Abstract: A system and method for finding candidates of qualified names for at least one simple name in a source code file are disclosed. A source code file may be received that has at least one simple name for which a corresponding qualified name is required. The source code file may be parsed to determine the simple names in the file and the qualified names in the file. For the at least one simple name for which a corresponding qualified name is required, a source code graph may be searched to find potential candidate qualified names that correspond to the at least one simple name. Upon receipt of a list of potential candidate qualified names from the source code graph, the list may be outputted to a user in order for the user to choose the appropriate qualified name. Build dependencies may also be chosen for the qualified name.

Abstract: Embodiments of systems, apparatuses, and methods for broadcast arithmetic in a processor are described.

Abstract: A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.

Abstract: Embodiments of systems disclosed herein relate to processor architecture. One such system implements a method that includes the processor obtaining an instruction. The instruction specifies an operation, and also specifies one of the registers as a source register and one of the registers as a destination register. The method also includes the processor obtaining an endian mode and determining that the instruction is an element-ordering-sensitive instruction. Based on the determination that the instruction is an element-ordering-sensitive instruction, the processor executes the instruction by performing the operation on the elements of the source register in accordance with the endian mode and writing a result of the operation to the destination register.

Abstract: Supporting even instruction tag (‘ITAG’) requirements in a multi-slice processor with null internal operations (IOPs) includes: receiving an IOP with an even ITAG requirement; determining that the IOP is to be assigned an odd ITAG; and inserting a null IOP into an instruction lane ahead of the IOP, wherein the null IOP is assigned the odd ITAG, and the IOP is assigned an even ITAG.

Abstract: Logic is provided to receive and execute a mask move instruction to transfer unmasked data elements of a vector data element including a plurality of packed data elements from a source location to a destination location, subject to mask information for the instruction. The logic is to execute a speculative full width operation, and if an exception occurs is to perform operations sequentially or one at a time. Other embodiments are described and claimed.

Abstract: An apparatus and method for supporting simultaneous multiple iterations (SMI) in a course grained reconfigurable architecture (CGRA). In support of SMI, the apparatus includes: Hardware structures that connect all of multiple processing engines (PEs) to a load-store unit (LSU) configured to keep track of which compiled program code iterations have completed, which ones are in flight and which are yet to begin, and a control unit including hardware structures that are used to maintain synchronization and initiate and terminate loops within the PEs. SMI permits execution of the next instruction within any iteration (in flight). If instructions from multiple iterations are ready for execution (and are pre-decoded), then the hardware selects the lowest iteration number ready for execution. If in a particular clock cycle, a loop iteration with a lower iteration number is stalled (i.e.

Abstract: A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.

Abstract: A programmable controller for executing a sequence program comprises a processor for reading and executing an instruction code from an external memory, an instruction cache memory for storing a branch destination program code of a branch instruction included in the sequence program, and a cache controller for entering the branch destination program code in the instruction cache memory according to data on priority, the instruction code of the branch instruction including the data on priority of an entry into the instruction cache memory.

Abstract: A data processing system includes a control register, a program counter and a controller. The control register is used to store a level status of an execution flow and at least one return address. When the controller reads a block call instruction while a level status of the execution flow has an initial value, the controller stores a return address of the block call instruction in the control register, increments a value of the level status, and redirects the execution flow to a target address indicated by the block call instruction. When the controller reads a block return instruction and the value of the level status is not equal to the initial value, the controller decrements the value of the level status. If the value of the level status becomes equal to the initial value, the controller redirects the execution flow to the return address.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes a control element, coupled to the out-of order processor via a control bus.

Abstract: Systems, apparatuses, and methods for pre-computing early age indicators for a non-shifting reservation station. A reservation station may include a plurality of entries storing a plurality of instruction operations prior to issuance to an execution unit. The reservation station may include control logic for pre-computing early age indicators for specifying which entry of each adjacent pair of entries is the oldest ready instruction operation. The early age indicators may be routed through registers and then through additional levels of control logic for determining the oldest ready instruction operation in all of the entries of the reservation station.

Abstract: In one embodiment, a processor includes an accelerator, a decoder to decode a first instruction into a decoded first instruction, and a second instruction into a decoded second instruction, and an execution unit to execute the first decoded instruction to, for a thread executing on the accelerator that is to be placed in an inactive state, cause a save of context information for the thread, and a save of a vector identifying the accelerator corresponding to the context information, and execute the second decoded instruction to read the vector to determine the accelerator to restore saved context information into for the thread, read the saved context information, and restore the saved context information into the accelerator.

Abstract: A method of compressing a sequence of program instructions begins by examining a program instruction stream to identify a sequence of two or more instructions that meet a parameter. The identified sequence of two or more instructions is replaced by a selected type of layout instruction which is then compressed. A method of decompressing accesses an X-index and a Y-index together as a compressed value. The compressed value is decompressed to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions. An apparatus for decompressing includes a storage subsystem configured for storing compressed instructions, wherein a compressed instruction comprises an X-index and a Y-index. A decompressor is configured for translating an X-index and Y-index accessed from the storage subsystem to a selected type of layout instruction which is decoded and replaced with a sequence of two or more instructions.

Abstract: Fast issuance and execution of a multi-width instruction across multiple slices in a parallel slice processor core is supported in part through the use of an early notification signal passed between issue logic associated with multiple slices handling that multi-width instruction coupled with an issuance of a different instruction by the originating issue logic for the early notification signal.

Abstract: A mechanism of booting up a system directly from a storage device and a means of initializing an embedded system prior to activating a CPU is presented. The said system is comprised of one or more CPUs, a reset controller, a storage device controller, one or more direct memory access controllers, a RAM and its controller, a ROM and its controller, a debug interface and a power-on reset (POR) sequencer. The POR sequencer controls the overall boot process of the embedded system. Said sequencer uses descriptors (POR Sequencer descriptors) which are used to update the configuration registers of the system and to enable CPU-independent data transfers with the use of DMA controllers. Using a minimal amount of non-volatile memory for booting up a system brings down costs associated with increased silicon real estate area and power consumption. Capability of pre-initializing the system even before a CPU is brought out of reset provides flexibility and system robustness.

Abstract: A processing system with multiple processing units may support separate operating systems (OSs) in separate partitions. During an initialization process, a preboot manager in the processing system may copy software to a sequestered area of memory in the processing system. The preboot manager may also configure the processing system to hide the sequestered area of memory from a first partition of the processing system. Also, the preboot manager may use a first processing unit in the processing system to boot an OS on the first partition, and the preboot manager may transmit a boot trigger from the first processing unit to a second processing unit in the processing system. The boot trigger may cause the second processing unit to use the software in the sequestered area of memory to boot a second partition of the processing system. Other embodiments are described and claimed.

Abstract: A method and a device for controlling usability of a communication device having a processing unit including a memory for storing computer code, a modem, an access circuit connected to the modem for cellular network authentication and access, and a secure element connected to the access circuit. A boot of the processing unit and the secure element can be initiated at power up of the device. A boot service in the secure element can be executed, and a current state of a state machine in the secure element can be determined. Thereafter, a partition of an operating system can be booted, where the partition is selected dependent on said current state of the state machine.

Abstract: Examples relate to extending hardware support for sensors embedded in peripherals. In some examples, a driver is used to determine that a peripheral device includes a sensor in response to the peripheral device being attached to a mobile computing device, where the driver is preloaded in an operating system kernel of the mobile computing device. Next, a list of supported hardware features is updated to include a peripheral hardware feature that is provided by a sensor of the peripheral device, and the list of supported hardware features is sent to an application store server. At this stage, a list of available applications that are compatible with the list of supported hardware features is received from the application store server.