Patents Issued in November 6, 2018
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Patent number: 10120698Abstract: An Operating-System (OS) independent peripheral API is provided to applications processing in an application OS. The API communicates with a peripheral OS that includes device drivers for peripherals. Requests for accessing the peripherals are made through the API of the application OS but access and control of the peripherals are maintained through the device drivers of the peripheral OS.Type: GrantFiled: March 28, 2017Date of Patent: November 6, 2018Assignee: NCR CorporationInventors: Alexander William Whytock, Graeme Mitchell
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Patent number: 10120699Abstract: A method is provided for facilitating access by an external user to the internal registers of a server including: transmitting access commands originating from the external user to a service processor using a communication protocol directly understandable by the service processor which accesses the internal registers using one or more access protocols, automatically transforming command lines issued by the user into access commands in the communication protocol using one or more service modules which associate at least the corresponding addresses of the internal registers with the names of the internal registers supplied by the external user. On the occasion of a user-commanded access by the service processor to the internal registers, the service processor is responsible for managing a possible risk of collision with a monitoring access to the internal registers for the purposes of updating a copy of the status of the internal registers.Type: GrantFiled: June 17, 2015Date of Patent: November 6, 2018Assignee: BULL SASInventor: Claude Brassac
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Patent number: 10120700Abstract: Storage management is disclosed, including: causing at least a control portion of a virtual disk to be created for a virtual machine; and using the at least control portion of the virtual disk as a communication channel between the virtual machine and a storage system.Type: GrantFiled: October 1, 2013Date of Patent: November 6, 2018Assignee: Tintri Inc.Inventors: Rex R. Walters, Brandon W. Salmon
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Patent number: 10120701Abstract: Mechanisms for moving data between different operating systems in a dual OS computing device are discussed. More particularly, embodiments of the present invention utilize the clipboard facilities supported by the operating systems, along with firmware and helper software in each OS, to move data back and forth when switching between an active and inactive operating system. The clipboard contents are preserved in non-volatile storage that is not lost across the sleep-state transitions used to switch operating systems. Helper software analyzes the clipboard contents being copied and converts them into a format recognized by the current operating system and its applications.Type: GrantFiled: December 4, 2014Date of Patent: November 6, 2018Assignee: Insyde Software Corp.Inventor: Timothy Andrew Lewis
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Patent number: 10120702Abstract: Certain aspects direct to systems and methods for platform simulation for development projects of a management controller, such as a baseboard management controller (BMC). The management controller stores a firmware module and a simulator module. The firmware module is supposed to receive output signals from a computing device as the platform, or from one or more devices connected to the platform. The simulator module is a software implemented module used to simulate the platform or the device, by generating the output signals of the platform or the device based on configuration data stored in a data library, and sending the simulated output signals to the firmware module for development and testing purposes.Type: GrantFiled: July 12, 2016Date of Patent: November 6, 2018Assignee: AMERICAN MEGATRENDS, INC.Inventors: Satheesh Thomas, Baskar Parthiban, Rajeswari Ravichandran, Pavithra Sachidanandam, Aruna Venkataraman, Senathipathy Thangavel
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Patent number: 10120703Abstract: Technologies are disclosed herein for executing commands within virtual machine (“VM”) instances. A public web service application programming interface (“API”) is exposed within a service provider network that includes methods relating to the execution of commands within VM instances. For example, the API might include a method for obtaining a list of the commands that can be executed within a VM instance. The API might also include a method for requesting the execution of a command within a VM instance. The API might also include a method for requesting data describing the status of the execution of a command within a VM instance. The API might also expose other methods. A software agent executing on a VM instance may be utilized to provide a list of commands that can be executed in the VM, to execute requested commands, and to provide data describing the status of execution of a command.Type: GrantFiled: February 27, 2017Date of Patent: November 6, 2018Assignee: Amazon Technologies, Inc.Inventor: Wesley Gavin King
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Patent number: 10120704Abstract: A parallel hypervisor system for virtualizing application-specific supercomputers is disclosed. The hypervisor system comprises (a) at least one software-virtual hardware pair consisting of a software application, and an application-specific virtual supercomputer for accelerating the said software application, wherein (i) The virtual supercomputer contains one or more virtual tiles; and (ii) The software application and the virtual tiles communicate among themselves with messages; (b) One or more reconfigurable physical tiles, wherein each virtual tile of each supercomputer can be implemented on at least one physical tile, by configuring the physical tile to perform the virtual tile's function; and (c) A scheduler implemented substantially in hardware, for parallel pre-emptive scheduling of the virtual tiles on the physical tiles.Type: GrantFiled: April 25, 2016Date of Patent: November 6, 2018Assignee: Global Supercomputing CorporationInventors: Kemal Ebcioglu, Atakan Dogan, Reha Oguz Altug
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Patent number: 10120705Abstract: A method for implementing GPU virtualization. The method is applied to a physical host and the physical host includes: a hardware layer including a GPU, a Host running on the hardware layer, and N back-end GPU Domains and M front-end VMs that run on the Host, where there are service channels between the N back-end GPU Domains and the M front-end VMs. The method includes: transferring, by an mth front-end VM, a GPU command to an nth back-end GPU Domain based on the service channels; and processing, by the nth back-end GPU Domain, the GPU command by using a GPU, to obtain corresponding processing result data, where the type of the operating systems running on the nth back-end GPU Domain and the mth front-end VM is same. The invention helps to optimize performance of a GPU virtualization system.Type: GrantFiled: June 30, 2016Date of Patent: November 6, 2018Assignee: Huawei Technologies Co., Ltd.Inventors: Weidong Han, Yingdong Liu
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Patent number: 10120706Abstract: Techniques are described that can be used to enable a transfer of an operating system from one machine to another. The transfer permits the operating system to be available to the target machine at buffers that are accessible to one or more application or other logic. In some implementations, information related to an operating system migration is stored in a buffer that is accessible to an application that is to use the information and thereby avoids a copy of such information from an intermediate buffer to an application buffer.Type: GrantFiled: May 20, 2015Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Eliel Louzoun, Mickey Gutman, Gregory Cummings
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Patent number: 10120707Abstract: Systems and methods for deploying development environments are described. A request to create a development environment is received from a user. The request is evaluated to identify a stored template appropriate for the requested development environment. An instruction sequence is then generated to create the requested development environment, based on the determined template. The instructions in the instruction sequence are transmitted to multiple virtual machine hosts. Upon successful creation of the development environment, a response is returned to the requesting user with access information for the development environment.Type: GrantFiled: December 8, 2015Date of Patent: November 6, 2018Assignee: PAYPAL, INC.Inventors: Trevor Wood, Jason Deleau
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Patent number: 10120708Abstract: Systems and methods for configuring a virtual machine provided by a remote computing system based on the availability of one or more remote computing resources and respective corresponding prices of the one or more remote computing resources.Type: GrantFiled: January 18, 2016Date of Patent: November 6, 2018Assignee: Amazon Technologies, Inc.Inventor: Rajan Panchapakesan
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Patent number: 10120709Abstract: A guest OS detects a DMA write request for a device assigned to the guest OS to perform a DMA write to a shared page of memory that has a write protection attribute to cause a protection page fault upon an attempt to write to the shared page of memory. The guest OS reads a portion of the shared page of memory from a location of that page, determines the value of the portion, and executes an atomic instruction that writes the value back to the location of the shared page of memory to trigger the page protection fault. Upon executing the atomic instruction, the guest OS sends the DMA write request to the device to cause the device to write to a writeable copy of the shared page of memory.Type: GrantFiled: February 29, 2016Date of Patent: November 6, 2018Assignee: Red Hat Israel, Ltd.Inventors: Michael Tsirkin, Andrea Arcangeli
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Patent number: 10120710Abstract: A virtual resource management node to seamlessly migrate a virtual machine with less influence on services in an NFV environment. A VIM is a VIM for managing each virtualized resource that is included in an NFV environment including virtualized resources including a physical machine in which a virtual machine having a VNF being a virtualized communication function is implemented, and the VIM includes a switching unit for switching a network flow from a virtual machine of a migration source to a virtual machine of a migration destination, or switching a system between an Active (ACT) system virtual machine of a migration source and a Standby (SBY) system virtual machine of a migration destination.Type: GrantFiled: February 17, 2015Date of Patent: November 6, 2018Assignee: NTT DOCOMO, INC.Inventors: Masaaki Kosugi, Hidenori Asaba, Takeo Yamasaki, Ashiq Khan, Shigeru Iwashina, Takashi Shimizu
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Patent number: 10120711Abstract: Examples quickly suspend and resume virtual desktops on demand or on schedule. Virtual desktops, or desktops as a service, are provided to users, where the virtual desktop is a forked VM, cloned VM, or otherwise at least a partial duplicate of an existing VM. The virtual desktop points to existing memory maintained by the existing VM, and the virtual desktop only writes to memory the pages that the virtual desktop creates or modifies.Type: GrantFiled: March 21, 2017Date of Patent: November 6, 2018Assignee: VMware, Inc.Inventors: Daniel James Beveridge, David Snowdon
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Patent number: 10120712Abstract: Pre-fetching instructions for tasks of an operating system (OS) is provided by calling a task scheduler that determines a load start time for a set of instructions for a particular task corresponding to a task switch condition. The OS calls, and in response to the load start time, a loader entity module that generates a pre-fetch request that loads the set of instructions for the particular task from a non-volatile memory circuit into a random access memory circuit. The OS calls the task scheduler to switch to the particular task.Type: GrantFiled: July 5, 2016Date of Patent: November 6, 2018Assignee: NXP USA, Inc.Inventors: Stefan Singer, Jochen M Gerster, Michael Rohleder
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Patent number: 10120713Abstract: A task control circuit maintains, in response to task event information, a task information queue that includes task information for a plurality of tasks. Based upon the task information in the task information queue, a future task switch condition is identified as corresponding to a task switch time for a particular task of the plurality of tasks. A load start time is determined for a set of instructions for the particular task. A pre-fetch request is generated to load the set of instructions for the particular task into the memory circuit. The pre-fetch request is forwarded to a hardware loader circuit. In response to the task switch time, a task event trigger is generated for the particular task. The hardware loader circuit is used to load, in response to the pre-fetch request, the set of instructions from a non-volatile memory into the memory circuit.Type: GrantFiled: July 5, 2016Date of Patent: November 6, 2018Assignee: NXP USA, Inc.Inventors: Michael Rohleder, Stefan Singer, Jochen Gerster
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Patent number: 10120714Abstract: A set of techniques for customizing resources for the workload of an application is described. The application can be received and hosted on a set of hardware and software resources of a service provider, which may include server instances, databases, load balancers and the like. Once the application is deployed and processing workload, it can be monitored to gather runtime trace information associated with the workload. This runtime trace information can be analyzed for potential optimizations and improvements to the set of resources or their configuration. Additionally, the user is enabled to input hardware/software specifications for the resources used to run the application. The service provider can use these specifications, along with the runtime trace information to optimize the resource stack used to execute the user's application.Type: GrantFiled: May 1, 2012Date of Patent: November 6, 2018Assignee: Amazon Technologies, Inc.Inventors: Luis Felipe Cabrera, Eric Jason Brandwine, James R. Hamilton, Jonathan A. Jenkins, Matthew D. Klein, Nathan Thomas, Pradeep Vincent
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Patent number: 10120715Abstract: A distributed network management method for a vehicle is provided. The distributed network management method includes a first step, a second step, a third step and a fourth step. The first step is for preforming a re-configuring action and a pre-defining action to a plurality of network messages transmitted through a plurality of nodes. The second step is for defining a leading node form the nodes. The third step is for detecting a failed node from the nodes. The fourth step is for defining at least one idle node by the leading node according to a task load of each of the nodes, thereby assigning a task of the failed node to the idle node.Type: GrantFiled: December 10, 2015Date of Patent: November 6, 2018Assignee: Automotive Research & Testing CenterInventors: Che-Cheng Chang, Chao-Yang Lee, Yi-Chen Lu
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Patent number: 10120716Abstract: Mechanisms for improving computing system performance by a processor device. System resources are organized into a plurality of groups. Each of the plurality of groups is assigned one of a plurality of predetermined task pools. Each of the predetermined task pools has a plurality of tasks. Each of the plurality of groups corresponds to at least one physical boundary of the system resources such that a speed of an execution of those of the plurality of tasks for a particular one of the plurality of predetermined task pools is optimized by a placement of an association with the at least one physical boundary and the plurality of groups.Type: GrantFiled: October 2, 2014Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin J. Ash, Seamus J. Burke, Lokesh M. Gupta, Clint A. Hardy, Matthew J. Kalos, Trung N. Nguyen, Karl A. Nielsen, Louis A. Rasor, David B. Whitworth
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Patent number: 10120717Abstract: The invention relates to a method for optimizing the parallel processing of data on a hardware platform, the hardware platform comprising at least one computing unit comprising a plurality of processing units able to execute a plurality of executable tasks in parallel, the data to be processed forming a data set that can be broken down into data subsets, a same sequence of operations being performed on each data subset.Type: GrantFiled: July 9, 2014Date of Patent: November 6, 2018Assignee: ThalesInventors: Rémi Barrere, Paul Brelet, Michel Barreteau, Eric Lenormand
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Patent number: 10120718Abstract: A resource management computer node obtains hardware utilization values measured for a hardware resource of a computer system being used by a software application. For a set of the utilization values that were measured during a same time-of-day range on a same day of week, the node determines a count value indicating a number of times the utilization values in the set exceed a count threshold, determines a count percentage based on a ratio of the count value to a sum of count values determined for the same day of week, compares the count percentage to a busy threshold, and, responsive to if the count percentage is determined to exceed the busy threshold, sets a busy indicator object at a location in a resource utilization data structure having a defined correspondence to the time-of-day range. The node controls reservation of hardware resources for the software application responsive to whether the busy indicator object has been set.Type: GrantFiled: August 24, 2016Date of Patent: November 6, 2018Assignee: CA, Inc.Inventors: Alex Esterkin, David Rich, James Mercer
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Patent number: 10120719Abstract: Embodiments relate to managing resource consumption in a computing system. An aspect includes providing a resource policy by defining a plurality of threshold values relating to the resource consumption, wherein the resources are consumed by a plurality of user-defined functions performing tasks for a database management system, wherein the user-defined functions are executed by a plurality of processes external to the database management system. Another aspect includes performing an action, as defined by the resource policy, on at least one of the user-defined functions.Type: GrantFiled: March 17, 2015Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: James L. Finnie, Torsten Steinbach, Michael Wurst
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Patent number: 10120720Abstract: A computing system includes a computer in communication with a tiered storage system. The computing system identifies a set of data transferring to a storage tier within the storage system. The computing system identifies a program to which the data set is allocated and determines to increase or reduce resources of the computer allocated to the program, based on the set of data transferring to the storage tier. The computing system discontinues transferring the set of data to the storage tier if a resource allocated to the program cannot be increased.Type: GrantFiled: October 24, 2016Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Rahul M. Fiske, Akshat Mithal, Sandeep R. Patil, Subhojit Roy
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Patent number: 10120721Abstract: A method of scheduling tasks for a group of applications. Each application is associated with a separate task queue for identifying application tasks that are ready for execution. The method receives a request to place a task in an application task queue. The method places the task in the application task queue based on a set of intra application scheduling policies defined for the application. The method receives a request to identify the next task to execute. The method identifies an application queue from which from which the next task is to be executed. The application queue is identified based on a set of inter application scheduling policies defined for the plurality of applications. The method schedules a task from the identified application queue for execution based on the intra application scheduling policies.Type: GrantFiled: October 29, 2015Date of Patent: November 6, 2018Assignee: VMware, Inc.Inventors: Naveen Ramaswamy, Dimal Baby
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Patent number: 10120722Abstract: According to the teachings herein, provisioning operations carried out via electronic processing in a communication network (60) benefit from the use of reordered workflows (20) having task orderings that are at least partly optimized with respect to task failure probabilities and/or resource-blocking penalties. The reordered workflows (20) are obtained by optimizing predefined provisioning workflows (10). Each predefined workflow (10) comprises two or more tasks (12) ordered along one or more task execution paths (14) in a task tree (16), according to a default task ordering that reflects any required inter-task dependencies but, in general, does not reflect any optimization in terms of failure penalties, resource blocking, etc. Among the several advantages provided by the teachings herein, carrying out provisioning operations in accordance with reordered workflows (20) wastes fewer compute cycles and reduces the needless blocking of network resources in the event of provisioning task failures.Type: GrantFiled: January 31, 2014Date of Patent: November 6, 2018Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)Inventors: Ron Hamway, Paul Ballman, Calin Curescu, Craig Donovan, Curtis Goedde
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Patent number: 10120723Abstract: An information processing system for processing jobs managed by a plurality of queues includes a first input unit, a determination unit, and a second input unit. The first input unit inputs a first job regularly generated in the information processing system to a first queue. The determination unit determines a queue to which a second job should be input, out of a plurality of queues, wherein the second job is generated upon reception of a request corresponding to an input via a screen provided by the information processing system. The second input unit inputs the second job to a queue determined to be an input target of the second job by the determining. The determination unit determines the queue to which the second job should be input based on a processing state of data to be processed for the second job.Type: GrantFiled: May 31, 2016Date of Patent: November 6, 2018Assignee: Canon Kabushiki KaishaInventor: Kazuo Imai
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Patent number: 10120724Abstract: A method and system for automatically metering a distributed file system node is provided. The method includes receiving data associated with jobs for execution via a distributed file system. Characteristics of the jobs are uploaded and policy metrics data associated with hardware usage metering is retrieved. Resource requests associated with hardware resource usage are retrieved and attributes associated with the resource requests are uploaded. The policy metrics data is analyzed and a recommendation circuit is queried with respect to the resource requests. A set of metrics of the policy metrics data associated with the resource requests is determined and a machine learning circuit is updated. Utilized hardware resources are determined with respect to the hardware usage metering and said resource requests.Type: GrantFiled: August 16, 2016Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Sudeep Badjatia, Rajarshi Bhose, Bijoy Deb, Ripon Nandi
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Patent number: 10120725Abstract: Methods, systems, and computer-readable media for automatically configuring an inventory of hardware to interact seamlessly with a datacenter are provided. Initially, customer-specific specifications are collected from a user, which are automatically supplemented with platform-specific specifications. These specifications are used to select the hardware inventory from a set of predefined hardware clusters, where each of the predefined hardware clusters represents compatible configurations of hardware assets and logical assets that have been demonstrated to function congruently. A cluster-configuration file is derived from data held within a stock-keeping unit (SKU) that describes the selected hardware inventory. The cluster-configuration file is populated with abstract symbolic representations that act as placeholders for expected values that are presently unknown. Network resources are assigned by automated conversion of the abstract symbolic representations into concrete values.Type: GrantFiled: June 22, 2012Date of Patent: November 6, 2018Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Marwan E Jubran, Aleksandr Gershaft, Weiping Hu, Vitalii Tsybulnyk
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Patent number: 10120726Abstract: According to one aspect of the present disclosure, a method and technique for hybrid virtual machine configuration management is disclosed. The method includes: assigning to a first set of virtual resources associated with entitled resources of a virtual machine a first priority; assigning to a second set of virtual resources associated with the virtual machine a second priority lower than the first priority, wherein the first and seconds sets when combined exceed the entitled resources for the virtual machine; mapping the first set of virtual resources to a first physical resource of a pool of shared physical resources allocatable to the first and second sets of virtual resources, wherein the first physical resource comprises a desired affinity level to a second physical resource allocated to the virtual machine; and preferentially allocating the first physical resource to the first set of virtual resources.Type: GrantFiled: November 23, 2015Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Vaijayanthimala K. Anand, Wen-Tzer T. Chen, William A. Maron, Mysore S. Srinivas, Basu Vaidyanathan
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Patent number: 10120727Abstract: Examples may include techniques for allocating configurable computing resources from a pool of configurable computing resources to a logical server or virtual machine. The logical server or virtual machine may use allocated configurable computing resources to implement, execute or run a workload.Type: GrantFiled: February 23, 2015Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Katalin K. Bartfai-Walcott, Alexander Leckey, John Kennedy, Chris Woods, Giovani Estrada, Joseph Butler, Michael J. McGrath, Slawomir Putyrski
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Patent number: 10120728Abstract: Techniques and structures relating to virtual graphics processing units (VGPUs) are disclosed. A VGPU may appear to software as an independent hardware GPU. However, two or more VGPUs can be implemented on the same GPU through the use of control structures and by duplicating some (but not all) hardware elements of the GPU. For example, additional registers and storage space may be added in a GPU supporting multiple VGPUs. Different execution priorities may be set for tasks and threads that correspond to the different supported VGPUs. Memory address space for the VGPUs may also be managed, including use of virtual address space for different VGPUs. Halting and resuming execution of different VGPUs allows for fine-grained execution control in various embodiments.Type: GrantFiled: August 3, 2017Date of Patent: November 6, 2018Assignee: Apple Inc.Inventors: Robert A. Drebin, James Wang
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Patent number: 10120729Abstract: Exemplary methods, apparatuses, and systems include virtualization software of a host computer receiving a first packet addressed to a first virtual link layer address. Each of a first plurality of virtual machines on the first host computer is configured to share the first virtual link layer address. The virtualization software of the first host computer maps a flow of packets, including the first packet, to a first virtual machine within the first plurality of virtual machines and forwards the first packet to the first virtual machine. The virtualization software of the first host computer receives a second packet from the first virtual machine in response to the first packet. The second packet includes the first virtual link layer address as a source address for the first virtual machine.Type: GrantFiled: February 14, 2014Date of Patent: November 6, 2018Assignee: VMWARE, INC.Inventors: Sreeram Ravinoothala, Ganesan Chandrashekhar
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Patent number: 10120730Abstract: The present invention provides an information processing device to efficiently execute a plurality of analysis engines on a plurality of analysis processing devices. The information processing device includes an arrangement control means that determines an arrangement pattern indicating connection between a plurality of data distribution devices and a plurality of controlled information processing devices based on cost information indicating price values of operation of a load control executing means regarding data processing and a dynamic load control means that connects the data distribution device to the controlled information processing device based on the arrangement pattern and controls start and stop of operation of the load control executing means based on the cost information and a load status of the controlled information processing device.Type: GrantFiled: February 16, 2015Date of Patent: November 6, 2018Assignee: NEC CORPORATIONInventor: Yosuke Iwamatsu
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Patent number: 10120731Abstract: Various embodiments are generally directed to techniques for controlling the use of locks that regulate access to shared resources by concurrently executed portions of code. An apparatus to control locking of a resource includes a processor component, a history analyzer for execution by the processor component to analyze at least one result of a replacement of a lock instruction of a first instance of code with a lock marker to allow the processor component to speculatively execute a second instance of code, and a locking component for execution by the processor component to replace the lock instruction with the lock marker based on analysis of the at least one result, the first and second instances of code to access a resource and the lock instruction to request a lock of access to the resource to the first instance of code. Other embodiments are described and claimed.Type: GrantFiled: July 15, 2013Date of Patent: November 6, 2018Assignee: INTEL CORPORATIONInventors: Khun Ban, Kingsum Chow, Shirish Aundhe, Sandhya Viswanathan
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Patent number: 10120732Abstract: Systems, devices, and techniques for processor synchronization are described. A described system includes exclusion monitor circuitry, a content addressable memory (CAM) coupled with the exclusion monitor circuitry, and processors coupled with the exclusion monitor circuitry. The processors can perform synchronization via the exclusion monitor circuitry using an identifier tag. The exclusion monitor circuitry can utilize the CAM to store information for handling one or more named mutual exclusions. The exclusion monitor circuitry and the CAM can be configured to concurrently handle multiple identifier tags that correspond to different mutual exclusions.Type: GrantFiled: April 27, 2017Date of Patent: November 6, 2018Assignee: FRIDAY HARBOR LLCInventors: Ricardo Jorge Lopez, Robert N. Hilton
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Patent number: 10120733Abstract: A remoting client and a remoting server are described. In one embodiment, the remoting client has a client remote access application, a client invoker, a marshaller, and an unmarhaller. The client remote access application provides a version indicator of the client remote access application and receives a version indicator of a server remote access application. The client invoker generates an invocation request including the version indicator of the client remote access application. The client remote access application determines a compatible version between the client remote access application and the server remote access application based on the version indicator of the client remote access application and the version indicator of the server remote access application.Type: GrantFiled: August 30, 2007Date of Patent: November 6, 2018Assignee: Red Hat, Inc.Inventors: Thomas Mitchell Elrod, Ron Sigal
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Patent number: 10120734Abstract: In some examples, an application programming interface (API) and services engine is configured to determine, in response to receiving a service request from an application, an application identifier for the service request based at least on an authorization token included in the service request, wherein the application identifier identifies an application that issued the service request; select, based at least on the application identifier, an application data store uniquely associated with the application that issued the service request; and process the service request using data stored by the selected application data store.Type: GrantFiled: August 29, 2016Date of Patent: November 6, 2018Assignee: Equinix, Inc.Inventors: Vijaay Doraiswamy, Ramchandra Jayateerth Koty, Purvish Purohit, Mahendra Malviya, Mohit Mathur, Darel P. Lasrado, Manikandan Kaliyaperumal, Premkumar Soman
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Patent number: 10120735Abstract: Systems, methods, apparatuses, and software for touch input systems in computing environments are provided herein. In one example, an interaction service positioned logically between an operating system and an application is provided. The interaction service directs a processing system to receive a call from the application referencing an interaction class to attach to a layer in a user interface used for the application, attach the interaction class to the layer in the user interface, listen to the operating system for user input occurring with respect to the layer, and determine per the interaction class what actions to perform in response to the user input.Type: GrantFiled: October 30, 2015Date of Patent: November 6, 2018Assignee: Microsoft Technology Licensing, LLCInventors: Brent Gilbert, Benjamin D. Haynes, Tony J. Beeman, Tyler R. Adams
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Patent number: 10120736Abstract: Two or more ports of a same type are identified in a computer. A separate device driver process is initiated for each of the identified ports. A one-to-one correspondence between each of the ports and each of the device driver processes is established.Type: GrantFiled: August 12, 2014Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael Adda, Dan Aloni, Avner Braverman
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Patent number: 10120737Abstract: An apparatus for detecting bugs in a logic-based processing device during post-silicon validation is disclosed. The apparatus includes a test bench and a Proactive Load and Check (PLC) hardware checker inserted within an uncore component of the logic-based processing device. The test bench includes a processor for converting an original test program to a modified test program for validating the functionalities of the logic-based processing device during post-silicon validation. The PLC hardware checker includes a controller, an address generator, a data register and a comparator.Type: GrantFiled: February 18, 2016Date of Patent: November 6, 2018Assignee: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Hai Lin, Subhasish Mitra
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Patent number: 10120738Abstract: Guest memory data structures are read by one or more read operations which are set up to handle page faults and general protection faults generated during the read in various ways. If such a fault occurs while performing the one or more read operations, the fault is handled and the one or more read operation is terminated. The fault is handled by either dropping the fault and reporting an error instead of the fault, by dropping the fault and invoking an error handler that is set up prior to performing the read operations, or by forwarding the fault to a fault handler that is setup prior to performing the read operations. If no fault occurs, the read operations complete successfully. Thus, under normal circumstances, no fault is incurred in a read operation on guest memory data structures.Type: GrantFiled: June 24, 2016Date of Patent: November 6, 2018Assignee: VMware, Inc.Inventors: Radu Rugina, Jeffrey W. Sheldon, James S. Mattson, Jr., David Dunn
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Patent number: 10120739Abstract: A method begins with a processing module querying distributed storage network (DSN) storage units regarding storage errors associated with a data segment. The method continues with the processing module receiving query responses and depending on the responses, assigning a first threshold priority or a second threshold priority to encoded data slices (EDSs) associated with the data segment. The method proceeds with the processing module, depending on the assigned threshold priority, issuing read slice requests and rebuilding EDS associated with the data segment.Type: GrantFiled: July 6, 2017Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: S. Christopher Gladwin, Asimuddin Kazi
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Patent number: 10120740Abstract: The present disclosure includes apparatus and methods for debugging on a memory device. An example apparatus comprises a memory device having an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to perform logical operations on the memory device. A controller is coupled to the array and sensing circuitry and configured to cause the memory device to store debugging code in the array of memory cells and execute instructions to perform logical operations using the sensing circuitry. The controller is further configured to receive an indication in the executing instructions to halt a logical operation, and to execute the debugging code on the memory device.Type: GrantFiled: March 22, 2016Date of Patent: November 6, 2018Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Shawn Rosti
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Patent number: 10120741Abstract: The present invention provides a semiconductor memory device that can perform failure detection of an address decoder by a simple method with a low area overhead. The semiconductor memory device includes: a first memory array having a plurality of first memory cells arrange in matrix; a plurality of word lines provided corresponding to each of the memory cell rows; an address decoder for selecting a word line from the word lines based on the input address information; a second memory array that is provided adjacent to the first memory array in the column direction, having a plurality of second memory cells able to read address information used in the selection of the previously stored word line, according to the selection of the word line extended to the second memory array; and a comparison circuit for comparing the input address information with the address information read from the second memory array.Type: GrantFiled: September 20, 2017Date of Patent: November 6, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Yuichiro Ishii, Atsushi Miyanishi, Yoshikazu Saito
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Patent number: 10120742Abstract: A power supply controller system includes a power supply portion, arithmetic processing portions, and first and second monitoring circuits configured to monitor an integrity of power supply of the power supply portion. The first monitoring circuit instructs a second arithmetic processing portion to stop an operation thereof when a first watchdog timer is not reset for a predetermined period of time. The second monitoring circuit instructs a first arithmetic processing portion to stop an operation thereof when a second watchdog timer is not reset for a predetermined period of time. The first monitoring circuit further includes a third watchdog timer periodically reset by any one of the first arithmetic processing portion and the second arithmetic processing portion and instructs another arithmetic processing portion to stop an operation thereof when the third watchdog timer is not reset for a predetermined period of time.Type: GrantFiled: April 28, 2017Date of Patent: November 6, 2018Assignee: OMRON CorporationInventors: Takamasa Ueda, Yasuo Muneta
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Patent number: 10120743Abstract: An information handling system includes a video interface and an error handler including a service profile. The error handler detects an error in an operation of the information handling system, generates an error report in response to detecting the error, generates a Quick Response (QR) code based on the error report, and sends the QR code to the video interface based upon the service profile.Type: GrantFiled: April 27, 2017Date of Patent: November 6, 2018Assignee: DELL PRODUCTS, LPInventors: Anand P. Joshi, Dirie N. Herzi
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Patent number: 10120744Abstract: A computing environment provisioning system includes a processing system and a memory for storing instructions that are executed by the processing system to obtain a graph having one or more edges with multiple vertices representing task instructions to perform multiple tasks on one or more resources of a computing environment, and sequentially execute the task instructions according to the edges between the vertices. When an at least one task encounters an error, the instructions pause execution of an ensuing task instruction in the graph.Type: GrantFiled: November 20, 2015Date of Patent: November 6, 2018Assignee: VCE IP Holding Company LLCInventors: Akshaya Mahapatra, Vandana Rao
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Patent number: 10120745Abstract: Corruption of program stacks is detected by using guard words placed in the program stacks. An instruction, which is to be used in protecting stacks of a computing environment, is provided in a called routine, based on determining that the called routine is to include logic to detect corruption of stacks. The instruction in the called routine is to check a guard word provided by a calling routine to determine whether a stack is corrupt.Type: GrantFiled: January 6, 2016Date of Patent: November 6, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Karl J. Duvalsaint, Michael K. Gschwind, Valentina Salapura
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Patent number: 10120746Abstract: The flow of events though an event-analysis system is controlled by a number of event throttles which filter events, prioritize events and control the rate at which events are provided to event-processing components of the event-analysis system. Incoming events to the event-analysis system are associated with a profile, and a metrics engine generates metrics based on the incoming events for each profile. The flow of events to the metrics engine is controlled on a per profile basis, so that excessive generation of new metrics and new profiles is limited. If the system from which the events originate is compromised, metrics associated with compromised profiles may be frozen to avoid corrupting existing metrics. Processing of events and anomalies by analysis engines within the event-analysis system may be delayed to allow the accumulation of metrics necessary for accurate analysis.Type: GrantFiled: June 14, 2016Date of Patent: November 6, 2018Assignee: Amazon Technologies, Inc.Inventor: Nima Sharifi Mehr
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Patent number: 10120747Abstract: Systems, methods and tools for performing a root cause analysis and improvements to the root cause detection by changing the way analysts and troubleshooters interact with the error reporting files to detect injection points that indicate the root cause of a system error. The systems, methods and tools record the observable behavior of users as the users review files to identify behavioral clues of the user to infer a level of interest in sections of the files being viewed. The systems identify correlations between user behavior and emotive expression to calculate a probability of event data being the root cause of an error. The systems may manually or automatically generate one or more tags in the reviewed file for each of the sections of the file that has a probability of being a root cause of a defect and the tags may vary as a function of the probability.Type: GrantFiled: August 26, 2016Date of Patent: November 6, 2018Assignee: International Business Machines CorporationInventors: Hernan A. Cunico, Jonathan Dunne, Jeremiah O'Connor, Asima Silva