Abstract: Technologies for field-programmable gate array (FPGA) processing include a computing device having a field-programmable gate array (FPGA) and a virtual FPGA controller (VFC). The computing device generates a user-specific platform profile (PP) that identifies one or more FPGA applications to be instantiated. The computing device synthesizes each FPGA application identified by the PP to generate a bit stream image that is associated with the PP and saves the bit stream image in a profile storage of the computing device. The computing device generates a virtual memory address that is indicative of the identified FPGA applications in response to saving the bit stream image. The VFC translates the virtual memory address to a user segment of the FPGA and a logical element (LE) offset within the user segment. The FPGA executes the bit stream associated with the PP with the FPGA at the LE offset. Other embodiments are described and claimed.

Abstract: An electronic device is provided to include a semiconductor memory that includes: a substrate including a first region and a second region different from the first region; an interlayer dielectric layer formed over the substrate; a first conductive pattern located over the first region and formed in the interlayer dielectric layer, the first conductive pattern including a planarized top surface with a top surface of the interlayer dielectric layer; a second conductive pattern located over the second region and formed in the interlayer dielectric layer, the second conductive pattern including at least a portion recessed below a top surface of the interlayer dielectric layer; a variable resistance pattern formed over the interlayer dielectric layer the variable resistance pattern having a bottom surface coupled to the first conductive pattern and exhibiting different resistance values; and a capping layer pattern formed over the variable resistance pattern.

Abstract: A cache memory that selectively enables and disables speculative reads from system memory is disclosed. The cache memory may include a plurality of partitions, and a plurality of registers. Each register may be configured to stored data indicative of a source of returned data for previous requests directed to a corresponding partition. Circuitry may be configured to receive a request for data to a given partition. The circuitry may be further configured to read contents of a register corresponding to the given partition, and initiate a speculative read dependent upon the contents of the register.

Abstract: Method and system are provided for object caching with mobility management for mobile data communication. The method may include: intercepting and snooping data communications at a base station between a user equipment and a content server without terminating communications; implementing object caching at the base station using snooped data communications; implementing object caching at an object cache server in the network, wherein the object cache server proxies communications to the content server from the user equipment; and maintaining synchrony between an object cache at the base station and an object cache at the object cache server.

Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.

Abstract: A computer-implemented method includes, in a transactional memory environment comprising a plurality of processors, identifying one or more selected processors and identifying one or more coherence privilege state indicators. The one or more coherence privilege state indicators are associated with the one or more selected processors. A coherence privilege behavioral pattern is determined based on the one or more coherence privilege state indicators. A corresponding computer program product and computer system are also disclosed.

Abstract: Tracking a processor instruction is provided to limit a speculative mis-prediction. A non-speculative read set indication and/or write set indication are maintained for a transaction. The indication(s) are stored in cache. In addition, a queue(s) of at least one address corresponding to a speculatively executed instruction is maintained. For a received request from a processor, a transaction resolution process takes place, and a resolution is performed if an address match in the queue is detected. The resolution includes to hold a response to the receive request until the speculative instruction is committed or flushed.

Abstract: A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.

Abstract: An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used (LRU) circuitry to keep track of least recently used cache lines kept in a higher level of the multi-level system memory. The memory controller also includes idle time predictor circuitry to predict idle times of a lower level of the multi-level system memory. The memory controller is to write one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory in response to the idle time predictor circuitry indicating that an observed idle time of the lower level of the multi-level system memory is expected to be long enough to accommodate the write of the one or more lesser used cache lines from the higher level of the multi-level system memory to the lower level of the multi-level system memory.

Abstract: A data processing system includes interconnect circuitry providing a plurality of memory transaction paths between one or more transaction masters, including a processor, debugging circuitry and a DMA unit, and one or more transaction slaves including a non-volatile memory, a DRAM memory and an I/O interface. A cache memory is provided between the interconnect circuitry and the non-volatile memory. This cache memory may be a two way set associative cache memory. The cache memory may serve as a read-only cache memory. A cache miss will result in a line fill of a cache line including the target data which was missed. If prefetching is enabled for the cache memory and the transaction was attempting to read a program instruction, then a prefetch operation may be performed in which a further contiguous cache line of data is also fetched into the cache memory upon the cache miss.

Abstract: This disclosure pertains to using traffic classes to selectively store data into cache memory or into system memory. A cache controller can map the traffic class of incoming data to portions of the cache memory allocated for corresponding traffic classes of data.

Abstract: A method, system and memory controller for implementing memory hierarchy placement decisions in a memory system including direct routing of arriving data into a main memory system and selective injection of the data or computed results into a processor cache in a computer system. A memory controller, or a processing element in a memory system, selectively drives placement of data into other levels of the memory hierarchy. The decision to inject into the hierarchy can be triggered by the arrival of data from an input output (IO) device, from computation, or from a directive of an in-memory processing element.

Abstract: Provided are a computer program product, system, and method for considering a frequency of access to groups of tracks and density of the groups to select groups of tracks to destage. One of a plurality of densities for one of a plurality of groups of tracks is incremented in response to determining at least one of that the group is not ready to destage and that one of the tracks in the group in the cache transitions to being ready to destage. A determination is made of a group frequency indicating a frequency at which tracks in the group are modified. At least one of the density and the group frequency is used for each of the groups to determine whether to destage the group. The tracks in the group in the cache are destaged to the storage in response to determining to destage the group.

Abstract: Systems and methods for managing contiguous addressing via virtual paging registers in a page table used in a high-performance computing platform. One embodiment commences upon initializing a first paging register with a first virtual address of a first virtual address length to form a first virtual address space, then receiving a request from a process to allocate physical memory corresponding to a second virtual address request. A memory allocator allocates the requested physical memory from a physical memory location determined by the memory allocator. An operating system or other sufficiently privileged access identifies a second paging register that is contiguously adjacent to the first paging register. If the second paging register is already in use, then the method identifies an unused (third) paging register into which the contents of the second paging register can be relocated. The method stores the second virtual address into the now freed-up second paging register.

Abstract: Address translation apparatus comprises translation circuitry to access an ordered set of two or more address translation tables stored at respective storage locations to generate an address translation between an input virtual memory address in a virtual memory address space and a respective translated memory address in a translated memory address space. Each address translation table in the ordered set of two or more address translation tables is configured to provide translation data indicating mappings between virtual memory addresses and translated memory addresses for a contiguous range of virtual memory addresses applicable to that address translation table. The ordered set of address translation tables are ordered with respect to one another according to an order of their respective ranges of virtual memory addresses for which they provide translation data.

Abstract: An apparatus and method are described for managing TLB coherence. For example, one embodiment of a processor comprises: one or more cores to execute instructions and process data; one or more translation lookaside buffers (TLBs) each comprising a plurality of entries to cache virtual-to-physical address translations usable by the set of one or more cores when executing the instructions; one or more epoch counters each programmed with a specified epoch value; and TLB validation logic to validate a specified set of TLB entries at intervals specified by the epoch value.

Abstract: A single chip microcontroller has a master core and at least one slave core. The master core is clocked by a master system clock and the slave core is clocked by a slave system clock and wherein each core is associated with a plurality of peripheral devices to form a master microcontroller and a slave microcontroller, respectively. A communication interface is provided between the master microcontroller and the slave microcontroller, wherein the communication interface has a plurality of configurable directional data registers coupled with a flow control logic which is configurable to assign a direction to each of the plurality of configurable data registers.

Abstract: Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

Abstract: The current consumed by flash memory devices on the channels of a solid-state drive (SSD) device will be in the form of a time varying waveform, characterized mainly by the types of commands being processed, and are often in the form of periods of constant levels interspersed with very short high current peaks or spikes. When multiple commands are being processed, significant high current peak demands and current surges can occur. The invention described herein is a device and method for scheduling commands to be processed in order to reduce the size of peak current demands and current surges. According to one embodiment of the invention, the device and method for scheduling a command uses look-up tables to determine the time to initiate the processing of the command by the flash memory devices.

Abstract: Aspects include sending a request to perform a unit of work that includes a synchronous I/O operation. The sending is from an operating system (OS) executing on a server to firmware located on the server. The synchronous I/O request includes a command request block that includes an operation code identifying the synchronous I/O operation and a identifier of a persistent storage control unit (SCU). The OS waits for the synchronous I/O to complete and the unit of work remains active during the waiting. The firmware detects that the synchronous I/O operation has completed. A command response block that includes completion status information about the synchronous I/O operation is received by the OS from the firmware. The unit of work is completed in response to the I/O operation completing.

Abstract: An embedded computer system includes a processor, an interrupt source, an interrupt controller and a cache memory subsystem. In response to a request from the processor to read a data element, the cache memory subsystem fills cache lines in a cache memory with data elements read from an upper-level memory. While filling a cache line the cache memory subsystem is unable to respond to a second request from the processor which also requires a cache line fill. In response to receiving an indication from an interrupt source, the interrupt controller provides an indication substantially simultaneously to the processor and to the cache memory subsystem. In response to receiving the indication from the interrupt controller, the cache memory subsystem terminates a cache line fill and prepares to receive another request from the processor.

Abstract: A direct memory access (DMA) transmission control method and apparatus, where the method includes selecting a target channel for the target DMA task according to a priority corresponding to the target DMA task when a DMA transmission request for transmitting data of a target DMA task is received, querying a task type and a priority of another DMA task that has occupied a channel and a task type of the target DMA task when the other DMA task exists on the DMA channel, comparing the task type and the priority of the other DMA task that has occupied the channel with the task type and the priority of the target DMA task, and controlling data transmission on the DMA channel according to a comparison result. Hence, the urgent DMA task can be preferentially processed.

Abstract: An electronic device coupling system includes a plurality of electronic devices and an external power supply. The plurality of electronic devices includes a master device and a plurality of slave devices coupleable to the master device one by one. Each electronic device has a sequence number according to an insertion sequence, the sequence number is corresponds to all the information of local electronic device, the sequence numbers of the plurality of electronic devices are sorted according to the insertion sequence, the sequence number of the master device is a first number of the sequence, and the master device is coupleable to at least one slave device by the sequence number and all the information corresponding to the sequence number. The at least one slave device is a customized group of the master device.

Abstract: Aspects include acquiring measurement data of a synchronous input/output (I/O) link between an operating system and a recipient. The acquiring measurement data can include monitoring operating system usage of synchronous I/O commands on the synchronous I/O link and storing the operating system usage in a measurement block as the measurement data. Further, the measurement block is accessible by the operating system to determine that the measurement data is acquired.

Abstract: A method and a computer readable medium comprising instructions for upgrading a firmware of a peripheral device connected to a host device via a Peripheral Component Interconnect Express (PCIe) bus from the operating system (OS) of the host device is disclosed. In one embodiment, the method and computer readable medium instructions includes halting host device access to the peripheral device after detecting the peripheral device has completed a shutdown sequence, and resetting the peripheral device after a predetermined time period after completion of the shutdown sequence. The method and computer readable medium instructions further includes initializing the firmware stored in a persistent storage location of the peripheral device, and re-establishing a connection between the peripheral device and the host device. In one embodiment, the predetermined time period is greater than a time it takes for the host device to detect the peripheral device has completed the shutdown sequence.

Abstract: A bridge hoard includes a printed circuit board (PCB) and a protocol converter mounted on the PCB to perform a conversion operation converting between a first communication protocol and a second communication protocol different from the first communication protocol. The bridge board further includes a first connector configured to communicate according to the first communication protocol and a second connector configured to communicate according to the second communication protocol. The bridge board additionally includes a hole formed in the PCB. The PCB is shaped as a concave polygon. The concave polygon includes a first region and a second region. The first region includes a first edge and a second edge, which extends in parallel to the first edge, along a first direction. The second region includes a third edge and a fourth edge, which extends in parallel to the third edge, along a second direction perpendicular to the first direction.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: The present invention provides an integrated system-on-chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. The device further includes a driver interface and coupled to the driver module and configured to be coupled to a silicon photonics device. In an example, a control block is configured to receive and send instruction(s) in a digital format to the communication block and is configured to receive and send signals in an analog format to communicate with the silicon photonics device.

Abstract: A communication system with serial ports for automatically identifying device types and communication protocols and method thereof are described. The communication system and method are capable of automatically identifying the device types and communication protocols of interface devices with different serial device numbers which are disposed in the serial port architecture. Furthermore, the drivers are capable of performing a serial communication based on the serial port architecture for matching the device types and communication protocols correspondingly, thereby reducing the development and manufacturing costs of communication system. Moreover, the user of an application program module only needs to provide the device numbers and data control information without the cooperation of hardware circuits and manufacturing technique of the interface devices to complete the automatic control and monitoring tasks of the interface devices to increase the utilization convenience.

Abstract: Technologies are described herein for power management in a peripheral device. A bridge is coupled to a communication link that provides power. The bridge determines an available power from the communication link. The bridge informs a peripheral device coupled to the bridge of the available power.

Abstract: An embodiment bus device with a programmable address includes a bus communication circuit connected to a bus terminal, a first pin terminal, a memory having a first register with a first address stored therein and a second register, and a state logic circuit. The state logic circuit detects a chip select signal on the first pin terminal, receives a first message through the bus communication circuit while the chip select signal is asserted, determines that the first message indicates an address set command, and saves an address value in the first message as a second address in the second register in response to a target address in the first message matching the first address. The state logic circuit further processes a second message received through the bus communication circuit in response to a target address of the second message matching the second address.

Abstract: A system may include an interface circuit and a plurality of wire buses electrically coupled with one another. The interface circuit may include transmitters which change states of the plurality of wire buses to transmit a plurality of multilevel symbols. The transmitters may drive wire buses, coupled to each other, to a termination voltage level.

Abstract: A circuit arrangement for handling write and read requests between a master circuit and a slave circuit in different clock domains includes first and second write FIFO circuits, a read FIFO circuit, and a write acknowledgment circuit. The first write FIFO circuit is configured and arranged to receive and buffer write addresses of write requests received from a master circuit and addressed to a slave circuit. The second write FIFO circuit is configured and arranged to receive and buffer write data associated with the write addresses of the write requests. The read FIFO circuit is configured and arranged to receive and buffer read addresses of read requests received from the master circuit and addressed to the slave circuit. The write acknowledgment control circuit is configured and arranged to transmit an acknowledgement to a write request to the master circuit before the slave circuit issues a response to the write request.

Abstract: A method includes communicating between at least first and second devices over a bus in accordance with a bus address space, including providing direct access over the bus to a local address space of the first device by mapping at least some of the addresses of the local address space to the bus address space. In response to indicating, by the first device or the second device, that the second device requires to access a local address in the local address space that is not currently mapped to the bus address space, the local address is mapped to the bus address space, and the local address is accessed directly, by the second device, using the mapping.

Abstract: Embodiments include a processor capable of supporting multi-mode and corresponding methods. The processor includes front end units, a number of processing elements more than a number of the front end units; and a controller configured to determine if thread divergence occurs due to conditional branching. If there is thread divergence, the processor may set control information to control processing elements using currently activated front end units. If there is not, the processor may set control information to control processing elements using a currently activated front end unit.

Abstract: A signal processing device including: one or more vector processors configured to perform vector processing to a signal using a parameter, one or more scalar processors configured to perform scalar processing for generating the parameter, a first circuit coupled to the one or more vector processors and the one or more scalar processors and configured to transfer the parameter from the one or more scalar processors to the one or more vector processors, and a second circuit coupled to the one or more vector processors and another circuit that inputs the signal to the second circuit, and configured to transfer the signal among the one or more vector processors and the other circuit.

Abstract: For bridges over waterways which are susceptible to scour, the load carrying capacity of the substructure may be reduced by scour. These bridges must be evaluated for reduced load rating and/or posting limits. Here, the substructure load rating is used in connection with calculating the bridge load rating. This is often limited by the substructure load carrying capacity and the tolerable deformation. Thus, bridges impacted by scour need to be judged based on both the superstructure and substructure components. The system/process to assess the substructure load rating uses an analytical method which combines numerical methods and empirical calculations to predict the behavior of a bridge's superstructure and substructure. Limited instrumentation is installed at critical locations on the bridge. The measurements are then used to verify and refine predictions to arrive at a substructure load rating which is usable with the superstructure load rating to define a safe load carrying capacity.

Abstract: Embodiments relate to gathering materials on an ocean surface. Initially, an initial distribution of material is determined based on observational sources, and the material is represented by particles in a numerical ocean model. Trajectories for the numerical ocean model are determined based on modeled surface currents data, and velocity gradients are computed along a corresponding trajectory of the trajectories for each of the particles based on the initial distribution. At this stage, deformation tensors are computed for each of the particles based on the velocity gradients, and a dilation map for the particles is generated based on a time step tensor of the plurality of deformation tensors for each of the particles. Collection of the material is monitored based on the dilation map.

Abstract: To reduce the processing amount of a field multiplication. A matrix application apparatus computes a vector b by multiplying a vector a and a matrix A, provided that a denotes a k-th order vector having elements a0, . . . , ak?1 (a0, . . . , ak?1?GF(xq)), b denotes an m-th order vector having elements b0, . . . , bm?1 (b0, . . . , bm?1?GF(xq)), and A denotes a m-by-k Vandennonde matrix. A polynomial multiplication part computes a value bi. An order reduction part designates gi?hif? as the value bi by using a polynomial hi obtained by dividing a part of the value bi having an order equal to or higher than q by Xq and a polynomial gi formed by a part of the value bi having an order lower than q.

Abstract: Techniques provided herein allow for a plurality of weighted samplings without replacement to be performed in O(n) time. According to some embodiments, the weighted sampling without replacement may be performed on a data set X of data elements {x1, x2, x3, . . . , xn}, where each data element xi of the data set X has an associated weight wi. The data set X may comprise data generated by a social networking system. Each data element xi in the data set X may be assigned with a random score si based on the weight wi associated with the data element xi. The random score si can be used to perform weighted sampling without replacement.

Abstract: Systems and methods for identifying elements of a mobile application are described. One or more processors can receive a request to identify elements of a mobile application. The processors can map a plurality of views included in the mobile application and associated transitions between the plurality of views. For each of the plurality of views, the processors can determine a category of the view. The processors can then store, for the mobile application, a data structure identifying each of the plurality of views, and for each of the plurality of views, the category of the view, and one more transitions to others of the plurality of views for use in responding to a request for content from the mobile application.

Abstract: A tool for standardized layout transformations of BIDI data exchanged between legacy and modern systems is provided. The tool retrieves client connection information from a client request for data. The tool determines, based, at least in part, on the client connection information, a client application's operating system. The tool determines whether the data requested in the client request is BIDI data. Responsive to a determination that the data requested is BIDI data, the tool initiates a layout transformation of the data requested at a single point within the database server. The tool returns transformed BIDI data to the client application.

Abstract: A method for generating an assent indication in a document approval and review function can include loading a document for editing in a document editor and determining a set of authors for the document. The method also can include modifying a title of the document to include an identity of at least one of the authors in the set. Finally, the method can include changing a visual appearance in the title of an identity of the assenting author responsive to one of the authors in the set assenting to a publication of the document.

Abstract: There is provided a method for preloading the glyphs required to display the content of a system. In accordance with an embodiment of the present technique, only those glyphs which are present in the system upon startup or synchronization of an electronic device are preloaded. The glyphs present upon startup or synchronization of the electronic device may be determined by scanning the system. In an illustrated embodiment, scanning the system may include analyzing models and views to determine the glyphs present in the system.

Abstract: One or more processors identify one or more character errors in a document. The one or more processors replace a character having the identified one or more character errors with a replacement character. The replacement of the character error with the replacement character allows deep parsing of the document to complete. The one or more processors apply to the document one or both of a deep parsing and natural language processing after the replacing.

Abstract: Embodiments presented herein disclose techniques for transforming input documents having disparate formats into a normalized format (e.g., Atom, RSS, HTML, customized XML, etc.). According to one embodiment, a plurality of fields is identified in an input document that has a given format. Each field includes a descriptor and text content associated with the descriptor. For each field, semantic properties are evaluated for the descriptor and text content against a plurality of mapping rules to determine whether the field is consistent with one of a plurality of fields of a target format. Each mapping rule specifies characteristics associated with one of the fields in the target format. Once so determined, a mapping from the first field to the second field is defined.

Abstract: Systems and methods may include updating subsets of elements of electronic documents. Associations of types of mutations, mutation locations, and subsets to update are stored in a database. A mutation to the element is received, and a type and location of the mutation are determined. Based on a stored association, a subset of the element is determined. The determined subset is associated with the determined type and determined location. The element is updated by updating the subset, and the updated element is displayed on a user device.

Abstract: A method of displaying webpage comments is disclosed. The method may comprise sending a webpage browse request to a server, the webpage browse request comprising a webpage address. The method may also comprise receiving webpage information corresponding to the webpage address returned by the server, the webpage information comprising source code and a comment object information list, and each piece of comment object information in the comment object information list comprising position information of a webpage article element commented on by a user. The method may also comprise rendering and displaying a webpage article corresponding to the webpage address according to the source code comprised in the webpage information, and displaying webpage comments corresponding to the webpage address according to the comment object information list.

Abstract: A method, computer readable medium and apparatus for transforming a request for web content includes obtaining at a web content optimization computing apparatus a hypertext transfer protocol (HTTP) request for a web page from at least one client computing device. An eXtensible Markup Language (XML) document including a representation of the HTTP request is generated with the web content optimization computing apparatus. At least one rule document associated with the HTTP request is identified with the web content optimization computing apparatus. The identified at least one rule document is transformed with the web content optimization computing apparatus into an eXtensible Stylesheet Language (XSL) document including one or more templates. One or more of the templates of the XSL document are applied with the web content optimization computing apparatus to transform the XML document. The transformed XML document is provided by the web content optimization computing apparatus.

Abstract: Methods and systems are provided for rearranging the content within a sub-region of a web page in response to resizing the sub-region, the content including a plurality of columns each having a respective width parameter, the system including a processor configured to implement the steps of: detecting a resizing event associated with the sub-region; determining a span value associated with the resized sub-region; determining a subset of the plurality of columns that fit within the span value based on the width parameters; and displaying the subset of columns within the resized sub-region.