Abstract: A module includes a circuit package having multiple electronic components on a substrate, a molded compound disposed over the substrate and the electronic components, and an external shield disposed on at least one outer surface of the circuit package. The external shield is segmented into multiple external shield partitions that are grounded, respectively. Adjacent external shield partitions of the multiple external shield partitions are separated by a corresponding gap located between adjacent electronic components of the multiple electronic components. The external shield is configured to protect the circuit package from external electromagnetic radiation and environmental stress. Each corresponding gap separating the adjacent external shield partitions is configured to provide internal shielding of at least one of the electronic components, between which the corresponding gap is located, from internal electromagnetic radiation generated by the other of the adjacent electronic components.

Abstract: A semiconductor device package includes a first circuit layer having a first surface and a second surface opposite the first side, a first electronic component, a shielding element, a shielding layer and a molding layer. The first electronic component is disposed over the first surface of the first circuit layer, and electrically connected to the first circuit layer. The shielding element is disposed over the first surface of the first circuit layer, and is electrically connected to the first circuit layer. The shielding element is disposed adjacent to at least one side of the first electronic component. The shielding layer is disposed over the first electronic component and the shielding element, and the shielding layer is electrically connected to the shielding element. The molding layer encapsulates the first electronic component, the shielding element and a portion of the shielding layer.

Abstract: A patterned shield structure applied to an integrated circuit (IC) is disposed between an inductor and a substrate of the integrated circuit. The patterned shield structure includes a center structure unit, a first patterned structure unit, and a second patterned structure unit. The center structure unit includes a first sub-center structure unit and a second sub-center structure unit. The second sub-center structure unit and the first sub-center structure unit are symmetrically disposed with respect to a middle of the center structure unit. The first patterned structure unit is disposed on one side of the center structure unit. The second patterned structure unit is disposed on another side of the center structure unit. The second patterned structure unit and the first patterned structure unit are symmetrically disposed with respect to the center structure unit.

Abstract: An integrated circuit package including at least one integrated circuit component, at least one electromagnetic interference shielding layer and an insulating encapsulation is provided. The at least one integrated circuit component includes an active surface, a plurality of sidewalls connected to the active surface and a plurality of conductive pillars protruding from the active surface. The at least one electromagnetic interference shielding layer covers the sidewalls of the at least one integrated circuit component, and the at least one electromagnetic interference shielding layer is electrically grounded. The insulating encapsulation encapsulates the at least one integrated circuit component and the at least one electromagnetic interference shielding layer, and the conductive pillars of the at least one integrated circuit component are accessibly exposed by the insulating encapsulation. Methods of fabricating the integrated circuit package are also provided.

Abstract: A compartment EMI shield is provided that is suitable for use in system module packages having thin form factors and/or smaller widths and/or lengths. The compartment EMI shield comprises a fence arranged along a compartment boundary at least in between first and second sets of electrical components of the system module package. The fence being configured to attenuate EMI of a frequency of interest traveling in at least one of a first direction and a second direction, where the first direction is from the first set of electrical components toward the second set of electrical components and the second direction is from the second set of electrical components toward the first set of electrical components.

Abstract: An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein.

Abstract: A wafer level package device and method are disclosed that include a warpage compensation metal adhered to a backside of a semiconductor wafer for minimizing warpage of the semiconductor wafer, where multiple metal features have been formed on the device side of the semiconductor substrate. The warpage compensation metal may include a copper film.

Abstract: Embodiments herein may relate to a package with one or more layers. A silicon die may be coupled with the one or more layers via an adhesive. A package stiffener may also be coupled with the adhesive adjacent to the die. A magnetic thin film may be coupled with the package stiffener. Other embodiments may be described and/or claimed.

Abstract: An apparatus for generating an identification key is provided. The apparatus may include a first conductive layer formed on a semiconductor chip, a second conductive layer formed on the semiconductor chip, wherein a spacing between the first conductive layer and the second conductive layer is equal to or greater than a first threshold and equal to or less than a second threshold, and a reader configured to determine whether a first node associated with the first conductive layer and a second node associated with the second conductive layer are shorted, and to provide an identification key.

Abstract: An example device includes a silicon substrate having a first substrate surface and a second substrate surface; a plurality of layers associated with one or more electronic components of an integrated circuit (IC), where the plurality of layers are deposited on the second substrate surface; a lithium-based battery having a plurality of battery layers deposited on the first substrate surface of the silicon substrate, where the lithium-based battery includes an anode current collector and a cathode current collector; a first through-silicon via (TSV) passing through the silicon substrate and providing an electrical connection between the anode current collector and the plurality of layers associated with the one or more electronic components of the IC; and a second TSV passing through the silicon substrate and providing an electrical connection between the cathode current collector and the plurality of layers associated with the one or more electronic components of the IC.

Abstract: A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on first surface of the lowermost layer, a conductor post having upper surface facing the first surface of the lowermost layer, a metal post formed such that the metal post is protruding from second surface of the lowermost layer and is positioned at lower surface of the conductor post, an electronic component embedded in the lowermost layer such that the component is positioned on second surface side of the lowermost layer and has an electrode facing the first surface of the lowermost layer, and via conductors formed in the lowermost layer and including first and second via conductors such that the first via conductor is connecting the first conductor layer and the upper surface of the conductor post and the second via conductor is connecting the first conductor layer and the electrode of the component.

Abstract: A structure of an under bump metallization and a method of forming the same are provided. The under bump metallization has a redistribution via hole, viewed from the top, in a round shape or a polygon shape having an angle between adjacent edges greater than 90°. Therefore, the step coverage of the later formed metal layer can be improved.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip.

Abstract: A center pad or paddle that is shaped with three or more curved spires which are symmetrical in form about axis that radiate from the center of the integrated circuit package, which takes advantage of the surface tension of solder to produce increased rotational align forces and increased centering forces during package soldering when aligned to a matching shaped pad on the surface of a circuit board.

Abstract: Various embodiments provide a semiconductor chip, wherein the semiconductor chip comprises a first contact area and a second contact area both formed at a frontside of the semiconductor chip; a passivation layer arranged at the frontside between the first contact area and the second contact area; and a contact stack formed over the frontside of the semiconductor chip and comprising a plurality of layers, wherein at least one layer of the plurality of layers is removed from the passivation layer and boundary regions of the contact areas being adjacent to the passivation layer and wherein at least one another layer of the plurality of different layer is present in the boundary region of the contact areas adjoining the passivation layer.

Abstract: The present disclosure provides bond pad structures, boning ring structure; and MEMS device packaging methods. An exemplary bonding pad structure includes a plurality of first metal blocks made of a first metal material; and a plurality of second metal blocks made of a second metal material. The plurality of first metal blocks are used to prevent the squeezing out and extending of the plurality of second metal blocks. On at least one equal dividing plane of the bonding pad structure, the first metal material is shown at least one time; and the second metal material is shown at least one time.

Abstract: An integrated circuit structure includes a substrate, a PPI over the substrate, a solder region over and electrically coupled to a portion of the PPI, and a molding compound molding a lower portion of the solder region therein. A top surface of the molding compound is level with or lower than a maximum-diameter plane, wherein the maximum-diameter plane is parallel to a major surface of the substrate, and the maximum-diameter of the solder region is in the maximum-diameter plane.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

Abstract: A method of packaging includes placing a package component over a release film, wherein solder regions on a surface of the package component are in physical contact with the release film. Next, A molding compound filled between the release film and the package component is cured, wherein during the step of curing, the solder regions remain in physical contact with the release film.

Abstract: An assembly of a semiconductor chip having pads to a substrate having pads aligned to receive the semiconductor chip is provided, whereby at least one of the semiconductor chip pads and substrate pads include solder bumps. The solder bumps are deformed against the substrate pads and the semiconductor chip pads, whereby an underfill material is applied to fill the gap between the semiconductor chip and substrate. The underfill material does not penetrate between the deformed solder bumps, the semiconductor chip pads, and the substrate pads. At least one of the solder bumps have not been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads, and at least another one of the solder bumps have been melted or reflowed to make a metallurgical bond between the semiconductor chip pads and the substrate pads.

Abstract: As one embodiment, a method of manufacturing a semiconductor device includes the following steps. That is, the method of manufacturing a semiconductor device includes a first step of applying ultrasonic waves to a ball portion of a first wire in contact with a first electrode of the semiconductor chip while pressing the ball portion with a first load. In addition, the method of manufacturing a semiconductor device includes a step of, after the first step, applying the ultrasonic waves to the ball portion while pressing the ball portion with a second load larger than the first load, thereby bonding the ball portion and the first electrode.

Abstract: Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in the die package are provided. The compressive dielectric layer reduces or eliminates bowing of the die package. As a result, the risk of broken redistribution layer (RDL) due to bowing is reduced or eliminated. In addition, the compressive dielectric layer, which is formed between the conductive TSV columns and surrounding molding compound, improves the adhesion between the conductive TSV columns and the molding compound. Consequently, the reliability of the die package is improved.

Abstract: The present invention relates to a bonding method for connecting a first wafer and a second wafer, wherein firstly a first adhesive layer is deposited onto a surface of the first wafer. Furthermore, a second adhesive layer is deposited onto the first adhesive layer, and the two adhesive layers are structured by way of selective removal of both adhesive layers in at least one predefined region of the first wafer, Moreover, the first wafer is connected to the second wafer by way of pressing a surface of the second wafer onto the second adhesive layer, wherein the second adhesive layer is more flowable that the first adhesive layer on connecting the first wafer to the second wafer.

Abstract: A package includes a substrate, an Under-Bump Metallurgy (UBM) penetrating through the substrate, a solder region over and contacting the UBM, and an interconnect structure underlying the substrate. The interconnect structure is electrically coupled to the solder region through the UBM. A device die is underlying and bonded to the interconnect structure. The device die is electrically coupled to the solder region through the UBM and the interconnect structure. An encapsulating material encapsulates the device die therein.

Abstract: A light emitting diode package including a circuit layer, a light-shielding layer, a plurality of light emitting diodes and an encapsulation layer is provided. A thickness of the circuit layer is less than 100 ?m. The light-shielding layer is disposed on a first surface of the circuit layer and the light-shielding layer has a plurality of apertures. The light emitting diodes are disposed on the first surface of the circuit layer and in the apertures of the light-shielding layer. The light emitting diodes are electrically connected to the circuit layer. The encapsulation layer covers the light-shielding layer. A refractive index of the encapsulation layer is 1.4 and to 1.7. The Young's modulus of the encapsulation layer is larger than or equal to 1 GPa. A thickness of the encapsulation layer is greater than thicknesses of the light emitting diodes.

Abstract: A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element mounted on the first circuit board; and a second semiconductor package including a second circuit board and a second semiconductor element mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package. The first semiconductor package further includes a sealing resin sealing the first semiconductor element; a conductive layer located in contact with the sealing resin; and a thermal via connected to the conductive layer and located on the first circuit board.

Abstract: A thermally enhanced semiconductor assembly with three dimensional integration includes a stacked semiconductor sub-assembly electrically coupled to a wiring board by bonding wires. A heat spreader that provides an enhanced thermal characteristic for the stacked semiconductor sub-assembly is disposed in a through opening of a wiring structure. Another wiring structure disposed on the heat spreader not only provides mechanical support, but also allows heat spreading and electrical grounding for the heat spreader by metallized vias. The bonding wires provide electrical connections between the sub-assembly and the wiring board for interconnecting devices assembled in the sub-assembly to terminal pads provided in the wiring board.

Abstract: Semiconductor die assemblies including stacked semiconductor dies having parallel plate capacitors formed between adjacent pairs of semiconductor dies in the stack, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor die assembly includes a first semiconductor die and a second semiconductor die stacked over the first semiconductor die. The first semiconductor die includes an upper surface having a first capacitor plate formed thereon, and the second semiconductor die includes a lower surface facing the upper surface of the first semiconductor die and having a second capacitor plate formed thereon. A dielectric material is formed at least partially between the first and second capacitor plates. The first capacitor plate, second capacitor plate, and dielectric material together form a capacitor that stores charge locally within the stack, and that can be accessed by the first and/or second semiconductor dies.

Abstract: A semiconductor package includes a printed circuit board, a resistor circuit, and first and second semiconductor chips. First and second pads are on a first surface of the printed circuit board, and external connection terminal is on a second surface of the printed circuit board. The resistor circuit has a first connection terminal connected to the first pad and a second connection terminal connected to the second pad. The first semiconductor chip is connected to the first pad and the second semiconductor chip is stacked on the first semiconductor chip and connected to the second pad. The printed circuit board includes a signal transfer line connecting a branch in the printed circuit board to the external connection terminal. A first transfer line connects the branch to the first pad. A second transfer line connects the branch to the second pad.

Abstract: Techniques are disclosed for making a flexible laminated circuit board using a metal conductor onto which a SMD may be attached. Conductive metal strips may be laminated to form a flexible substrate and the metal strips may then be perforated for the placement of LED package leads. The LED packages may be attached to the conductive strips using solder or a conductive epoxy and the upper laminate layer may include perforations exposing portions of the metal strips for the attachment of the LED packages. Alternatively, strings of LED packages may be fabricated by attaching LED packages to conductive strips and these strings may be laminated between flexible sheets to form a laminated LED circuit. Plastic housings may aid in attaching the LED packages to the conductive strips. The plastic housings and/or the laminate sheets may be made of a reflective material.

Abstract: A display includes a plurality of pixel chips, chixels, provided on a substrate. The chixels and the light emitters thereon may be shaped, sized and arranged to minimize chixel, pixel, and sub-pixel gaps and to provide a seamless look between adjacent display modules. The substrate may include light manipulators, such as filters, light converters and the like to manipulate the light emitted from light emitters of the chixels. The light manipulators may be arranged to minimize chixel gaps between adjacent chixels.

Abstract: A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A metallic plated hole can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.

Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.

Abstract: A power semiconductor module including a positive-side switching device and a positive-side diode device which are mounted on a positive-side conductive pattern, and a negative-side switching device and a negative-side diode device which are mounted on an output-side conductive pattern. When an insulating substrate is viewed in plan view, the positive-side diode device and the negative-side diode device are disposed between the positive-side switching device and the negative-side switching device, and the negative-side diode device is disposed closer to the positive-side switching device than the positive-side diode device is.

Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has a redistribution layer, at least one die over the redistribution layer, through interlayer vias on the redistribution layer and aside the die and a molding compound encapsulating the die and the through interlayer vias disposed on the redistribution layer. The semiconductor package has connectors connected to the through interlayer vias and a protection film covering the molding compound and the die. The protection film is formed by a printing process.

Abstract: A package may include a plurality of stacked semiconductor devices (chips) is disclosed. Each chip may include through vias (through silicon vias—TSV) that can provide an electrical connection between chips and between chips and external connections, such as solder connections or solder balls. Electro static discharge (ESD) protection circuitry may be placed on a bottom chip in the stack even when through vias connect circuitry on a top chip in the stack exclusive of the bottom chip. In this way, ESD protection circuitry may be placed in close proximity to the ESD event occurring at an external connection. In particular, every chip in the stack of semiconductor chips may have circuitry electrically connected to the external connection and by placing ESD protection circuitry on the bottom chip closest to the electrical connection, instead of on all chips ESD protection may be more area efficient.

Abstract: A silicon controlled rectifier (SCR) using separate bipolar transistors is disclosed. The separate bipolar SCR enables access to internal feedback terminals of the SCR, which may then may be used to adjust the gain of individual bipolar transistors. Further embodiments provide custom design latch up immune solutions. The latch up immunity is achieved by integrating an active Field Effect Transistor (FET) into the internal feedback node of the SCR. This provides access to ‘feedback’ node of the SCR allowing for latch-up free SCR design. The active FET times out in a short time period (e.g., microseconds) thus shutting off the SCR feedback mechanism making the SCR latch-up immune.

Abstract: An Electro-Static-Discharge (ESD) protection device has a Silicon-Controlled Rectifier (SCR) with a triggering PMOS transistor. The SCR is a PNPN structure with a P+ anode/source within a center N-well, a P-substrate, and an outer N-well that connects to a cathode using N+ well taps. The P+ anode/source is both the source of the triggering PMOS transistor and the anode of the SCR. A trigger circuit drives the gate of the triggering PMOS transistor low, turning it on to charge the P+ drain. Since the P+ drain straddles the well boundary, making physical contact with both the center N-well and the P-substrate, holes flow into the P-substrate. The P+ drain is located near guard rings that suppress latch-up. The holes from the P+ drain flood the region under the guard rings, temporarily weakening their effect and reducing the trigger voltage.

Abstract: In an ESD protection device, a first well of a first conductivity type and a second well of a second conductivity type are formed in a substrate to contact each other. A first impurity region of the first conductivity type and a second impurity region of the second conductivity type are formed in the first well, and are electrically connected to a first electrode pad. The second impurity region is spaced apart from the first impurity region in a direction of the second well. A third impurity region is formed in the second well, has the second conductivity type, and is electrically connected to a second electrode pad. A fourth impurity region is formed in the second well, is located in a direction of the first well from the third impurity region to contact the third impurity region, has the first conductivity type, and is electrically floated.

Abstract: An electro-static discharge (ESD) protection device includes a first PN diode, a second PN diode and a silicon controlled rectifier (SCR). The first PN diode and the second PN diode are coupled in series between a pad and a ground voltage to provide a first discharge current path. The SCR is coupled between the pad and the ground voltage to provide a second discharge current path. The SCR has a PNPN structure.

Abstract: The present application provides an electrostatic discharge protection circuit including a first N-type transistor, a second N-type transistor and a high-voltage tracing circuit. The high-voltage tracing circuit includes a first input terminal, a second input terminal and an output terminal. The first input terminal is coupled to the metal pad to receive a metal pad voltage. The second input terminal receives a supply voltage. The output terminal is coupled to the second N-type transistor and configured to output a high-voltage tracing voltage, wherein the high-voltage tracing voltage is larger than or equal to the metal pad voltage.

Abstract: A diode string having a plurality of diodes for ESD protection of a CMOS IC device comprises a first diode and a last diode in the diode string, wherein the first diode and the last diode are both formed on a bottom layer in a silicon substrate, and remaining diodes in the diode string. The remaining diodes are formed on a top layer placed on top of the bottom layer. The diode string further comprises a plurality of conductive lines that connect the first diode and the last diode on the bottom layer sequentially with the remaining diodes on the top layer to form a three dimensional (3D) structure of the diode string.

Abstract: III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple capacitors in an RFIC and/or PMIC. In embodiments, depletion mode III-N capacitors including a GaN layer in which a two dimensional electron gas (2DEG) is formed at threshold voltages below 0V are monolithically integrated with group IV transistor architectures, such as planar and non-planar silicon CMOS transistor technologies. In embodiments, silicon substrates are etched to provide a (111) epitaxial growth surface over which a GaN layer and III-N barrier layer are formed. In embodiments, a high-K dielectric layer is deposited, and capacitor terminal contacts are made to the 2DEG and over the dielectric layer.

Abstract: An integrated circuit may include a plurality of input/output (I/O) cells used for communicating signals, power, and ground to and from a core of the integrated circuit. The I/O cells may each include a bond pad formed in one or more top metal layers. One or more of the bond pads may be offset a predetermined distance from an I/O cell edge corresponding to a chip edge of the integrated circuit. A volume may be determined by the I/O cell edge and the predetermined distance and one or more rails may be disposed in the volume and in at least one metal layer common with at least one metal layer of the bond pad. The rails may be involved in the discharge of electrostatic discharge (ESD) current, and may reduce path resistance of the path used to discharge the ESD current.

Abstract: A stacked three dimensional semiconductor device includes multiple thin substrates stacked over one another and over a base substrate. The thin substrates may include a thickness of about 0.1 ?m. In some embodiments, a noise suppression tier is vertically interposed between active device tiers. In some embodiments, each tier includes active device portions and noise suppression portions and the tiers are arranged such that noise suppression portions are vertically interposed between active device portions. The noise suppression portions include decoupling capacitors in a power/ground mesh and alleviate vertical noise.

Abstract: A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the semiconductor layer extending in parallel to each other along a first direction parallel to the surface of the semiconductor layer, and forming a plurality of gate electrodes comprising longitudinal portions extending parallel to the semiconductor fins along the first direction.

Abstract: A method for forming MOS transistor includes providing a substrate including a semiconductor surface having a gate electrode on a gate dielectric thereon, dielectric spacers on sidewalls of the gate electrode, a source and drain in the semiconductor surface on opposing sides of the gate electrode, and a pre-metal dielectric (PMD) layer over the gate electrode and over the source and drain regions. Contact holes are formed through the PMD layer to form a contact to the gate electrode and contacts to the source and drain. A post contact etch dielectric layer is then deposited on the contacts to source and drain and on sidewalls of the PMD layer. The post contact etch dielectric layer is selectively removed from the contacts to leave a dielectric liner on sidewalls of the PMD layer. A metal silicide layer is formed on the contacts to the source and drain.

Abstract: A complementary metal-oxide semiconductor (CMOS) circuit and a method of fabricating the device are described. The circuit includes an n-channel field effect transistor (nFET), the nFET including a high-k dielectric layer on an interlayer. The CMOS circuit also includes a p-channel field effect transistor (pFET), the pFET including the high-k dielectric layer on the interlayer and additionally including an aluminum-based cap layer between the high-k dielectric layer and a pFET work function setting metal. Metal atoms from the cap layer do not intermix with the interlayer.