Abstract: Structures for metallization levels of integrated circuits and associated fabrication methods. A first metallization level with a metallization line is formed. A second metallization level is formed over the first metallization level, having two metallization lines and two conductive vias extending from the two metallization lines to the metallization line in the first metallization level. The first metallization line is separated into a first section and a second section disconnected from the first section, so that the first section is connected by one conductive via to one metallization line in the second metallization level, and the second section is connected by the other conductive via to the other metallization line in the second level.

Abstract: Methods for forming a spacer comprising depositing a film on the top, bottom and sidewalls of a feature and treating the film to change a property of the film on the top and bottom of the feature. Selectively dry etching the film from the top and bottom of the feature relative to the film on the sidewalls of the feature using a high intensity plasma.

Abstract: A tantalum compound, a method of forming a thin film, and a method of fabricating an integrated circuit device, the tantalum compound being represented by the following General Formula (I):

Abstract: A method of forming a dielectric layer includes forming a preliminary dielectric layer on a substrate using a silicon precursor and performing an energy treatment on the preliminary dielectric layer to form a dielectric layer. In the dielectric layer, a ratio of Si—CH3 bonding unit to Si—O bonding unit ranges from 0.5 to 5.

Abstract: A method of manufacturing a semiconductor device includes forming a seed layer on a substrate by alternately performing supplying a halogen-based first process gas to the substrate and supplying a non-halogen-based second process gas to the substrate, and forming a film on the seed layer by supplying a third process gas to the substrate. A pressure of a space where the substrate exists in the act of supplying the first process gas is set higher than a pressure of the space where the substrate exists in the act of supplying the second process gas.

Abstract: Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

Abstract: A technique includes forming a laminated film on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first film which contains at least a predetermined element and oxygen, and forming a second film which contains at least the predetermined element, oxygen and carbon. The first film and the second film are laminated to form the laminated film.

Abstract: There is provided a method of manufacturing a semiconductor device, including: transferring a substrate to a module having a first process chamber and a second process chamber; reading a recipe program depending on a type and a number of the substrate; and processing the substrate according to the recipe program, wherein in the act of processing the substrate, a first data indicating a state of the first process chamber and a second data indicating a state of the second process chamber are respectively detected, and a comparison between the first data and a previously-acquired first reference data and a comparison between the second data and a previously-acquired second reference data are displayed on a display screen.

Abstract: Facilitating throughput in nanoimprint lithography processes by using an imprint resist including fluorinated components and a substrate treated with a pretreatment composition to promote spreading of an imprint resist on the substrate. The interfacial surface energy between the pretreatment composition and air exceeds the interfacial surface energy between the imprint resist and air by at least 1 mN/m, and the contact angle of the imprint resist on the surface of the nanoimprint lithography template is less than 15°.

Abstract: A method of fabricating a ceramic substrate structure includes providing a ceramic substrate, encapsulating the ceramic substrate in a barrier layer, and forming a bonding layer coupled to the barrier layer. The method further includes removing a portion of the bonding layer to expose at least a portion of the barrier layer and define fill regions, and depositing a second bonding layer on the at least a portion of the exposed barrier layer and the fill regions.

Abstract: Systems and methods for growing high-quality CdTe-based materials at high growth rates are provided. According to an aspect of the invention, a method includes depositing a first CdTe-based layer on a CdTe-based template at a rate of greater than 1 ?m/min. Each of the first CdTe-based layer and the CdTe-based template has a single-crystal structure and/or a large-grain polycrystalline structure. The depositing is performed by physical vapor deposition.

Abstract: This invention is directed toward a method for manufacturing a semiconductor device with a heterostructure comprises covering a semiconductor structure with a seed layer structure; forming one or more separated circularly shaped openings in the seed layer structure to expose the semiconductor structure therein, and leave the seed layer structure outside the one or more separated circularly shaped openings; forming an insulator layer thereon; etching the obtained structure to (i) expose at least a portion of the seed layer structure, such that the exposed at least portion of the seed layer structure surrounds each of the one or more separated circularly shaped openings, and (ii) optionally expose the semiconductor structure, in the one or more separated circularly shaped openings; and epitaxially growing a semiconductor layer from the exposed at least portion of the seed layer structure, firstly mainly vertically and then into each of the one or more separated circularly shaped openings until the epitaxially g

Abstract: A method is disclosed to prepare a substrate for photolithography. The method includes forming an underlayer over a surface of the substrate; depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer. Also disclosed is a structure configured for photolithography. The structure includes a substrate; an underlayer over a surface of the substrate; an interface hardmask layer disposed on the underlayer; and a layer of EUV resist disposed on the interface hardmask layer. The interface hardmask layer contains material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer.

Abstract: A semiconductor device includes: a substrate having a cell region with a semiconductor element and an outer peripheral region; and a drift layer on the substrate. The semiconductor element includes a base region, a source region, a trench gate structure, a deep layer deeper than a gate trench, a source electrode, and a drain electrode. The outer peripheral region has a recess portion in which the drift layer are exposed, and a guard ring layer. The guard ring layer includes multiple guard ring trenches having a frame shape, surrounding the cell region and arranged on an exposed surface of the drift layer, and a first guard ring in the guard ring trenches. Each of the linear deep trenches has a width equal to a width of each of the linear guard ring trenches.

Abstract: The invention relates to a method for manufacture of an electrical contact on a structure (10) made of an anisotropic material NA which exhibits an anisotropic electrical conductivity, where the structure (10) exhibits an axial electrical conductivity along a first axis XX? of the structure (10) and an orthogonal conductivity along a direction YY? orthogonal to the first axis XX? of the structure (10), where the orthogonal conductivity is less than the axial conductivity, where the method comprises: a step for the formation of a conductive electrode (20), with an initial thickness Ei, comprising a species M, on a first surface (30) of the structure (10), where the first surface (30) is orthogonal to the orthogonal direction YY?; the method being characterized in that the step for the formation of the conductive electrode (20) is followed by a step for implantation of species X through the conductive electrode (20), into the structure (10).

Abstract: Embodiments are directed to a method of forming a feature of a semiconductor device. In one or more embodiments, the feature is a gate, and the method includes forming a substrate and forming a gate material extending over a major surface of the substrate. The method further includes forming a trench extending through the gate material and into the substrate in a first direction, wherein the trench further extends through the gate material and the substrate in a second direction. The method further includes filling the trench with a fill material and forming individual gates from the gate material, wherein the individual gates extend along a third direction.

Abstract: In some embodiments, an apparatus includes a first layer with a first surface and a second surface opposite to the first surface. The apparatus also includes a second layer having a third surface interfacing the second surface and a fourth surface opposite the third surface. The apparatus further includes a third layer having a fifth surface interfacing the fourth surface and a sixth surface opposite the fifth surface. The apparatus also includes a fourth layer having a seventh surface interfacing the sixth surface to form a heterojunction, which generates a two-dimensional electron gas channel formed in the fourth layer. Further, the apparatus includes a recess that extends from the first surface to the fifth surface.

Abstract: Various embodiments include apparatuses and electronic devices. One such apparatus can include a first dielectric material and a second dielectric material, and a conductive material between the first dielectric material and the second dielectric material. A charge storage element, such as a floating gate or charge trap, is located between the first dielectric material and the second dielectric material and adjacent to the conductive material. The charge storage element has a first surface and a second surface. The first and second surfaces are substantially separated from the first dielectric material and the second dielectric material, respectively, by a first gap and a second gap. In various embodiments, the gaps are air gaps. Additional apparatuses and methods are disclosed.

Abstract: As a first grinding step, a peripheral portion of a back surface of a wafer (1) is ground with a first grindstone (17) to form a fractured layer (19) in the peripheral portion. Subsequently, as a second grinding step, a central portion of the back surface of the wafer (1) is ground with the first grindstone (17) to form a recess (21) while the peripheral portion in which the fractured layer (19) is formed is left as a rib (20). Subsequently, as a third grinding step, a bottom surface of the recess (21) is ground with a second grindstone (22) of an abrasive grain size smaller than that of the first grindstone (17) to reduce a thickness of the wafer (1).

Abstract: A method of metal-assisted chemical etching comprises forming an array of discrete metal features on a surface of a semiconductor structure, where each discrete metal feature comprises a porous metal body with a plurality of pores extending therethrough and terminating at the surface of the semiconductor structure. The semiconductor structure is exposed to an etchant, and the discrete metal features sink into the semiconductor structure as metal-covered surface regions are etched. Simultaneously, uncovered surface regions are extruded through the pores to form anchoring structures for the discrete metal features. The anchoring structures inhibit detouring or delamination of the discrete metal features during etching. During continued exposure to the etchant, the anchoring structures are gradually removed, leaving an array of holes in the semiconductor structure.

Abstract: A method for forming a semiconductor device in a plasma processing chamber is provided. An atomic layer etch selectively etches SiO with respect to SiN and deposits a fluorinated polymer. The fluorinated polymer layer is stripped, comprising flowing a stripping gas comprising oxygen into the plasma processing chamber, forming a plasma from the stripping gas, and stopping the flow of the stripping gas. A SiN layer is selectively etched with respect to SiO and SiGe and Si.

Abstract: Embodiments herein describe techniques for forming a zinc oxide mask used when performing RIE. In one embodiment, the zinc oxide mask is near-amorphous which means the zinc oxide has a grain size that is less than 50 nanometers. In contrast, metal masks such as aluminum, chromium, and titanium have a less robustness to RIE process. When performing RIE, the edges of these RIE masks can form pits or holes which harm the features of the underlying substrate. However, a near-amorphous zinc oxide RIE mask is less susceptible to pitting, and thus, can improve the geometry of the etched features.

Abstract: A process for smoothing a silicon-on-insulator structure comprising the exposure of a surface of the structure to an inert or reducing gas flow and to a high temperature during a heat treatment includes performing a first heat treatment step at a first temperature and under a first gas flow defined by a first flow rate, and performing a second heat treatment step at a second temperature lower than the first temperature and under a second gas flow defined by a second flow rate lower than the first flow rate.

Abstract: In an embodiment, a method of planarizing a surface includes applying a first layer to a surface including a protruding region including at least one compound semiconductor and a stop layer on an upper surface such that the first layer covers the surface and the protruding region, removing a portion of the first layer above the protruding region and forming an indentation in the first layer above the protruding region, the protruding region remaining covered by material of the first layer, and progressively removing an outermost surface of the first layer to produce a planarized surface including the stop layer on the upper surface of the protruding region and an outer surface of the first layer.

Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.

Abstract: The embodiments herein generally deal with semiconductor processing methods and apparatus. More specifically, the embodiments relate to methods and apparatus for etching a semiconductor substrate. A partially fabricated semiconductor substrate is provided in a reaction chamber. The reaction chamber is divided into an upper sub-chamber and a lower sub-chamber by a grid assembly. Plasma is generated in the upper sub-chamber, and the substrate is positioned in the lower sub-chamber. The grid assembly includes at least two grids, each of which is negatively biased, and each of which includes perforations which allow certain species to pass through. The uppermost grid is negatively biased in order to repel electrons. The lowermost grid is biased further negative (compared to the uppermost grid) in order to accelerate positive ions from the upper to the lower sub-chamber. Etching gas is supplied directly to the lower sub-chamber.

Abstract: A method of forming patterns may use an organic reflection-preventing film including a polymer having an acid-liable group. A photoresist film is formed on the organic reflection-preventing film. A first area selected from the photoresist film is exposed to generate an acid in the first area. Hydrophilicity of a first surface of the organic reflection-preventing film facing the first area of the photoresist film may be increased. The photoresist film including the exposed first area is developed to remove a non-exposed area of the photoresist film. The organic reflection-preventing film and a target layer are anisotropically etched by using the first area of the photoresist film as an etch mask.

Abstract: A method for bonding wafers is provided. The method comprises the steps of providing a first wafer having an exposed first layer, the first layer comprising a first metal; and providing a second wafer having an exposed second layer, the second layer comprising a second metal, the first metal and the second metal capable of forming a eutectic mixture having a eutectic melting temperature. The method further comprises the steps of contacting the first layer with the second layer; and applying a predetermined pressure at a predetermined temperature to form a solid-state diffusion bond between the first layer and the second layer, wherein the predetermined temperature is below the eutectic melting temperature.

Abstract: A switching device and a power semiconductor module are configured with a substrate, a power semiconductor component arranged thereupon and with a load connection device. The substrate incorporates mutually electrically-insulated printed conductors and wherein the load connection device, preferably for an AC potential, comprises at least two partial connection devices, having mutually corresponding contact surfaces and being interconnected in an force-fitted or materially-bonded manner and, on the contact surfaces, an electrically conductive manner, wherein a first partial connection device has a first contact device, which is force-fitted or materially-bonded to the printed conductor of the substrate, and wherein a second partial connection device has a second contact device for the further, preferably external, connection of a load connection device.

Abstract: Disclosed is a substrate transporting device including a transport mechanism, a transport chamber, a first exhaust fan, and a controller. The transport mechanism is movable in parallel in a given direction. The transport chamber includes a first wall disposed on a first side of the given direction of the transport mechanism, and a plurality of transportation ports each used for moving the substrate between an exterior and an interior of the transport chamber. The first exhaust fan is disposed closer to the first wall than any of the transportation ports, and exhausts gas in the transport chamber outside the transport chamber. The controller performs control such that, when the transport mechanism moves toward the first wall in a first proximal area whose distance from the first wall is of a given value or less, an exhaust amount of the first exhaust fan is larger than that when the transport mechanism moves toward the first wall out of the first proximal area.

Abstract: After a development liquid on a substrate is washed away with a rinse liquid, the rotational speed of the substrate is reduced, so that a liquid layer of the rinse liquid is formed over a top surface of the substrate. Thereafter, the rotational speed of the substrate is increased. The increase in the rotational speed of the substrate causes a centrifugal force to be slightly greater than tension, thereby causing the liquid layer to be held on the substrate with the thickness thereof in its peripheral portion increased and the thickness thereof at the center thereof decreased. Then, gas is discharged toward the center of the liquid layer from a gas supply nozzle, so that a hole is formed at the center of the liquid layer. This causes tension that is balanced with a centrifugal force exerted on the peripheral portion of the liquid layer to disappear. Furthermore, the rotational speed of the substrate is further increased while the gas is discharged. Thus, the liquid layer moves outward from the substrate.

Abstract: A collector assembly for use with a spin chuck includes a base component, a top component and a first intermediate component configured to be fitted between the base component and the top component. The base, top and first intermediate components are configured so as to be interconnectable to form a process enclosure and so as to be separable from one another. The base component and the intermediate component each comprise collector wall segments such that when the base, top and first intermediate components are interfitted, the wall segments together define an outer side wall of the collector assembly.

Abstract: In one embodiment, a semiconductor manufacturing apparatus includes a support module configured to support a wafer having first and second faces. The apparatus further includes a chamber configured to contain the support module. The apparatus further includes a microwave generator configured to generate a microwave. The apparatus further includes a waveguide configured to emit the microwave into the chamber to irradiate the first or second face of the wafer with the microwave, the waveguide being provided to the chamber such that an incidence direction of the microwave emitted from the waveguide onto the first or second face is non-vertical to the first or second face.

Abstract: A system and method for a cluster tool apparatus for processing a semiconductor product including processing modules located adjacent each other and configured to process a semiconductor module, loadlocks configured to retain and dispense unprocessed semiconductor products and each positioned adjacent one of the processing modules, a robot configured to load, transfer and unload a semiconductor product to and from the processing modules, a hardware controller in communication with the robot and executing a method to close down the cluster tool apparatus to an idle state, the method including determining a status of the processing modules, determining if a close down process is required based on the status or based on a close down signal, and, if required, determining a schedule for a close down process based on a semiconductor product residency parameter, and controlling the operation of the robot based on the schedule to perform the close down process.

Abstract: A projecting/receiving unit (52) projects a laser light to a peripheral portion (30) and receives the reflected light while a liquid is being fed to a substrate (14) and is flowing on the peripheral portion (30). A signal processing controller (54) processes the electric signal of the reflected light to decide the state of the peripheral portion (30). The state of the peripheral portion being polished is monitored. Moreover, the polish end point is detected. A transmission wave other than the laser light may also be used. The peripheral portion (30) may also be enclosed by a passage forming member thereby to form a passage properly. The peripheral portion can be properly measured even in the situation where the liquid is flowing on the substrate peripheral portion.

Abstract: Apparatus for processing a substrate are provided herein. In some embodiments, a substrate support includes a body having a support surface; an RF electrode disposed in the body proximate the support surface to receive RF current from an RF source; a shaft to support the body; a conductive element having an interior volume and extending through the shaft, wherein the conductive element is coupled to the RF electrode; and an RF gasket; wherein the conductive element includes features that engage the RF gasket to return the RF current to ground.

Abstract: The invention relates generally to semiconductor fabrication technology and, more particularly, to chemical vapor deposition (CVD) processing and associated apparatus for addressing temperature non-uniformities on semiconductor wafer surfaces. Embodiments include a wafer carrier for use in a system for growing epitaxial layers on one or more wafers by CVD, the wafer carrier comprising a top plate and base plate which function coordinately to reduce temperature variability caused during CVD processing.

Abstract: The bottom plate has a plate-like shape, is arranged to face an outer face of a lower wall, and has a locking portion. The groove member has: a groove-forming portion having a groove opening downward formed therein, a surrounding wall portion, which is connected to the groove-forming portion, and is arranged around the groove-forming portion; and a locked portion, which is connected to the surrounding wall portion, is elastically deformable, and is locked by way of the locking portion of the bottom plate by being elastically deformed. The groove member is supported and fixed by way of the lower wall and the bottom plate.

Abstract: A connecting mechanism includes a mounting unit, a substrate transfer port, a door closing or opening the substrate transfer port, a coupling mechanism coupling a cover of the substrate container mounted on the mounting unit with the door, and a gas exhaust/purge unit. First, second and third seal members respectively seal a first space between a peripheral portion of the substrate transfer port and the door, a second space between the door and the cover of the substrate container, and a space between the peripheral portion of the substrate transfer port and the main body. The gas exhaust unit exhausts the first space and a second space. The purge gas, which has been supplied into the substrate container by the gas exhaust/purge unit, is supplied into the first and the second space by allowing the gas exhaust unit to exhaust the first and the second space.

Abstract: A robot system includes: a robotic hand configured to load and unload a workpiece into and from a cassette in which a plurality of workpieces are aligned in a first direction; a sensor configured to detect the workpiece; a transporter configured to change a relative position of the sensor with respect to the cassette in the first direction and in a second direction; and circuitry configured to: control the transporter to arrange the sensor at a first position; command the sensor to scan in the first direction, to acquire first mapping data; control the transporter to arrange the sensor at a second position by changing the relative position of the sensor in the second direction; command the sensor to scan in the first direction, to acquire second mapping data; and determine that one or more of the workpieces are inclined based on the first and second mapping data.

Abstract: A transfer apparatus including a frame, multiple arms connected to the frame, each arm having an end effector and an independent drive axis for extension and retraction of the respective arm with respect to other ones of the multiple arms, a linear rail defining a degree of freedom for the independent drive axis for extension and retraction of at least one arm, and a common drive axis shared by each arm and configured to pivot the multiple arms about a common pivot axis, wherein at least one of the multiple arms having another drive axis defining an independent degree of freedom with respect to other ones of the multiple arms.

Abstract: A device for determining alignment errors of structures which are present on, or which have been applied to a substrate, comprising a substrate holder for accommodating the substrate with the structures and detection means for detecting X-Y positions of first markings on the substrate and/or second markings on the structures by moving the substrate or the detection means in a first coordinate system, wherein in a second coordinate system which is independent of the first coordinate system X?-Y? structure positions for the structures are given whose respective distance from the X-Y positions of the first markings and/or second markings can be determined by the device.

Abstract: Substrate processing apparatus including a wafer transport apparatus with a transport arm including an end effector, an arm pose deterministic feature integral to the substrate transport apparatus and disposed so that a static detection sensor of the substrate processing apparatus detects at least one edge of the at least one arm pose deterministic feature on the fly with radial motion of the transport arm, and a controller configured so that detection of the edge effects a determination of a proportion factor identifying at least a thermal expansion variance of the transport arm on the fly and includes a kinematic effects resolver configured to determine, from the detection of the edge on the fly, a discrete relation between the determined proportion factor and each different discrete variance respective to each different link of the transport arm determining at least the thermal expansion variance of the transport arm on the fly.

Abstract: Apparatus and method for aligning a rotatable substrate to a support mechanism to write a feature to the substrate, and a substrate so configured. In some embodiments, the substrate has a circumferentially extending timing pattern with spaced apart first and second timing marks disposed on opposing sides of a center point of the timing pattern and an identification (ID) field that stores a unique identifier value associated with the substrate. Upon mounting of the substrate to a support mechanism that rotates the substrate about a central axis that is offset from the center point, a control circuit generates a compensation value to compensate for the offset using the first and second timing marks and outputs a process instruction to authorize processing of the substrate using the unique identifier value. In some cases, the unique identifier value is used as a lookup to a computerized database.

Abstract: In accordance with various embodiments of the disclosed subject matter, a shallow trench isolation structure and a fabricating method thereof are provided. The method for forming the shallow trench isolation structure may include: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming a first insulating layer on a surface of the semiconductor substrate and in the shallow trench, a portion of the first insulating layer in the shallow trench includes an opening; etching the first insulating layer to increase a width of the opening; after etching the first insulating layer, performing a plasma treatment to an exposed surface of the first insulating layer; after the plasma treatment, cleaning the surface of the first insulating layer; and after cleaning the surface of the first insulating layer, filling a second insulating layer into the shallow trench.

Abstract: A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first doped portion. The semiconductor device also includes a first fin partially embedded in the doped isolation structure, and a sidewall surface of the first fin is in direct contact with the first doped portion. The semiconductor device includes a second fin partially embedded in the doped isolation structure, and the doped isolation structure is between the first fin and the second fin, and a sidewall surface of the second fin is in direct contact with the second doped portion.

Abstract: A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a radio frequency power switch that has a root mean square breakdown voltage in a range from 80 V to 200 V resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 1012 Ohm-cm. Methods of manufacture for the semiconductor device include removing a wafer handle to expose a first surface of the buried oxide layer, disposing the interfacial adhesion layer onto the first surface of the buried oxide layer, and molding the polymer substrate onto the interfacial adhesion layer.

Abstract: A multilayer structure includes a first material layer, a second material layer, and a diffusion barrier layer. The second material layer is connected to the first material layer. The second material layer is spaced apart from the first material layer. The diffusion barrier layer is between the first material layer and the second material layer. The diffusion barrier layer may include a two-dimensional (2D) material. The 2D material may be a non-graphene-based material, such as a metal chalcogenide-based material having a 2D crystal structure. The first material layer may be a semiconductor or an insulator, and the second material layer may be a conductor. At least a part of the multilayer structure may constitute an interconnection for an electronic device.

Abstract: A method for manufacturing a semiconductor structure includes the following steps. At first, a titanium layer is formed on a preformed layer. Then, a first titanium nitride layer is formed on the titanium layer. A first plasma treatment is applied to the first titanium nitride layer such that the first titanium nitride layer has a first N/Ti ratio. A second titanium nitride layer is formed on the first titanium nitride layer. A second plasma treatment is applied to the second titanium nitride layer such that the second titanium nitride layer has a second N/Ti ratio larger than the first N/Ti ratio.

Abstract: Disclosed herein are a metal-graphene heterojunction metal interconnect, a method of forming the same, and a semiconductor device including the same. The method includes: a) forming a carbon source layer by depositing a carbon source on a top surface of a substrate; b) forming a metal catalyst layer by depositing a metal catalyst on the carbon source layer; and c) carrying out heat treatment on the substrate comprising the carbon source layer and the metal catalyst layer. The graphene can be formed by carrying out the heat treatment only once irrespectively of the number of substrates, and accordingly to the manufacturing time and manufacturing cost of the metal interconnect are reduced, and a damage to the metal interconnect by the heat treatment is not caused.