Abstract: The disclosure relates to systems and method for processing images. The method includes selecting a predetermined reference structure, the predetermined reference structure having a known feature size/shape. The method also includes obtaining a reference image of the predetermined reference structure, and capturing a calibration image of the predetermined reference structure using an observation device. The calibration image includes a plurality of features. Additionally, the method includes identifying at least one portion of the plurality of features of the calibration image that include a feature size/shape substantially similar to the known feature size and shape of the predetermined reference structure. Finally, the method includes combining the identified portion of the plurality of features of the calibration image to form a stacked feature image, and determining a point spread function (PSF) of the observation device by comparing the obtained reference image with the stacked feature image.

Abstract: Devices and methods for monitoring a discharge in a plasma process are provided. An example method includes detecting at least a first signal path of at least one plasma supply signal within at least a first time range within at least one period of the plasma supply signal, detecting at least a second signal path of the at least one plasma supply signal within at least a second time range which is at the point corresponding to the first time range in at least one other period of the plasma supply signal, and generating an identification signal if the second signal path deviates by at least a distance from the first signal path. The distance has a minimum time difference and a minimum signal amplitude difference. The method enables to identify arcs in a very reliable and very rapid manner.

Abstract: According to various embodiments, a socket arrangement for holding an end block on a process chamber may include the following: a first socket element with a first fastening arrangement for fastening the first socket element on a process chamber wall and with a second fastening arrangement; and a second socket element with a third fastening arrangement, for fastening the second socket element on the first socket element and with a fourth fastening arrangement for fastening an end block on the second socket element; wherein the second fastening arrangement of the first socket element and the third fastening arrangement of the second socket element may be formed for engaging in one another with play in such a way that the second socket element may be deflectable in relation to the first socket element.

Abstract: The present disclosure provides methods and systems for automated tuning of multimode inductively coupled plasma mass spectrometers (ICP-MS). In certain embodiments, a ‘single click’ optimization method is provided for a multi-mode ICP-MS system that automates tuning of the system in one or more modes selected from among the multiple modes, e.g., a vented cell mode, a reaction cell mode (e.g., dynamic reaction cell mode), and a collision cell mode (e.g., kinetic energy discrimination mode). Workflows and computational routines, including a dynamic range optimization technique, are presented that provide faster, more efficient, and more accurate tuning.

Abstract: A mass calibration kit and a calibration method for a low-mass area of a high-resolution mass spectrometer in negative ion mode. The mass calibration kit comprises semiconductor nanometer material suspension, a free fatty acid standard solution and a MALDI sample target cleaning liquid. The mass calibration method comprises: adjusting a voltage difference between a sample target of the mass spectrometer and a slit to be 20 V; dripping the semiconductor nanometer material suspension on the surface of the sample target till a solvent is completely volatilized and dried; dripping the free fatty acid standard solution on the surface of a semiconductor nanometer material till the solvent is completely volatilized and dried; and putting the sample target in the mass spectrometer for mass calibration, wherein calibration coefficients obtained after the instrument calibration can be used for correcting a sample mass spectrometric detection result.

Abstract: Methods, systems and devices that provide fluid devices with at least one SPE bed adjacent (upstream of) a separation channel which may be in communication with an inlet of a Mass Spectrometer. The fluid device can be configured to operate using independently applied pressures to a BGE reservoir and a sample reservoir for pressure-driven injection that can inject a discrete sample plug into a separation channel that does not require voltage applied to the sample reservoir and can allow for in-channel focusing methods to be used. The methods, systems and devices are particularly suitable for use with a mass spectrometer but optical or other electronic detectors may also be used with the fluidic devices.

Abstract: Semiconductor devices and a method for forming the same are provided. In various embodiments, a method for forming a semiconductor device includes receiving a semiconductor substrate including a channel. An atmosphere-modulation layer is formed over the channel. An annealing process is performed to form an interfacial layer between the channel and the atmosphere-modulation layer.

Abstract: A solution for fabricating a group III nitride heterostructure and/or a corresponding device is provided. The heterostructure can include a nucleation layer, which can be grown on a lattice mismatched substrate using a set of nucleation layer growth parameters. An aluminum nitride layer can be grown on the nucleation layer using a set of aluminum nitride layer growth parameters. The respective growth parameters can be configured to result in a target type and level of strain in the aluminum nitride layer that is conducive for growth of additional heterostructure layers resulting in strains and strain energies not exceeding threshold values which can cause relaxation and/or dislocation formation.

Abstract: A method for manufacturing a semi-conducting material including a layer of nitride of a group 13 element comprising active areas for manufacturing electronic components, and inactive areas, the active and inactive areas extending on a front face of the layer of nitride, the method comprising steps consisting of: using a mask comprising a plurality of apertures each defining an active area pattern on the initial substrate, growing the layer of nitride, receiving a theoretical pattern pitch corresponding to a desired distance between two adjacent active area patterns on the front face of the layer of nitride, calculating at least one mask pitch different from the theoretical pattern pitch for compensating shifts in the active area patterns, the mask pitch corresponding to a distance between two adjacent apertures of the protective mask.

Abstract: A vertical trench MOSFET comprising: a N-doped substrate of a III-N material; and an epitaxial layer of the III-N material grown on a top surface of the substrate, a N-doped drift region being formed in said epitaxial layer; a P-doped base layer of said III-N material, formed on top of at least a portion of the drift region; a N-doped source region of said III-N material; formed on at least a portion of the base layer; and a gate trench having at least one vertical wall extending along at least a portion of the source region and at least a portion of the base layer; wherein at least a portion of the P-doped base layer along the gate trench is a layer of said P-doped III-N material that additionally comprises a percentage of aluminum.

Abstract: A method for manufacturing a semiconductor device includes: forming a first patterned target layer on a substrate having a first region and a second region, the first patterned target layer having first openings along a first direction in the first region; forming a patterned hard mask layer over the first patterned target layer and having first recesses along a second direction in the first region and second recesses along the first direction in the second region; forming a patterned photoresist layer over the patterned hard mask layer and having stripe structures along the second direction in the first region and block structures along the first direction in the second region; and etching the patterned photoresist layer, patterned hard mask layer, and first patterned target layer to form a second patterned target layer.

Abstract: A method of treating a surface of a silicon substrate forms an accelerated gas cluster ion beam of carbon atoms, promotes fragmentation and/or dissociation of gas cluster ions in the beam, removes charged particles from the beam to form a neutral beam, and treats a portion of a surface of the silicon substrate by irradiating it with the neutral beam. A silicon substrate surface layer of SiCX (0.05<X<3) formed by accelerated and focused Neutral Beam irradiation of a silicon substrate wherein the Neutral Beam is derived from a gas cluster ion beam which has had its cluster ions dissociated and charged particles removed.

Abstract: Multigate devices and fabrication methods that mitigate the layout effects are described. In conventional processes to fabricate multigate semiconductor devices such as FinFET devices, long isolation cut masks may be used. This can lead to undesirable layout effects. To mitigate or eliminate the layout effect, fabrication methods are proposed in which the interlayer dielectric (ILD) layer remains intact at the gate cut location during the fabrication process.

Abstract: A metal film is deposited on a front surface of a semiconductor wafer of silicon. After the semiconductor wafer is received in a chamber, the pressure in the chamber is reduced to a pressure lower than atmospheric pressure. Thereafter, nitrogen gas is supplied into the chamber to return the pressure in the chamber to ordinary pressure, and the front surface of the semiconductor wafer is irradiated with a flash of light, so that a silicide that is a compound of the metal film and silicon is formed. The oxygen concentration in the chamber is significantly lowered during the formation of the silicide because the pressure in the chamber is reduced once to the pressure lower than atmospheric pressure and then returned to the ordinary pressure. This suppresses the increase in resistance of the silicide resulting from the entry of oxygen in the atmosphere in the chamber into defects near the interface between the metal film and a base material.

Abstract: A method for making a solar cell is disclosed. In accordance with the method of the present invention a composite wafer is formed. The composite layer includes a single crystal silicon wafer, a silicon-based device layer and sacrificial porous silicon sandwiched therebetween. The composite wafer is treated to an aqueous etchant maintained below ambient temperatures to selectively etch the sacrificial porous silicon and release or undercut the silicon-based layer from the single crystal silicon wafer. The released silicon device layer is attached to a substrate to make a solar cell and the released single crystal silicon wafer is reused to make additional silicon device layer.

Abstract: In an inductively-coupled plasma torch unit, a coil, a first ceramic block, and a second ceramic block are arranged parallel to one another, and an elongated chamber has an annular shape. Plasma generated inside the chamber is ejected toward a substrate through an opening portion in the chamber. The substrate is processed by relatively moving the elongated chamber and the substrate in a direction perpendicular to a longitudinal direction of the opening portion. A rotating ceramic pipe having a cylindrical shape is provided so as to cause a refrigerant to flow into a cavity formed inside the ceramic pipe. Accordingly, it becomes possible to apply greater high-frequency power, thereby enabling fast plasma processing.

Abstract: This method for manufacturing a niobate-system ferroelectric thin-film device includes: a lower electrode film formation step of forming a lower electrode film on a substrate; a ferroelectric thin film formation step of forming a niobate-system ferroelectric thin film on the lower electrode film; an etch mask pattern formation step of forming an etch mask in a desired pattern on the niobate-system ferroelectric thin film, the etch mask being an amorphous fluororesin film laminated via a noble metal film; and a ferroelectric thin film etching step of shaping the niobate-system ferroelectric thin film into a desired fine pattern by wet etching using an etchant comprising: a chelating agent; an aqueous alkaline solution containing an aqueous ammonia solution; and an aqueous hydrogen peroxide solution.

Abstract: A process for chemical mechanical polishing a substrate containing tungsten is disclosed to reduce corrosion rate and inhibit dishing of the tungsten and erosion of underlying dielectrics. The process includes providing a substrate; providing a polishing composition, containing, as initial components: water; an oxidizing agent; a polyglycol or polyglycol derivative; a dicarboxylic acid, a source of iron ions; a colloidal silica abrasive; and, optionally a pH adjusting agent; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein some of the tungsten (W) is polished away from the substrate, corrosion rate is reduced, dishing of the tungsten (W) is inhibited as well as erosion of dielectrics underlying the tungsten (W).

Abstract: An optical system that is able to reliably deliver a uniform amount of energy across an anneal region contained on a surface of a substrate. The optical system is adapted to deliver, or project, a uniform amount of energy having a desired two-dimensional shape on a desired region on the surface of the substrate. An energy source for the optical system is typically a plurality of lasers, which are combined to form the energy field.

Abstract: Many aspects of an improved IC package are disclosed herein. The improved IC package exhibits low-impedance and high power and signal integrity. The improved IC package comprises an IC die mounted on a multilayer coreless substrate. The thicknesses of prepreg layers of the coreless substrate are specific chosen to minimize warpage and to provide good mechanical performance. Each of the prepreg layers may have different coefficient of thermal expansion (CTE) and/or thickness to enable better control of the coreless substrate mechanical properties. The improved IC package also includes a vertically mounted die side capacitor and a conductive layer formed on the solder resist layer of the substrate. The conductive layer is formed such that it also encapsulates the vertically mounted capacitor while being electrically coupled to one of the capacitor's electrode.

Abstract: An insulating second element is provided and overlies a surface of a first element which consists essentially of a material having a CTE of less than 10 ppm/° C. and has a first thickness in a first direction normal to the surface. Openings extend in the first direction through the second element. The first element is abraded to produce a thinned first element having a second thickness less than the first thickness. Conductive elements are formed at a first side of the interposer coincident with or adjacent to a surface of the thinned first element remote from the second element. A conductive structure extends through the openings in the second element, wherein the conductive elements are electrically connected with terminals of the interposer through the conductive structure, and the terminals are disposed at a second side of the interposer opposite from the first side.

Abstract: Apparatus, methods, and computer programs for semiconductor processing in a capacitively-coupled plasma chamber are provided. A chamber includes a bottom radio frequency (RF) signal generator, a top RF signal generator, and an RF phase controller. The bottom RF signal generator is coupled to the bottom electrode in the chamber, and the top RF signal generator is coupled to the top electrode. Further, the bottom RF signal is set at a first phase, and the top RF signal is set at a second phase. The RF phase controller is operable to receive the bottom RF signal and operable to set the value of the second phase. Additionally, the RF phase controller is operable to track the first phase and the second phase to maintain a time difference between the maximum of the top RF signal and the minimum of the bottom RF signal at approximately a predetermined constant value, resulting in an increase of the negative ion flux to the surface of the wafer.

Abstract: A laser crystallization apparatus includes a laser generator that generates a laser beam including a plurality of line beams that are parallel to each other. An optical system includes a plurality of lenses and mirrors, wherein the optical system optically converts the generated laser beam to a converted laser beam. A chamber includes a stage and a substrate disposed on the stage, wherein a laser-crystallized thin film is formed on the substrate when the substrate is irradiated by the converted laser beam. A line focus adjuster that adjusts a line focus and a final focus of the plurality of line beams passing through the optical system, wherein the substrate is irradiated by the plurality of line beams at the final focus of the plurality of line beams.

Abstract: Provided is an indicator that can easily detect whether treatment with at least one member of plasma, ozone, ultraviolet rays, and radical-containing gas is uniformly performed on an entire substrate in an electronic device manufacturing apparatus; also provided is a method for designing and/or managing an electronic device manufacturing apparatus using the indicator. The indicator is used in an electronic device manufacturing apparatus, wherein (1) the indicator detects at least one member selected from the group consisting of plasma, ozone, ultraviolet rays, and radical-containing gas, (2) the indicator has a shape that is the same as that of a substrate used in the electronic device manufacturing apparatus, (3) the indicator contains a color-changing layer, and (4) the color-changing layer is formed by an ink composition whose color changes or disappears by reaction with at least one member selected from the group consisting of plasma, ozone, ultraviolet rays, and radical-containing gas.

Abstract: In some embodiments, the present disclosure relates to a method of bump metrology The method is performed by forming a through-substrate-via within a substrate, forming a plurality of metal interconnect layers within a dielectric structure over the substrate, and forming a bump on the plurality of metal interconnect layers. One or more substrate warpage parameters of the substrate are measured and an initial position of a lens within a substrate metrology module is calculated based upon the one or more substrate warpage parameters. The lens is then moved to the initial position, and a height and a width of the bump are measured using the substrate metrology module after moving the lens to the initial position.

Abstract: An apparatus including a stator configured to be stationarily connected to a housing; and a rotor configured to have a robot arm connected thereto. The rotor includes a shaft and an robot arm mount adjustably connected to the shaft. The stator and the rotor include mechanical reference locators to temporarily stationarily locate the robot arm mount to the stator for subsequently stationarily fixing the robot arm mount to the shaft.

Abstract: A substrate transport mechanism receives two substrates from an upstream ID section using two arms of three arms. The substrate transport mechanism delivers one of the two substrates to and from an individual processing unit of a processing block using one of arms holding the one of the two substrates to be subjected to a given process by the processing block and one of the arms holding no substrate. The substrate transport mechanism then keeps holding the other substrate with the remaining one arm of the arms having received the substrates while the processing unit processes the substrate. The substrate transport mechanism transfers the two substrates to a downstream processing block using the one arm holding the substrate subjected to the given process by the processing block and the one arm holding the other substrate.

Abstract: A substrate position alignment device includes a plurality of rotary tables which hold a plurality of substrates to be vertically spaced apart from each other, a rotation drive device which synchronously rotates the plurality of rotary tables, a plurality of support elements which support the substrate on the rotary table, support element drive members which independently and horizontally move the plurality of support elements between inward positions and outward positions, and up-down devices which move up and down the plurality of support element drive members. The substrate position alignment device operates the rotation drive device, the support element drive members and the up-down device based on the positions of notches of the substrate, to align the notches of the plurality of substrates with a reference rotational angle position.

Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

Abstract: Devices and methods of fabricating devices are provided. One method includes: obtaining an intermediate semiconductor device having a dielectric layer, an insulating layer, and a plurality of metal lines, including a liner material and a first metal material; recessing the metal material of each metal line forming a set of cavities; filling the cavities with a protective cap; etching the protective cap and the liner material in the set of cavities; depositing a plurality of dielectric caps in the set of cavities; depositing an interlayer dielectric layer over the insulating layer and the plurality of dielectric caps; patterning a via in the interlayer dielectric layer; and depositing a lining and a second metal material in the interconnect area; wherein the second metal material is electrically insulated from the first metal in at least one of the plurality of metal lines.

Abstract: The present disclosure belongs to the field of display and discloses an array substrate and a method for manufacturing the same, and a display apparatus. The array substrate comprises a first signal line and a second signal line provided side by side in a same direction and in a same layer, the second signal line comprising two separated parts, and a separation region being provided between the two separated parts; a first lead, configured to be connected to the first signal line, and pass through the separation region, so as to intersect with the second signal line; and a second lead, configured to be in a layer different than that of the second signal line, and conned the two separated parts.

Abstract: A semiconductor device has a carrier with a fixed size. A plurality of first semiconductor die is singulated from a first semiconductor wafer. The first semiconductor die are disposed over the carrier. The number of first semiconductor die on the carrier is independent from the size and number of first semiconductor die singulated from the first semiconductor wafer. An encapsulant is deposited over and around the first semiconductor die and carrier to form a reconstituted panel. An interconnect structure is formed over the reconstituted panel while leaving the encapsulant devoid of the interconnect structure. The reconstituted panel is singulated through the encapsulant. The first semiconductor die are removed from the carrier. A second semiconductor die with a size different from the size of the first semiconductor die is disposed over the carrier. The fixed size of the carrier is independent of a size of the second semiconductor die.

Abstract: A peeling method at low cost with high mass productivity is provided. An oxide layer is formed over a formation substrate, a first layer is formed over the oxide layer using a photosensitive material, an opening is formed in a portion of the first layer that overlaps with the oxide layer by a photolithography method and the first layer is heated to form a resin layer having an opening, a transistor including an oxide semiconductor in a channel formation region is formed over the resin layer, a conductive layer is formed to overlap with the opening of the resin layer and the oxide layer, the oxide layer is irradiated with light using a laser, and the transistor and the formation substrate are separated from each other.

Abstract: Semiconductor device structures with reduced gate end width formed at gate structures and methods for manufacturing the same are provided. In one example, a semiconductor device structure includes a plurality of gate structures formed over a plurality of fin structures, the gate structures formed substantially orthogonal to the fin structures, wherein the plurality of gate structures includes a first gate structure having a first gate end width and a second gate structure having a second gate end width, wherein the second gate end width is shorter than the first gate end width.

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions.

Abstract: Semiconductor devices may include a substrate including first to third regions, with first to third interfacial layers in the first to third regions, respectively, first to third high-k dielectric films on the first to third interfacial layers, respectively, first to third work function adjustment films on the first to third high-k dielectric films, respectively, and first to third filling films on the first to third work function adjustment films, respectively. Concentrations of a dipole forming element in the first to third high-k dielectric films may be first to third concentrations. The first concentration may be greater than the second concentration, and the second concentration may be greater than the third concentration. Thicknesses of the first to third work function adjustment films may be first to third thicknesses. The first thickness may be less than the second thickness, and the second thickness may be less than the third thickness.

Abstract: Fabricating of radio-frequency (RF) devices involves providing a field-effect transistor formed over an oxide layer formed on a semiconductor substrate and converting at least a portion of the semiconductor substrate to porous silicon.

Abstract: The present invention relates to a method for forming an electronic device intended to accommodate at least one fully depleted transistor of the FDSOI type and at least one partially depleted transistor of the PDSOI type, from a stack of layers (10) comprising at least one insulating layer (100) topped with at least one active layer (200) made of a semiconductor material, the method comprising at least one step of dry etching and one step of height adjustment between at least two etched elements.

Abstract: An electronic hardware assembly including at least a first and second laminar component, wherein the first laminar components includes a die, the die including a substrate, a functional region and a first protective layer, and the second laminar component includes a second protective layer, wherein the first and second laminar components are arranged in a stack such that the functional region of the first laminar component is arranged within the assembly substantially between first and second protective layers.

Abstract: Package substrate and a method of manufacturing the same is disclosed. The package substrate includes an insulating layer having first circuit patterns embedded in a first surface of the insulating layer, and a protruded circuit pattern formed above at least one of the embedded first circuit patterns, wherein a width of the protruded circuit pattern is greater than a width of each of the embedded first circuit patterns. Accordingly, a flip chip and a wire bonding chip may be installed at the same time owing to an embedded structure of circuit pattern and a protruded structure of circuit pattern realized together on a surface where an electronic component is to be installed. Moreover, a fine circuit pattern may be formed, and a surface treatment layer may be selectively formed at desired portions without forming an additional seed layer for electroplating, thereby possibly simplifying manufacturing processes and saving manufacturing costs.

Abstract: Embodiments of the present disclosure provide techniques and configurations for a computing system with a thermal interface having magnetic particles. In some embodiments, the computing system may include a first part, a second part, and a thermal interface to couple the first and second parts. The thermal interface may comprise a thermal interface material having magnetic particles that are aligned in a defined direction relative to a surface of the first or second part, to provide desired thermal conductivity between the first and second parts. The defined direction of alignment of magnetic particles may comprise an alignment of the particles substantially perpendicularly to the surface of the first or second part. Other embodiments may be described and/or claimed.

Abstract: A first surface of a heat source is spaced from a support by a first gap, in a thermal path from the first surface to the support. A second surface of the heat source, opposite to the first surface, is spaced by a second gap from a heat sink, in a thermal path from the second surface to the heat sink. The thermal path to the support provides a first thermal resistance, based on a gap spacing of the first gap and the thermal path to the heat sink provides a second thermal resistance, based on a gap spacing of the second gap.

Abstract: A lead frame for a packaged integrated circuit (IC) device has alternating first and second leads that protrude from a package body in respective first and second planes, where the second plane is parallel to and below the first plane. The first leads are formed into Gull Wing shaped leads and the second leads are formed into J-shaped leads. Inner lead portions of the first and second leads are maintained in the first plane with a tape. An inner lead portion of each of the second leads includes a deformation area that facilitates maintaining the tape in contact with the inner lead area of the second leads, even when a mold tool presses down on an outer lead side of the second leads to place the outer lead ends of the second leads in the second plane.

Abstract: A leadframe assembly includes a leadframe having a die attach pad and a first plurality of leads. A first generally sine wave-shaped wire having a first end and a second end has a first end of thereof attached to a first one of the first plurality of leads and the second end thereof attached to a second one of the first plurality of leads. A method of making a leadframe assembly includes forming an inductor on a leadframe by bending a first wire into a generally sine wave-shaped configuration and attaching the first wire to a first set of leads of the leadframe.

Abstract: A lead frame includes leads including inner leads and outer leads. Each of the leads includes an inner lead and an outer lead. A tie bar extends so as to cross connecting points of the inner leads and the outer leads. The leads and the tie bar include a first surface, a second surface, and side surfaces. A plating layer is provided on the inner leads, the outer leads and the tie bar. A first non-plating region is provided between an edge in the first surface of the inner lead and an edge of the plating layer provided on the first surface of the inner lead. A second non-plating region is provided between an edge of the first surface on the inner lead side of the tie bar and an edge on the inner lead side of the plating layer provided on the first surface of the tie bar.

Abstract: A package substrate includes a substrate, a first connection terminal mounted over the substrate, the first connection terminal including a first land and a second land on the substrate, a first solder resist surrounding the first land and the second land, and a first solder ball formed straddling the first land and the second land; and a second connection terminal which is mounted over the substrate and disposed adjacent to the first connection terminal, the second connection terminal including a third land and a fourth land on the substrate, a second solder resist surrounding the third land and the fourth land, and a second solder ball formed straddling the third land and the fourth land.

Abstract: A semiconductor substrate and a manufacturing method thereof are provided. The semiconductor substrate includes a dielectric layer, a circuit layer, a first protection layer and a plurality of conductive posts. The dielectric layer has a first surface and a second surface that are opposite to each other. The circuit layer is embedded in the dielectric layer and is exposed from the first surface. The first protection layer covers a portion of the first circuit layer and defines a plurality of holes that expose a remaining portion of the first circuit layer. The conductive posts are formed in the holes.

Abstract: A substrate and method of fabrication is disclosed. In one example, the substrate includes a first dielectric layer, a first and a second conductive trace arranged over the first dielectric layer and a second dielectric layer arranged between the first and second conductive traces and partially covering the first and second conductive traces, wherein an exposed part of the first and second conductive traces is exposed from the second dielectric layer at an interface and wherein a shape of the interface between the first and second conductive traces includes one or more of an angle, an edge, a curvature, a bulge, a step and an indentation.

Abstract: A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main surface of the semiconductor substrate; a first diffusion layer formed on the semiconductor substrate and provided to surround the first insulating film formed in a convex shape, the first diffusion layer being different in conductivity type from the semiconductor substrate; a first conductive layer formed so as to extend across the first insulating film formed in a convex shape, the first conductive layer forming a fuse element; and a second insulating film provided on the first conductive layer.