Abstract: Disclosed is a method of fabricating a semiconductor image sensor device. The method includes providing a substrate having a pixel region, a periphery region, and a bonding pad region. The substrate further has a first side and a second side opposite the first side. The pixel region contains radiation-sensing regions. The method further includes forming a bonding pad in the bonding pad region; and forming light-blocking structures over the second side of the substrate, at least in the pixel region, after the bonding pad has been formed.

Abstract: A CMOS image sensor includes a substrate and at least one device isolation region in the substrate and defining first and second pixel regions and first and second active portions in each of the first and second pixel regions. A reset and select transistor gates are disposed in the first pixel region, while a source follower transistor gate is disposed in the second pixel region, such that pixels in the first and second pixel regions share the reset, select and source follower transistors. A length of the source follower transistor gate may be greater than lengths of the reset and selection transistor gates.

Abstract: Among other things, a detection assembly of a radiation detector system is provided. In some embodiments, the detection assembly comprises a plurality of detector elements. Respective detector elements include a scintillator array, a photodetector array supporting the scintillator array on a first side of the photodetector array, and an electrical contact disposed on a second side of the photodetector array. In some embodiments, the detection assembly includes a printed circuit board. The electrical contact of respective detector elements is bonded to the printed circuit board to physically and electrically couple respective detector elements to the printed circuit board. A method of fabricating a detection assembly of a radiation detector system is also provided.

Abstract: The invention relates to a method for producing an optoelectronic semiconductor chip (1). A semiconductor layer sequence (3) is provided, comprising a first semiconductor layer (3a) and a second semiconductor layer (3b). Furthermore, a first contact layer (5a) is provided which extends laterally along the first semiconductor layer (3a) and electrically contacts same. A third semiconductor layer (7) is applied onto a first contact layer (5a) face facing away from the semiconductor layer sequence (3). A recess (8) is formed which extends through the third semiconductor layer (7), the first contact layer (5a), and the first semiconductor layer (3a) into the second semiconductor layer (3b). A passivation layer (9) is applied onto a third semiconductor layer (7) face facing away from the semiconductor layer sequence (3). At least one first (9a) and at least one second passage opening (9b, 9c) are formed in the passivation layer (9).

Abstract: A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area, the forming including: exposing the first area of the surface to light having a first wavelength while exposing the first area to a quantum dot forming environment that causes the quantum dots in the first area to form at a first growth rate while the quantum dots have a dimension less than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to the quantum dot forming environment that causes the quantum dots in the second area to form at a third growth rate while the quantum dots have a dimension less than a second threshold dimension; and processing the layer to form the LED device.

Abstract: A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.

Abstract: An optoelectronic device includes a first electrode and a second electrode facing each other a photoelectric conversion layer between the first electrode and the second electrode and a buffer layer between the photoelectric conversion layer and the second electrode. The buffer layer includes a nitride. The nitride includes one of silicon nitride (SiNx, 0<x<1), silicon oxynitride (SiOyNz, 0<y<0.5, 0<z<1), and a combination thereof.

Abstract: An organic light emitting device includes four sub-organic light emitting devices. The first device includes a first anode, a first common light emitting portion, and a first sub-light emitting portion. The second device includes a second anode, a second common light emitting portion, a first auxiliary layer, and a second sub-light emitting portion. The third device includes a third anode and a third common light emitting portion. The fourth device includes a fourth anode, a fourth common light emitting portion, and a light emitting layer emitting a first light. The first and second sub-light emitting portions have an integral structure and emit second light. The first, second, third, and fourth common light emitting portions have an integral structure and emit third light having a wavelength longer than a wavelength of at least one of the first or second lights.

Abstract: Discussed in an organic light emitting display device including a first pixel, and a second pixel being adjacent the first pixel, wherein each of the first pixel and the second pixel includes a plurality of subpixels, wherein the plurality of subpixels include a green subpixel, a red subpixel, and a blue subpixel, and wherein the red subpixel and the blue subpixel are shared by the first pixel and the second pixel.

Abstract: Disclosed are a display device and a method of manufacturing the same, which prevent a reduction in an aperture ratio and occurrence of color mixing caused by a process error of a black matrix and a color filter. The display device includes a plurality of color filters, an inorganic layer covering the plurality of color filters, and a black matrix disposed on the inorganic layer between the plurality of color filters.

Abstract: A micro LED display panel includes a plurality of active areas disposed on a substrate and arranged in an array. A plurality of micro LEDs are uniformly arranged in each of the active areas to achieve high-resolution of micro LED display panel. By controlling the number of micro LEDs in each of the active areas, the production cost can be effectively controlled, while a screen door effect can be eliminated to thereby enhance market competitiveness of the micro LED display panel.

Abstract: The present disclosure relates to a thin film transistor substrate having two different types of thin film transistors on the same substrate and a display using the same. A disclosed display device may include a substrate, a first thin film transistor including a first semiconductor layer having a polycrystalline semiconductor material on the substrate, and a second thin film transistor including a second semiconductor layer including an oxide semiconductor material on the substrate. Both the first semiconductor layer and the second semiconductor layer may be disposed directly on a same underlying layer.

Abstract: An organic light-emitting display apparatus includes a pixel electrode, a light emission layer over the pixel electrode, an opposite electrode covering the light emission layer, a plurality of upper layers over the opposite electrode, a light-shielding layer over the upper layers.

Abstract: A display may have an array of organic light-emitting diodes that form an active area on a flexible substrate. Metal traces may extend between the active area and an inactive area of the flexible substrate. Display driver circuitry such as a display driver integrated circuit may be coupled to the inactive area. The metal traces may extend across a bent region in the flexible substrate. A coating layer in the bent region may serve as a neutral stress plane adjustment layer. Metal traces may have meandering shapes such as zigzag shapes to reduce stress when bending. Adjacent traces may be shorted together to provide redundancy. Multiple layers of traces may be provided. Inorganic passivation layer coatings on the metal traces may help protect the metal traces.

Abstract: Disclosed is an AMOLED display panel structure, comprising a plurality of transversely scan lines which extend horizontally, a plurality of data lines which extend vertically and are insulated from the scan lines, switching lines of a same number of the scan lines which extend vertically, a plurality of row driving circuits coupled to the switching lines and a plurality of column driving circuits coupled to the data lines; one switching line is coupled to one scan line, one row driving circuit is coupled to a plurality of switching lines, one column driving circuits is coupled to a plurality of data lines; the row driving circuit and the column driving circuit are located in the lower border frame region; the left, right and upper frame regions are only used for package to achieve the ultra narrow border frames for all three sides of the AMOLED display panel.

Abstract: An object is to provide a display device with a high aperture ratio or a semiconductor device in which the area of an element is large. A channel formation region of a TFT with a multi-gate structure is provided under a wiring that is provided between adjacent pixel electrodes (or electrodes of an element). In addition, a channel width direction of each of a plurality of channel formation regions is parallel to a longitudinal direction of the pixel electrode. In addition, when a channel width is longer than a channel length, the area of the channel formation region can be increased.

Abstract: A display tile structure includes a tile layer with opposing emitter and backplane sides. A light emitter having first and second electrodes for conducting electrical current to cause the light emitter to emit light is disposed in the tile layer. First and second electrically conductive tile micro-wires and first and second conductive tile contact pads are electrically connected to the first and second tile micro-wires, respectively. The light emitter includes a plurality of semiconductor layers and the first and second electrodes are disposed on a common side of the semiconductor layers opposite the emitter side of the tile layer. The first and second tile micro-wires and first and second tile contact pads are disposed on the backplane side of the tile layer.

Abstract: Provided is a guard ring section to which a fine processing is easily applied. Provided is a semiconductor device comprising: a semiconductor substrate; an active region formed in the semiconductor substrate; and a guard ring section formed more outside than the active region in the semiconductor substrate, wherein the guard ring section includes: a guard ring formed in a circular pattern on an upper surface of the semiconductor substrate; an interlayer insulating film formed above the guard ring; a field plate formed in a circular pattern along the guard ring and above the interlayer insulating film; and a tungsten plug formed in a circular pattern along the guard ring and penetrating the interlayer insulating film to connect the guard ring and the field plate.

Abstract: A high power vertical insulated-gate switch is described that includes an active region, containing a cell array, and a surrounding termination region. The termination region is for at least the purpose of controlling a breakdown voltage and does not contain any switching cells. Assuming the anode is the silicon substrate (p-type), it is desirable to have good hole injection efficiency from the substrate in the active region in the device's on-state. Therefore, the substrate should be highly doped (p++) in the active region. It is desirable to have poor hole injection efficiency in the termination region so that there is a minimum concentration of holes in the termination region when the switch is turned off. Various doping techniques are disclosed that cause the substrate to efficiency inject holes into the active region but inefficiently inject holes into the termination region during the on-state.

Abstract: A method of manufacturing a semiconductor device is provided. A stacked structure including one or more sacrificial layers and one or more semiconductor layers are stacked on a substrate is formed. A dummy gate structure including a dummy gate and a dummy spacer on the stacked structure is formed. The stacked structure is etched using the dummy gate structure to form a first recess. The one or more sacrificial layers are etched. The dummy spacer is removed. A spacer film is formed on the dummy gate, the one or more semiconductor layer and the one or more sacrificial layers. The semiconductor layer and spacer film are etched to form a second recess using the dummy gate and spacer film. An external spacer formed on the dummy gate and an internal spacer formed on the one or more sacrificial layers are formed. A source/drain region is formed in the second recess.

Abstract: A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along an extension direction of the trench, the gate segments being connected to neighboring gate segments by means of connection elements. A distance between adjacent gate segments is equal to or smaller than 0.5*L, wherein L denotes a length of each of the gate segments, the length being measured along the extension direction of the trench.

Abstract: A junction field effect transistor includes a substrate and a gate region having a first conductive type in the substrate. Source/drain regions of a second conductive type opposite to the first conductive type are disposed in the substrate on opposite sides of the gate region. A pair of high-voltage well regions of the second conductive type are disposed beneath the source/drain regions. A channel region is provided beneath the gate region and between the pair of high-voltage well regions. The channel region is of the second conductive type and has a dopant concentration lower than that of the pair of high-voltage well regions.

Abstract: A power device having fast switching characteristic, while keeping EMI noise to a minimum and a method of fabricating the same are provided. The power device includes a first field stop layer having a first conductivity type, a first drift region formed on the first field stop layer and having a first conductivity type in an impurity concentration that is lower than the first field stop layer, a buried region formed on the first drift region and having the first conductivity type in an impurity concentration that is higher than the first drift region, a second drift region formed on the buried region, a power device cell formed at an upper portion of the second drift region, and a collector region formed below the first field stop layer.

Abstract: In a case where a semiconductor layer is epitaxially grown on a step shape formed due to CBL (current blocking layer) formation, the crystallinity of the semiconductor layer lowers. Also, a GaN layer that is epitaxially regrown on the CBL is not formed continuously by epitaxial growth, and therefore the crystallinity of the GaN layer lowers. A vertical semiconductor device manufacturing method is provided that comprises: a step of epitaxially growing a gallium nitride-based n-type semiconductor layer on a gallium nitride-based semiconductor substrate; a step of epitaxially growing a gallium nitride-based p-type semiconductor layer on the n-type semiconductor layer; and a step of ion-implanting p-type impurities to form a p+-type embedded region selectively in a predetermined depth range across the boundary between the n-type semiconductor layer and the p-type semiconductor layer.

Abstract: Provided is a semiconductor device according to an embodiment including an i-type or first-conductivity-type first diamond semiconductor layer having a first side surface, a second-conductivity-type second diamond semiconductor layer provided on the first diamond semiconductor layer and having a second side surface, a third diamond semiconductor layer being in contact with the first side surface and the second side surface, the third diamond semiconductor containing nitrogen, a first electrode electrically connected to the first diamond semiconductor layer, and a second electrode electrically connected to the second diamond semiconductor layer.

Abstract: A method for forming a graphene FET includes providing a graphene layer having a surface. A first metal layer having a work function <4.3 eV is deposited on the graphene surface. The first metal layer is oxidized to form a first metal oxide layer. The first metal oxide layer is etched to provide open surface contact regions including a first and a second region of the graphene layer for providing a graphene surface source and drain contact. A second metal layer is deposited including a second metal layer portion providing a source with a source contact over the graphene surface source contact and a second metal layer portion providing a drain with a drain contact over the graphene surface drain contact. A grown-in graphitic interface layer is formed at an interface between the source contact and graphene surface source contact and the drain contact and graphene surface drain contact.

Abstract: A silicon carbide single crystal includes: threading dislocations each of which having a dislocation line extending through a C-plane, and a Burgers vector including at least a component in a C-axis direction. In addition, a density of the threading dislocations having angles, each of which is formed by an orientation of the Burgers vector and an orientation of the dislocation line, larger than 0° and within 40° is set to 300 dislocations/cm2 or less. Furthermore, a density of the threading dislocations having the angles larger than 40° is set to 30 dislocations/cm2 or less.

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

Abstract: The present invention provides a semiconductor device comprising a substrate including an active region and an edge region and containing a semiconductor doped with impurities having a first conductivity type; an insulating film disposed on the edge region of the substrate; a field plate pattern disposed on the insulating film; and at least one first doped region having a second conductivity type buried in the edge region of the substrate and extending in a direction having a vector component parallel to an upper surface of the substrate.

Abstract: A NVM cell structure includes a semiconductor substrate having a first conductivity type, a first well region having a second conductivity type, a floating gate transistor and an erase gate region. The first well region is disposed on a first OD region of the semiconductor substrate. The erase gate region disposed on a second OD region of the semiconductor substrate includes a first doped region and at least one second doped region having the second conductivity type. The first doped region is disposed in semiconductor substrate and covers the second OD region, and the second doped region is disposed in the first doped region. The first doped region encompasses the second doped region, and a doping concentration of the second doped region is larger than a doping concentration of the first doped region.

Abstract: A microelectronic device includes an electrical conductor which includes a graphene heterolayer. The graphene heterolayer includes a plurality of alternating layers of graphene and barrier material. Each layer of the graphene has one to two atomic layers of graphene. Each layer of the barrier material has one to three layers of hexagonal boron nitride, cubic boron nitride, and/or aluminum nitride. The layers of graphene and the layers of barrier material may be continuous, or may be disposed in nanoparticles of a nanoparticle film.

Abstract: Structures for a field-effect transistor and fabrication methods for forming a structure for a field-effect transistor. The structure may include a gate electrode, a source/drain region formed adjacent to a vertical sidewall of the gate electrode, and a conductive link that couples the vertical sidewall of the gate electrode with the source/drain region.

Abstract: A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

Abstract: A vertical transistor device and a method for fabricating the same are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and fin portions located on the bottom portion. Each of the fin portions includes an upper portion and a lower portion. The lower portion is located between the bottom portion of the semiconductor substrate and the upper portion, in which the lower portion includes recesses. The first sources/drains are disposed on terminals of the upper portions of the fin portions. The second sources/drains are disposed on the recesses of the lower portions of the fin portions, in which the sources/drains are not merged with each other. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the recesses on the lower portions of the fin portions.

Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.

Abstract: The present disclosure relates to a field-effect transistor and a method of fabricating the same. A field-effect transistor includes a semiconductor substrate including a first semiconductor material having a first lattice constant, and a fin structure on the semiconductor substrate. The fin structure includes a second semiconductor material having a second lattice constant that is different from the first lattice constant. The fin structure further includes a lower portion that is elongated in a first direction, a plurality of upper portions protruding from the lower portion and elongated in a second direction that is different from the first direction, and a gate structure crossing the plurality of upper portions.

Abstract: A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.

Abstract: The invention relates to a thin-film transistor and a manufacturing method thereof. The manufacturing method of the thin-film transistor includes the following steps: an insulating layer is formed to cover a gate on a substrate; a semiconductor pattern having a first region and a second region is formed on the insulating layer; a plurality of island patterns is formed, wherein at least a portion of the plurality of island patterns is disposed on the semiconductor pattern, and the plurality of island patterns is separated from one another by a gap; and a source and a drain are formed to cover a portion of the plurality of island patterns and fill the gaps to respectively be electrically connected to the first region and the second region of the semiconductor pattern.

Abstract: A transistor including an oxide semiconductor layer can have stable electrical characteristics. In addition, a highly reliable semiconductor device including the transistor is provided. A semiconductor device includes a multi-layer film including an oxide layer and an oxide semiconductor layer, a gate insulating film in contact with the multi-layer film, and a gate electrode overlapping with the multi-layer film with the gate insulating film provided therebetween. In the semiconductor device, the oxide semiconductor layer contains indium, the oxide semiconductor layer is in contact with the oxide layer, and the oxide layer contains indium and has a larger energy gap than the oxide semiconductor layer.

Abstract: One of the objects is to improve display quality by reduction in malfunctions of a circuit. In a driver circuit formed using a plurality of pulse output circuits having first to third transistors and first to fourth signal lines, a first clock signal is supplied to the first signal line; a preceding stage signal is supplied to the second signal line; a second clock signal is supplied to the third signal line; an output signal is output from the fourth signal line. Duty ratios of the first clock signal and the second clock signal are different from each other. A period during which the second clock signal is changed from an L-level signal to an H-level signal after the first clock signal is changed from an H-level signal to an L-level signal is longer than a period during which the preceding stage signal is changed from an L-level signal to an H-level signal.

Abstract: A minute transistor is provided. A transistor with small parasitic capacitance is provided. A transistor with high frequency characteristics is provided. A semiconductor device including the transistor is provided. A semiconductor device includes an oxide semiconductor, a first conductor and a second insulator embedded in a first insulator, a second conductor and a third conductor. Edges of the second conductor and the third conductor facing each other each has a taper angle of 30 degree or more and 90 degree or less.

Abstract: An electronic device includes a drift region having a first conductivity type and a grid including a plurality of doped regions formed in the drift region and having a second conductivity type. The doped regions have a dopant concentration greater than 2.2×1019 cm?3. Related methods are also disclosed.

Abstract: Certain aspects of the present disclosure provide a semiconductor variable capacitor. The semiconductor variable capacitor generally includes a first non-insulative region disposed above a semiconductor region, and a second non-insulative region disposed adjacent to the semiconductor region. In certain aspects, the semiconductor variable capacitor also includes a first silicide layer disposed above the second non-insulative region, wherein the first silicide layer overlaps at least a portion of the semiconductor region. In certain aspects, a control region may be disposed adjacent to the semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.

Abstract: Discussed is a solar cell includes a semiconductor substrate, a conductive type region including a first conductive type region and a second conductive type region formed on one surface of the semiconductor substrate, an electrode including a first electrode and a second electrode, wherein the first electrode is connected to the first conductive type region and the second electrode is connected to the second conductive type region, and a passivation layer formed on the conductive type region. The passivation layer includes at least one of silicon nitride and silicon carbide.

Abstract: Fabrication methods and structures relating to backplanes for back contact solar cells that provide for solar cell substrate reinforcement and electrical interconnects are described. The method comprises depositing an interdigitated pattern of base electrodes and emitter electrodes on a backside surface of a semiconductor substrate, forming electrically conductive emitter plugs and base plugs on the interdigitated pattern, and attaching a backplane having a second interdigitated pattern of base electrodes and emitter electrodes at the conductive emitter and base plugs to form electrical interconnects.

Abstract: One embodiment of the present invention can provide a system for fabrication of a photovoltaic structure. The system can include a physical vapor deposition tool configured to sequentially deposit a transparent conductive oxide layer and a metallic layer on an emitter layer formed in a first surface of a Si substrate, without requiring the Si substrate to be removed from the physical vapor deposition tool after depositing the transparent conductive oxide layer. The system can further include an electroplating tool configured to plate a metallic grid on the metallic layer and a thermal annealing tool configured to anneal the transparent conductive oxide layer.

Abstract: A Laser Power Converter (LPC) device (1) comprises an anti-reflection coating (10), a window layer (20), an active region (30), an electron blocking layer (40), a Distributed Bragg Reflector (DBR) (50) and a substrate (60). The device further comprises an anode (70), a cathode (80) and insulating layers (90). The active region (30) is formed of indium gallium arsenide phosphide (InGaAsP), with the proportion of chemical elements in the InGaAsP layers being InyGa1-yAsxP1-x, and is designed to convert electromagnetic radiation having a wavelength of 1.55 ?m into electrical energy. However, the exact composition of the InGaAsP is chosen to have a band-gap wavelength at slightly above 1.55 ?m because in operation the device heats up and the band-gap shifts to longer wavelengths. To obtain a suitable band-gap the composition may be InyGa1-yAsxP1-x, where x=0.948, 0.957, 0.965, 0.968, 0.972 or 0.976 and y=0.557, 0.553, 0.549, 0.547, 0.545 or 0.544 respectively.

Abstract: The present disclosure provides a composite material of a pre-formed crystalline or polycrystalline semiconductor particles embedded in a crystalline or polycrystalline perovskite matrix material. The pre-formed crystalline or polycrystalline semiconductor particles and and crystalline or polycrystalline perovskite being selected so that any lattice mismatch between the two lattices does not exceed about 10%. The pre-formed crystalline or polycrystalline semiconductor particles and said crystalline or polycrystalline perovskite matrix material have lattice planes that are substantially aligned.

Abstract: A photoelectric conversion element includes a buffer layer, a BSF layer, a base layer, a photoelectric conversion layer, an emitter layer, a window layer, a contact layer, and a p-type electrode sequentially on one surface of a substrate, and includes an n-type electrode on the other surface of the substrate. The photoelectric conversion layer has at least one quantum dot layer. The at least one quantum dot layer includes a quantum dot and a barrier layer. A photoelectric conversion member including the buffer layer, the BSF layer, the base layer, the photoelectric conversion layer, the emitter layer, the window layer, and the contact layer has an edge of incidence that receives light in an oblique direction relative to the growth direction of the quantum dot. A concentrator concentrates sunlight and causes the concentrated sunlight to enter the photoelectric conversion member from the edge of incidence.

Abstract: An aspect of the invention provides a solar cell that comprises a semiconductor substrate having a light-receiving surface and a rear surface; a first semiconductor layer having a first conductivity type; a second semiconductor layer having a second conductivity type, the first semiconductor layer and the second semiconductor layer being formed on the rear surface, and a trench formed in the rear surface, wherein the first semiconductor layer is formed on the rear surface in which the trench is not formed, and the second semiconductor layer is formed on a side surface of the trench in an arrangement direction in which the first semiconductor layer and the second semiconductor layer are alternately arranged and on a bottom surface of the trench.