Abstract: A through via structure includes a conductive wiring, at least one dielectric layer over the conductive wiring, a via hole in the at least one dielectric layer and exposing the conductive wiring, and a conductive via in the via hole. The conductive via includes a conductive barrier layer in a bottom portion of the via hole, and a conductive layer in a top portion of the via hole.

Abstract: A three-dimensional memory device includes an alternating stack of L-shaped insulating layers and L-shaped electrically conductive layers located over a top surface of a substrate, such that each of the L-shaped insulating layers and the L-shaped electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion, memory stack structures extending through a memory array region of the alternating stack that includes the horizontally-extending portions of the L-shaped electrically conductive layers, such that each of the memory stack structures includes a memory film and a vertical semiconductor channel, dielectric spacers non-horizontally extending between neighboring pairs of a non-horizontally-extending portion of an L-shaped insulating layer and a non-horizontally-extending portion of an L-shaped electrically conductive layer, and contact via structures that contact a respective one of the non-horizontally-extending portions of the L-shaped

Abstract: Among other things, one or more support structures and techniques for forming such support structures within semiconductor devices are provided. The support structure comprises an oxide infused silicon layer that is formed within a trench of a dielectric layer on a substrate of a semiconductor device. The oxide infused silicon layer results from a silicon layer that is exposed to oxide during an ultraviolet (UV) curing process. The oxide infused silicon layer is configured to support a barrier layer against a conductive structure formed on the barrier layer within the trench. In this way, the support structure provides pressure against the barrier layer so that the barrier layer substantially maintains contact with the conductive structure, to promote improved performance and reliability of the conductive structure.

Abstract: An electronic device includes a semiconductor memory, wherein the semiconductor memory may include: a cell mat disposed over a substrate, the cell mat including a plurality of memory cells; an insulating layer disposed over the cell mat; a conductive pattern disposed over the insulating layer, the conductive pattern overlapping a first portion of the cell mat without overlapping a second portion of the cell mat; and a shielding layer disposed in the insulating layer, the shielding layer overlapping at least the second portion of the cell mat, the shielding layer being capable of blocking plasma.

Abstract: A power module includes a power semiconductor element, an interconnection material, a circuit board, an external terminal, a joining material, and a sealing resin. A clearance portion is continuously formed between the sealing resin and each of an end surface of the joining material and a surface of the interconnection material so as to extend from the end surface of the joining material to the surface of the interconnection material, the end surface of the joining material being located between the power semiconductor element and the interconnection material, the surface of the interconnection material being located between the end surface and a predetermined position of the interconnection material separated by a distance from the end surface.

Abstract: The present technology relates to a camera module capable of reducing the number of steps in the manufacturing process and reducing a black spot failure, a method for manufacturing the camera module, an imaging apparatus, and an electronic instrument. A frame and the rigid flexible substrate are adhered to each other by adhesive formed of thermosetting resin applied on an abutment surface excluding a portion of a range including a bonding section with the FPC drawer unit, thereby forming a vent hole in a site where adhesive has not been applied. At this time, the air of the space between the frame and the rigid flexible substrate is expanded by the heat and discharged from the vent hole.

Abstract: A method of making a microelectronic package includes bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier. The conductive structure may be a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier. The plurality of interconnections may have free ends that overlie the carrier. The microelectronic element may be positioned between at least two adjacent interconnections of the plurality of interconnections. The plurality of interconnections and the microelectronic element may be encapsulated with an encapsulant. The carrier may be removed to expose the free ends of the interconnections and bond pads of the microelectronic element. The free ends of the interconnections and the bond pads of the microelectronic element may be conductively connected with the terminals of the microelectronic package.

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

Abstract: A semiconductor structure including an insulating encapsulant, a first semiconductor die, a second semiconductor die and a redistribution circuit layer is provided. The first and the second semiconductor dies embedded in the insulating encapsulant and separated from one another. The first semiconductor die includes a first active surface accessibly exposed and a first conductive terminal distributed at the first active surface. The second semiconductor die includes a second active surface accessibly exposed and a second conductive terminal distributed at the second active surface. The redistribution circuit layer including a conductive trace is disposed on the first and the second active surfaces and the insulating encapsulant. The conductive trace is electrically connected from the first semiconductor die and meanderingly extends to the second semiconductor die, and a ratio of a total length of the conductive trace to the top width of the insulating encapsulant ranges from about 3 to about 10.

Abstract: A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in a peripheral portion covered with a protective film. On the other hand, a thickness of a wiring formed in the same step as the pad is larger than that of the pad in the wire bonding portion. The main conductive film of the pad in the wire bonding portion is comprised of only one layer of a first aluminum film, while the main conductive film of the wiring is comprised of at least two layers of aluminum films (the first aluminum film and a second aluminum film) in any region of the wiring.

Abstract: A mounting apparatus includes: a mounting tool; a supporting mechanism; a first pressurizing mechanism having a Z axis motor as a drive source for moving the mounting tool in the vertical direction together with the supporting mechanism so as to apply a first load to the electronic component; a second pressurizing mechanism having a VCM as a drive source provided between the supporting mechanism and the mounting tool, and for moving the mounting tool in the vertical direction with respect to the supporting mechanism so as to apply a second load to the electronic component; a load cell; and a control unit configured to control driving of the first pressurizing mechanism and the second pressurizing mechanism, the control unit previously driving the second pressurizing mechanism to bring the load cell into contact with the supporting mechanism and generate precompression when the first load is applied by the first pressurizing mechanism.

Abstract: A method for manufacturing a light-emitting device includes: a first connecting step of forming a ball portion of the wire joined to a first connecting point on a light emitting element; a first transferring step of transferring the capillary to a first point located in a +Z direction above the first connecting point; a second transferring step of transferring the capillary from the first point to a second point located in a ?X direction opposite from a second connecting point on the substrate; a third transferring step of transferring the capillary from the second point to a third point located in a +X direction beyond the second connecting point and in the +Z direction above the second connecting point; a second connecting step of transferring the capillary and joining the wire to the second connecting point; and forming an encapsulating member to encapsulate the wire.

Abstract: A package packaged with a cap. The package features trenches, through holes, and a non-conductive coupling element forming a locking mechanism integrated embedded or integrated within a substrate. The package has a cap coupled to the non-conductive coupling element through ultrasonic plastic welding. The package protects the dice from an outside environment or external stresses or both. A method is desired to form package to reduce glue overflow defects in the package. Fabrication of the package comprises drilling holes in a substrate; forming trenches in the substrate; forming a non-conductive coupling element in the through holes and the trenches to form a locking mechanism; allowing the non-conductive coupling element to harden and cure; coupling a die or dice to the substrate; and coupling a cap to the non-conductive coupling element to protect the die or dice from an outside environment or external stresses or both.

Abstract: In a stack of chips which each include active circuit regions, a plurality of through-silicon via (TSV) structures are formed for thermally conducting heat from the multi-chip stack by patterning, etching and filling with thermally conductive material a plurality of TSV openings in the multi-chip stack, including a first larger TSV opening that extends through substantially the entirety of the multi-chip stack without penetrating any active circuit region, and a second smaller TSV opening that extends down to but not through an active circuit region.

Abstract: Package on package structures and methods of manufacture are described. In various embodiments, DRAM die are integrated into various locations within a package on package structure, including within a bottom logic die package, as a co-package with a top NAND die package, and as a hybrid package structure between a top NAND die package and a bottom logic die package.

Abstract: A multi-package integrated circuit assembly can include a first electronic package having a first package substrate including a first die side and a first interface side. A first die can be electrically coupled to the first die side. A second electronic package can include a second package substrate having a second die side and a second interface side. A second die can be electrically coupled to the second die side. A conductive interconnect can be electrically coupled from the interface side of the first package substrate to the interface side of the second package substrate. A collective substrate can be attached to the first electronic package. For instance, the collective substrate can be located on a face of the first electronic package opposing the first package substrate. The collective substrate is electrically coupled to the first die and the second die through the first package substrate.

Abstract: Apparatuses and methods relating generally to a microelectronic package for wafer-level chip scale packaging with fan-out are disclosed. In an apparatus, there is a substrate having an upper surface and a lower surface opposite the upper surface. A microelectronic device is coupled to the upper surface with the microelectronic device in a face-up orientation. Wire bond wires are coupled to and extending away from the upper surface. Posts of the microelectronic device extend away from a front face thereof. Conductive pads are formed in the substrate associated with the wire bond wires for electrical conductivity.

Abstract: An electronic package is provided, including: a substrate having opposite first and second surfaces; at least a first electronic element disposed on the first surface of the substrate; a first encapsulant encapsulating the first electronic element; at least a second electronic element and a frame disposed on the second surface of the substrate; and a second encapsulant encapsulating the second electronic element. By disposing the first and second electronic elements on the first and second surfaces of the substrate, respectively, the invention allows a required number of electronic elements to be mounted on the substrate without the need to increase the surface area of the substrate. Since the volume of the electronic package does not increase, the electronic package meets the miniaturization requirement. The present invention further provides a method for fabricating the electronic package.

Abstract: A method of manufacturing a light-emitting device incudes providing a supporting member having a recess; disposing a light-emitting element at a bottom surface of the recess; disposing a first light-reflecting resin at the bottom surface of the recess; disposing a second light-reflecting resin in the recess, a viscosity of the second light-reflecting resin being higher than a viscosity of the first light-reflecting resin; and curing the first light-reflecting resin and the second light-reflecting resin to form a light-reflecting wall.

Abstract: A method for manufacturing a semiconductor device includes laminating a plurality of semiconductor wafers via an adhesive, heating such that the adhesive reaches a specific viscosity, and pressing the semiconductor wafers under a provisional pressure bonding load such that a gap between solder of through-electrodes provided to chip parts and through-electrodes of an adjacent semiconductor wafer falls within a specific range that is greater than zero, to produce a provisional pressure-bonded laminate; cutting the provisional pressure-bonded laminate with a cutter to produce a provisional pressure-bonded laminate chip part; and heating the provisional pressure-bonded laminate chip part to at least curing temperature of the adhesive and at least melting point of the solder, and pressing the provisional pressure-bonded laminate chip part under a main pressure bonding load to produce a main pressure-bonded laminate chip part such that the solder comes into contact with the through-electrodes of adjacent chip parts

Abstract: A capacitor includes a body including a substrate having first and second capacitor regions, and first to third terminal electrodes disposed on an external surface of the body. The first capacitor region includes a plurality of first trenches, and a first capacitor layer disposed on one surface of the substrate and in the first trenches in the first capacitor region and including at least one first dielectric layer and first and second electrodes disposed with the at least one first dielectric layer interposed therebetween. The second capacitor region includes a plurality of second trenches, and a second capacitor layer disposed on one surface of the substrate and the second trenches in the second capacitor region and including at least one second dielectric layer and third and fourth electrodes disposed with the at least one second dielectric layer interposed therebetween. The second capacitor layer has a specific surface area greater than that of the first capacitor layer.

Abstract: To prevent an electrostatic damage on a display device formed with a driving circuit. Protective circuits are provided not only at input terminal parts, but also at intermediate parts of a circuit or at the ends of wiring lines. Otherwise, the protective circuits are provided at the ends of the wiring lines and at the places immediately before and after the input terminals, respectively, and then the circuit is interposed therebetween. Further, the protective circuits are provided around a circuit with a large current consumption.

Abstract: An integrated circuit having a CML driver including a driver biasing network. A first output pad and a second output pad are connected to a voltage pad. A first driver is connected to the first output pad and the voltage pad. A second driver is connected to the second output pad and the voltage pad. A first ESD circuit is connected to the voltage pad, the first output pad, and the first driver. A second ESD circuit is connected to the voltage pad, the second output pad, and the second driver. The first ESD circuit biases the first driver toward a voltage of the voltage pad when an ESD event occurs at the first output pad, and the second ESD circuit biases the second driver toward the voltage of the voltage pad when an ESD event occurs at the second output pad.

Abstract: Disclosed is an electrostatic discharge (ESD) protection circuit. The ESD protection circuit may include a silicon controller rectifier (SCR) which may be triggered via at least one of its first trigger gate or second trigger gate. The ESD protection circuit may further include a highly doped region coupled to either the anode or cathode of the SCR, wherein the highly doped region may provide additional carriers to facilitate triggering of the SCR during an ESD event, whereby the SCR may be triggered more quickly.

Abstract: Embodiments of the invention provide an array substrate, a display device and a manufacturing method of the array substrate. The array substrate comprises a substrate (10) and a plurality of electrostatic discharge short-circuit rings (20) provided on the substrate. Each of the electrostatic discharge short-circuit rings (20) comprises a gate electrode (22), a gate insulating layer (26), an active layer (21), a source electrode (23), a drain electrode (24) and a passivation layer (30). Each of the electrostatic discharge short-circuit ring (20) further comprises a transparent conductive layer (25) for connecting the gate electrode (22) and the drain electrode (24), and the transparent conductive layer (25) is provided below the passivation layer (30).

Abstract: An ESD protection apparatus includes a semiconductor substrate, a first gate structure, a first doping region, a second doping region and a third doping region. The semiconductor substrate has a doping well with a first conductivity one end of which is grounded. The first gate structure is disposed on the doping well. The first doping region having a second conductivity, is disposed in the doping well and adjacent to the first gate structure, and is electrically connected to a pad. The second doping region having the second conductivity is disposed in the doping well and adjacent to the first gate structure. The third doping region having the first conductivity is disposed in the doping well and forms a P/N junction interface with the second doping region, wherein the second doping region and the third doping region respectively have a doping concentration substantially greater than that of the doping well.

Abstract: A display panel is disclosed, which includes: a substrate; plural scan lines disposed on the substrate and extending along a first direction; a first insulating layer disposed on the scan lines; plural data lines disposed on the first insulating layer and extending along a second direction; a second insulating layer disposed on the data lines; and a common electrode disposed on the second insulating layer and including a through hole; wherein, the through hole includes a first region and a second region, the first region has a first maximum width along the first direction, the second region has a second maximum width along the first direction, and a ratio of the second maximum width over the first maximum width is greater than 0 and less than 1.

Abstract: An asymmetric transistor may be used for controlling a memory cell. The asymmetric transistor may include at least one gate stack having bottom to top: a gate dielectric layer having a planar upper surface and a uniform thickness extending atop the entirety of the device channel, a dielectric threshold voltage adjusting element including: a sloped dielectric element located on the planar upper surface of the gate dielectric layer, and a sidewall dielectric layer extending from the sloped dielectric element along a first sidewall of the opening space, and a gate conductor located atop an upper surface of the sloped dielectric element and along a side of the sidewall dielectric layer. The dielectric threshold voltage adjusting element creates a threshold voltage that is lower in a writing mode than in a storage mode of the memory cell.

Abstract: Disclosed herein is a semiconductor integrated circuit device including a standard cell with a fin extending in a first direction. The fin and a gate line extending in a second direction perpendicular to the first direction and provided on the fin constitute an active transistor. The fin and a dummy gate line provided in parallel with the gate line constitute a dummy transistor. The active transistor shares a node as its source or drain with the dummy transistor.

Abstract: A semiconductor structure is disclosed that includes a p-channel metal-oxide semiconductor (PMOS) array having a first set of oxide diffusion layer (OD) structures, an n-channel metal-oxide semiconductor (NMOS) array having a second set of OD structures, and a dummy buffer zone surrounding the PMOS and NMOS arrays. The semiconductor structure has a uniform spacing between OD structures in the first and second sets of OD structures and between the PMOS and NMOS array, such that no dummy buffer zone is included between the PMOS array and the NMOS array.

Abstract: Semiconductor memory cells, array and methods of operating are disclosed. In one instance, a memory cell includes a bi-stable floating body transistor and an access device; wherein the bi-stable floating body transistor and the access device are electrically connected in series.

Abstract: The present disclosure provides a memory cell. The memory cell includes a substrate, a deep trench capacitor formed in the substrate, and a vertical transistor formed on the substrate and electrically connected to the deep trench capacitor. The vertical transistor includes a source region and a drain region stacked on the substrate, a channel region vertically sandwiched between the source region and the drain region, and a gate structure annularly wrapping around the channel region.

Abstract: A semiconductor device includes a substrate, plural active areas, plural bit lines and plural dummy bit lines. The substrate includes a cell region and a periphery region, and the active areas are defined on the substrate. The bit lines are disposed on the substrate, within the cell region and across the active areas. The dummy bit lines are disposed at a side of the bit lines, wherein the dummy bit lines are in contact with each other and have different pitches therebetween.

Abstract: An integrated circuit with a SAR SRAM cell with power routed in metal-1. An integrated circuit with a SAR SRAM cell that has power routed in Metal-1 and has metal-1 and metal-2 integrated circuit and SAR SRAM cell patterns which are DPT compatible. A process of forming an integrated circuit with a SAR SRAM cell with DPT compatible integrated circuit and SAR SRAM cell metal-1 and metal-2 patterns.

Abstract: A three-dimensional non-volatile memory including a substrate, a stacked structure and a channel layer. The stacked structure is disposed on the substrate and includes first dielectric layers, gates and charge storage structures. The first dielectric layers and the gates are alternately stacked. The charge storage structures are disposed at one side of the gates. Two adjacent charge storage structures are isolated by the first dielectric layer therebetween. Each of the charge storage structures includes a first oxide layer, a nitride layer and a second oxide layer sequentially disposed at one side of each of the gates. The channel layer is disposed on a sidewall of the stacked structure adjacent to the charge storage structures.

Abstract: Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

Abstract: According to the embodiment, a semiconductor device includes: a substrate; a stacked body provided on the substrate and including a plurality of electrode layers stacked with an insulator interposed; a semiconductor pillar provided on the substrate and in the stacked body; a semiconductor body provided in the stacked body; and an insulating film including a charge storage film provided between the plurality of electrode layers and the semiconductor body, and extending in the stacking direction. The semiconductor body includes a first portion and a second portion. The first portion is surrounded with the plurality of electrode layers and extends in a stacking direction of the stacked body. The second portion is in contact with an upper surface of the semiconductor pillar.

Abstract: An electronic component made up of field-effect transistor (FET) cells is disclosed. Each FET cell includes a finger region having drain, gate, and source fingers disposed over a semiconductor substrate. An isolation region extends across a first end of the finger region. An off-state linearization region abuts the first end of the isolation region. A doped well is disposed within the off-state linearization region over the semiconductor substrate. A dielectric layer is disposed over the doped region. A first conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A second conductive stripe is disposed over the dielectric layer in longitudinal alignment with the drain finger. A drain finger electrode is aligned over and coupled to both the drain finger and the first conductive stripe. A source finger electrode is aligned over and coupled to both the source finger and the second conductive stripe.

Abstract: The present invention provides a manufacturing method of an array substrate and an array substrate. The manufacturing method of the array substrate according to the present invention combines the COA technology and the BOA technology, where a black matrix is first formed on a backing plate, followed by forming a top-gate TFT device on the black matrix, and finally forming a color filter layer on the TFT device, wherein the pixel electrode is directly arranged on the drain electrode and connected with the drain electrode. The manufacturing method helps enhance electrical performance of a TFT device and stability of performance, improves quality of a display panel, and, compared to an existing array substrate manufacturing method, reduces masks and operations involved. The manufacturing method is simple and helps reduce manufacturing costs.

Abstract: A thin film transistor “TFT”) substrate includes a substrate, an active layer over the substrate, and first and second TFTs over the substrate. The active layer includes: a first drain region, a first channel region and a first source region, which function as a drain, a channel and a source of the first TFT: a first lightly doped region between the first drain region and the first channel region: a second lightly doped region between the first channel region and the first source region: and a second drain region, a second channel region and a second source region, which function as a drain, a channel and a source of the second TFT. An impurity concentration at the second drain or source region is lower than an impurity concentration at the first drain or source region and higher than an impurity concentration at the first or second channel region.

Abstract: A display device includes a driver circuit including a logic circuit including a first transistor which is a depletion type transistor and a second transistor which is an enhancement type transistor; a signal line which is electrically connected to the driver circuit; a pixel portion including a pixel whose display state is controlled by input of a signal including image data from the driver circuit through the signal line; a reference voltage line to which reference voltage is applied; and a third transistor which is a depletion type transistor and controls electrical connection between the signal line and the reference voltage line. The first to the third transistors each include an oxide semiconductor layer including a channel formation region.

Abstract: According to an embodiment of the present disclosure, a method for manufacturing the array substrate includes forming a first transparent conductive layer and a metallic layer successively on a base substrate, and forming a gate electrode, a source electrode, a drain electrode and a first transparent electrode by one patterning process.

Abstract: A method of printing transferable components includes pressing a stamp including at least one transferable semiconductor component thereon on a target substrate such that the at least one transferable component and a surface of the target substrate contact opposite surfaces of a conductive eutectic layer. During pressing of the stamp on the target substrate, the at least one transferable component is exposed to electromagnetic radiation that is directed through the transfer stamp to reflow the eutectic layer. The stamp is then separated from the target substrate to delaminate the at least one transferable component from the stamp and print the at least one transferable component onto the surface of the target substrate. Related systems and methods are also discussed.

Abstract: The invention provides a TFT substrate manufacturing method and TFT substrate. The TFT substrate manufacturing method first etches the gate insulation layer to form two first through-holes and forming two bridging metal blocks inside the two first through holes; then etches the interlayer dielectric layer to form two second through-holes connecting respectively the two first through-holes, the source and drain connecting the two bridging metal blocks respectively through the two second through-holes. By changing a conventional etching process into two etching process to form the through-hole structure on the gate insulation layer and interlayer dielectric layer, able to improve uniformity of the active layer, reduce process difficulty, avoid the problem of etching stopped due to higher etching thickness, and improve the product quality.

Abstract: The present disclosure relates to a solid-state image sensor, an electronic apparatus and an imaging method by which specific processing other than normal processing can be sped up with reduced power consumption. The solid-state image sensor includes a pixel outputting a pixel signal used to construct an image and a logic circuit driving the pixel, and is configured of a stacked structure in which a first semiconductor substrate including a plurality of the pixels and a second semiconductor substrate including the logic circuit are joined together. In addition, among the plurality of pixels, a specific pixel is connected to the logic circuit independently of a normal pixel, the specific pixel being the pixel that outputs the pixel signal used in the specific processing other than imaging processing in which the image is imaged. The present technology can be applied to a stacked solid-state image sensor, for example.

Abstract: An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for additional absorption. In addition, the elevated photosensors reduce the size of the pixel cells while reducing leakage, image lag, and barrier problems.

Abstract: Implementations of semiconductor packages may include: a substrate coupled to one or more die and to one or more connectors, a glass lid coupled over one or more die by an adhesive and a housing comprising one or more sides and a bottom opening and a top opening. The substrate may be coupled to the housing at the bottom opening and the glass lid may be coupled under the housing at the top opening.

Abstract: In an imaging device, a plurality of first photoelectric conversion units generate a first signal based on first visible light and infrared light. A plurality of second photoelectric conversion units generate a second signal based on only second visible light. An infrared absorption layer absorbs the infrared light and transmits only the second visible light. A plurality of third photoelectric conversion units generate a third signal based on the infrared light. A signal processing circuit generates a fourth signal by correcting the first signal using the third signal. The signal processing circuit generates a visible light image signal on the basis of the second signal and the fourth signal. The signal processing circuit generates an infrared light image signal on the basis of the third signal.

Abstract: An image sensor includes a plurality of photodiodes formed in a substrate; nano void regions formed in the substrate adjacent to sides of each photodiode of the plurality of photodiodes; and a plurality of nano voids formed in each nano void region of the nano void regions.

Abstract: A multi-color HDR image sensor includes at least a first combination color pixel with a first color filter and an adjacent second combination color pixel with a second color filter which is different from the first color filter, wherein each combination color pixel includes at least two sub-pixels having at least two adjacent photodiodes. Within each combination color pixel, there is a dielectric deep trench isolation (d-DTI) structure to isolate the two adjacent photodiodes of the two adjacent sub-pixels with same color filters in order to prevent the electrical cross talk. Between two adjacent combination color pixels with different color filters, there is a hybrid deep trench isolation (h-DTI) structure to isolate two adjacent photodiodes of two adjacent sub-pixels with different color filters in order to prevent both optical and electrical cross talk. Each combination color pixel is enclosed on all sides by the hybrid deep trench isolation (h-DTI) structure.