Abstract: An apparatus comprises a slider having an air bearing surface (ABS) that is configured for heat-assisted magnetic recording and comprises a write pole and a near-field transducer. The near-field transducer comprises a peg, an enlarged portion, and a dielectric layer. The peg has a front surface proximate the ABS, an opposing back surface, a top surface facing the write pole, two side surfaces, and a bottom surface opposing the top surface. The enlarged portion surrounds a portion of the peg including the back surface and has a front edge facing the ABS, wherein the distance from the ABS to the front edge is larger than the distance from the ABS to the front surface. The dielectric layer is disposed on a portion of the top surface of the peg and extends from the back surface of the peg to the front edge.

Abstract: The disclosure provides a method, device and system for recording information, a storage medium and a processing unit. The method for recording information includes that: non-Audio/Video (AV) information forming a preset association relationship with a first target file is acquired, wherein the first target file includes AV information; and the AV information and the non-AV information are synchronously recorded according to an information synchronization condition.

Abstract: A method of manufacturing magnetic tape storage data cartridges may include cutting a master tape having a first width into multiple tape sections that each have a smaller width than the first width, cleaning the tape sections to remove debris caused by the cutting, and writing the servo tracks on each tape section after the tape section is cleaned. The method may further include spooling each tape section into a respective tape cartridge after writing the servo track on the tape section.

Abstract: An automatic playback overshoot correction system predicts the position in the program material where the user expects to be when the user stops the fast forward progression of the program material. The system determines the position where the program material was stopped and transitions to the new mode that the user selected, starting at the stopped position with an overshoot correction factor subtracted from it. The system uses a prediction method to correctly place the user within the program upon transition out of fast forward mode and determines if the speed of the fast forward mode and then automatically subtracts a time multiple to the frame where the transition was detected and positions the user at the correct frame. The time multiple is fine tuned if the user is consistently correcting after the fast forward mode stops.

Abstract: The present disclosure provides an electronic device for generating a multiple point of view (MPOV) video and the method thereof. The present disclosure involves the electronic device to obtain a plurality of media contents. The electronic device would identify a first media content relating to a second media content in time and location according to time information, audio information, and location information including a geographic tag and a surrounding signal information. Then, the first media content and the second media content are provided as relevant media contents for generating the MPOV video of the event having the relevant media content captured from different point of view.

Abstract: Technologies for implementing embedding interactive content into a shareable online video. The technologies include an authoring tool including a graphical user interface (GUI). The tool can be used to input an edit decision list (EDL) file and a video file that has a video. The GUI can provide a view of specific scenes of the video according to the EDL file and the video file. The GUI can also provide interactive features. Through the GUI and/or the tool, a selection of a scene of the specific scenes can be inputted as well as a selection of an interactive feature from the interactive features can be inputted. Then, the tool can embed the selected interactive feature into the selected scene at a selected specific spatial location in the selected scene. The tool can also output the video file with the embedded interactive feature.

Abstract: Implementations relate to visualizations including images based on image content. In some implementations, a computer-implemented method includes obtaining a set of images, determining one or more pixel characteristics of the set of images, and determining one or more faces depicted in the plurality of images based on one or more pixel characteristics. The method selects a group of images of the set of images, where each image in the group of images depicts a different group of faces than depicted in the other images in the set of images. The method generates a visualization including the group of images, and provides the visualization to a user device in response to a user request to cause the group of images to be displayed by the user device.

Abstract: A reproduction unit synchronously reproduces different videos recorded in the same time zone on each of a main pane and a sub pane of which a size is smaller than a size of the main pane of a reproduction screen having the main pane and the sub pane. A reproduction switching unit switches the video reproduced on the main pane to the video reproduced on the sub pane during a reproduction of the video by the reproduction unit.

Abstract: A holding device includes a frame module and an accommodation unit. The frame module includes a plate body and two lateral plates oppositely disposed on the first plate body. A placement area is collectively defined by the plate body and the lateral plates. Two protrusions are respectively provided on the lateral plates. The accommodation unit includes a tray and two elastic plates. The tray is slidably located within the placement area, and an accommodation space is defined between two opposite sides of the tray. Each elastic plate is elastically connected to one of opposite sides of the tray. When the tray is moved after a load is placed within the accommodation space, the protrusions respectively push the elastic plates towards the accommodation space so that the load is toollessly fastened between the elastic plates.

Abstract: The present disclosure relates generally to the field of power supply wiring in a semiconductor device. In one embodiment, a semiconductor device is disclosed that includes, an uppermost metal layer including a power supply enhancing wiring, power supply wiring coupled to the power supply enhancing wiring through a via between the uppermost metal layer and a metal layer underlying the uppermost metal layer, and at least one memory device component disposed in vertical alignment with the via between the uppermost metal layer and the metal layer underlying the uppermost metal layer.

Abstract: Techniques and mechanisms for configuring a memory device to perform a sequence of in-memory computations. In an embodiment, a memory device includes a memory array and circuitry, coupled thereto, to perform data computations based on the data stored at the memory array. Based on instructions received at the memory device, control circuitry is configured to enable an automatic performance of a sequence of operations. In another embodiment, the memory device is coupled in an in-series arrangement of other memory devices to provide a pipeline circuit architecture. The memory devices each function as a respective stage of the pipeline circuit architecture, where the stages each perform respective in-memory computations. Some or all such stages each provide a different respective layer of a neural network.

Abstract: Examples may include techniques to mitigate bias drift for memory cells of a memory device. A first memory cell coupled with a first word-line and a bit-line is selected for a write operation. A second memory cell coupled with a second word-line and the bit-line is de-selected for the write operation. First and second bias voltages are applied to the first word-line and the bit-line during the write operation to program the first memory cell. A third bias voltage is applied to the second word-line during the write operation to reduce or mitigate voltage bias to the second memory cell due to the second bias voltage applied to the bit-line to program the first memory cell.

Abstract: Apparatuses, circuits, and methods are disclosed for biasing signal lines in a memory array. In one such example the memory array includes a signal line coupled to a plurality of memory cells and is configured to provide access to the plurality of memory cells responsive to a biasing condition of the signal line. The memory array also includes a signal line driver coupled to the signal line, the signal line driver configured to provide a biasing signal to the signal line and to provide a preemphasis in the biasing signal responsive to a control signal. The control signal is responsive to an operating condition.

Abstract: A cycle control circuit may include a judgement pulse generation circuit, a detection signal generation circuit or a flag generation circuit. The judgement pulse generation circuit may be configured to set a predetermined value based on an initialization signal and a period signal, and to generate a judgment pulse. The detection signal generation circuit may be configured to generate a detection signal from a reference flag. The flag generation circuit may be configured to generate a reference flag based on a reference signal. A cycle of the reference signal may be maintained or adjusted based on the reference flag.

Abstract: Various embodiments may provide a circuit arrangement. The circuit arrangement may include a first spin-orbit torque magnetic tunnel junction cell, a second spin-orbit torque magnetic tunnel junction cell, a first driver circuit arrangement, a second driver circuit arrangement, and a read circuit arrangement. The circuit arrangement allows for the operation of a non-volatile flip-flop based on spin-orbit torque effect.

Abstract: A spin current magnetization rotational element includes: a first ferromagnetic metal layer for a magnetization direction to be changed; and a spin-orbit torque wiring. The spin-orbit torque wiring has a structure in which a spin conduction layer and an interfacial spin generation layer are alternately laminated in the first direction, the number of a plurality of the interfacial spin generation layers is two or greater, and in the spin-orbit torque wiring, one of the plurality of interfacial spin generation layers is closest to the first ferromagnetic metal layer.

Abstract: A semiconductor device includes a first serializer configured to collect at least one event in a first domain to generate a first serial data stream and transmit the first serial data stream periodically at a first period, a first de-serializer configured to receive the first serial data stream to restore the first serial data stream into first parallel data streams, the first parallel data stream encoding first parallel data items, a timer configured to provide a clock signal having a second period, a direct memory access (DMA) configured to capture the first parallel data items periodically at a second period using the clock signal to generate capture data items, and a first memory configured to store the capture data items. The addresses of the first memory at which the respective capture data items are stored are arranged in an order that the respective capture data items are captured.

Abstract: A memory device with reduced power consumption is provided. The memory device includes a plurality of memory cells, a precharge circuit, a latch circuit, a bit line pair, and a local bit line pair. The precharge circuit has a function of supplying precharge voltage to the local bit line pair. The plurality of memory cells are connected to the local bit line pair. The latch circuit is connected to the local bit line pair. The latch circuit in a standby state is preferably supplied with the precharge voltage and one of low power supply voltage and high power supply voltage.

Abstract: A circuit includes a dummy wordline, a dummy bitline, and a dummy cell coupled to the dummy bitline. The dummy cell includes an active pulldown nMOSFET and a pass nMOSFET having a gate connected to the dummy wordline, a first source terminal connected to the drain terminal of the active pulldown nMOSFET, and a drain terminal connected to the dummy bitline. The circuit further includes a substrate-connected dummy bitline coupled to the source terminal of each active pulldown nMOSFET and coupled to a substrate.

Abstract: Embodiments of the present disclosure are directed towards techniques to provide structural integrity for a memory device comprising a memory array. In one embodiment, the device may comprise a memory array having at least a plurality of wordlines disposed in a memory region of a die, and a first fill layer deposited between adjacent wordlines of the plurality of wordlines in the memory region, to provide structural integrity for the memory array. At least a portion of a periphery region of the die adjacent to the memory region may be substantially filled with a second fill layer that is different than the first fill layer. Other embodiments may be described and/or claimed.

Abstract: Examples are disclosed for adaptive configuration of non-volatile memory. The examples include a mode register configured to include default and updated values to indicate one or more configurations of the non-volatile memory. The examples may also include discoverable capabilities maintained in a configuration table that may indicate memory address lengths and/or operating power states.

Abstract: A writing method of a resistive memory storage apparatus is provided. The writing method includes: applying a first set voltage on a memory cell, and acquiring a first reading current of the memory cell; applying a first disturbance voltage on the memory cell, and acquiring a second reading current of the memory cell; and determining to apply a second set voltage or a second disturbance voltage on the memory cell according to a magnitude relationship between the first reading current and the second reading current. An absolute value of the first disturbance voltage is smaller than an absolute value of a reset voltage, and an absolute value of the second disturbance voltage is smaller than an absolute value of the second set voltage. In addition, a resistive memory storage apparatus is also provided.

Abstract: A variable resistance memory array, programming a variable resistance memory element and methods of forming the array. A variable resistance memory array is formed with a plurality of word line transistors surrounding each phase change memory element. To program a selected variable resistance memory element, all of the bitlines are grounded or biased at the same voltage. A top electrode select line that is in contact with the selected variable resistance memory element is selected. The word line having the word line transistors surrounding the selected variable resistance memory element are turned on to supply programming current to the element. Current flows from the selected top electrode select line through the variable resistance memory element into the common source/drain region of the surrounding word line transistors, across the transistors to the nearest bitline contacts. The word lines are patterned in various lattice configurations.

Abstract: A state-changeable device includes a first and a second particle arranged in proximity to each other; and a coupling material between the first and the second particle; wherein the first and the second particle are adapted to provide a charge carrier distribution such that surface plasmon polaritons (SPP) occur; and the coupling material is adapted to exhibit a variable conductivity in response to a trigger signal thereby changing an electro-optical coupling between the first and the second particle.

Abstract: The total chip area for a three-dimensional memory device can be reduced employing a design layout in which the word line decoder circuitry is formed underneath an array of memory stack structures. The interconnection between the word lines and the word line decoder circuitry can be provided by forming discrete word line contact via structures. The discrete word line contact via structures can be formed by employing multiple sets of etch masks with overlapping opening areas and employed to etch a different number of pairs of insulating layers and electrically conductive layers, thereby obviating the need to form staircase regions having stepped surfaces. Sets of at least one conductive interconnection structure can be employed to provide vertical electrical connection to the word line decoder circuitry. Bit line drivers can also be formed underneath the array of memory stack structures to provide greater areal efficiency.

Abstract: Provided is a method performed by a nonvolatile memory device, the method may include: initiating a first program operation corresponding to a first program loop among a plurality of program loops; receiving a suspend command for an urgent read operation during the first program operation; determining a recovery timing from either of a first timing contemporaneous with the receiving the suspend command, and a second timing after completion of the first program operation, based on the suspend command; and initiating a recovery at the determined recovery timing by applying a recovery voltage to a selected word line.

Abstract: A semiconductor memory device including a memory cell array including a plurality of memory blocks, a voltage generator applying operation voltages to a selected memory block, among the plurality of memory blocks, a control logic generating converted data by converting data bit sets respectively corresponding to at least one set of program states among a plurality of program states, during a program operation, and a read and write circuit temporarily storing the converted data and performing a program operation by controlling potential levels of bit lines of the memory cell array in accordance with stored converted data.

Abstract: The invention is directed to an electronic device. A memory device having improved reliability according to an embodiment includes a memory cell array including a plurality of memory cells, a peripheral circuit performing a program operation on selected memory cells, among the plurality of memory cells, and a control logic controlling the peripheral circuit to perform an additional program operation on memory cells corresponding to a deep erased state where the memory cells has a threshold voltage having a lower voltage level than a threshold voltage of an erase state, among the selected memory cells, after the program operation is completed.

Abstract: A data storage device includes a non-volatile memory device and a controller. The controller is configured to calculate a read range including read regions that may correspond to each of read commands for the same physical address among a plurality of read commands received from a host device. The controller may be configured to generate an integral read command for simultaneously reading the calculated read range. The controller may transmit the integral read command to the non-volatile memory device.

Abstract: A semiconductor storage device includes a plurality of memory cells, bit lines respectively connected to the third memory cells, sense circuits respectively connected to the bit lines, latch circuits respectively connected to the sense circuits, and an input and output circuit connected to a first set of latch circuits via a first data line, a second set of latch circuit via a second data line, and a third set of latch circuits via a third data line. The bit lines are disposed in sequence in a first direction and a group of the sense circuits is disposed in sequence in a second direction crossing the first direction, and two bit lines that are not adjacent in the first direction are connected respectively to two sense circuits in the group that are adjacent in the second direction.

Abstract: A flash memory storage apparatus and a reading method thereof are provided. The flash memory storage apparatus includes a memory cell array and a memory control circuit. The memory cell array includes at least one memory cell string coupled between a bit line and a source line. The memory control circuit is coupled to the memory cell array and configured to control a read operation of the memory cell array during the reading period. The reading period includes a pre-charge period and a discharge period. The source line performs a pre-charge operation on the bit line via a signal transmission path during the pre-charge period. The bit line performs a discharge operation on the source line via the same signal transmission path during the discharge period. The signal transmission path includes the memory cell string.

Abstract: In an embodiment, a method is provided for controlling a level of a read current in a non-volatile memory that is powered by a supply voltage includes. A model current representative of an actual current able to flow during a readout through a read path of the memory is determined based on the value of the supply voltage. The model current is compared to a reference current having a reference value. A control signal is generated. The control signal is to control the generation of the read current having a level equal to the lowest value between a fraction of the value of the model current and the reference value.

Abstract: A memory device and associated techniques for reducing read disturb of memory cells during a sensing process. The drain-end select gate transistors of unselected sub-blocks are made temporarily conductive for a time period during the ramp up of the unselected word line voltages to reduce the amount of capacitive coupling up of the respective memory string channel. This reduces a channel gradient which can exist in the memory string channels, thereby also reducing the read disturb. Further, the time period is greater when the selected word line is in a source-end or midrange subset of the word lines than when the selected word line is in a drain-end subset of the word lines. Another option involves omitting the injection disturb countermeasure, or providing a less severe injection disturb countermeasure, when the unselected sub-blocks are unprogrammed.

Abstract: A method for writing data to a NAND flash memory is disclosed, having steps of writing a first set of data to a first memory block, writing a second set of data to a second memory block, writing a third set of data to a third memory block and writing a fourth set of data to a XNOR memory block.

Abstract: A memory device having an improved program speed may include a memory cell array including a plurality of memory cells, each being programmed to one of a plurality of program states; a peripheral circuit configured to perform a program operation to one or more of the plurality of memory cells, the program operation including a program voltage applying operation and a verify operation; and a control logic configured to control the peripheral circuit to simultaneously perform the verify operation for at least two program states by applying bit line voltages having different voltage levels to bit lines coupled to the plurality of memory cells.

Abstract: Disclosed are a memory device, including: a memory block including a plurality of cell strings; a peripheral circuit configured to set voltages for a program operation of selected memory cells in the cell strings, and program the selected memory cells by using the set voltages; and a control circuit configured to control the peripheral circuit so that the selected memory cells are programmed in response to a program command, and increase a channel voltage of non-selected cell strings including non-selected memory cells while the selected memory cells are programmed, and an operating method thereof.

Abstract: A memory controller includes a memory that stores therein data corresponding to a distribution of write durations measured from a nonvolatile memory device of a specific model, and a processor that measures a write duration taken to write data to a memory cell in a nonvolatile memory device of a same model as the specific model and that determines whether or not the memory cell is defective by evaluating, based on the data corresponding to the distribution, a displacement of the measured write duration from a center portion of the distribution.

Abstract: An antifuse device is disclosed. The antifuse device includes a plurality of active regions, a plurality of word lines extending along a first direction and cut through the active regions, a plurality of bit lines and a plurality of source lines extending along a second direction and stride across the active regions. The bit lines and the source lines are arranged alternatively along the first direction. Plural antifuse capacitors are disposed along the source lines and connected between the source lines and the active regions.

Abstract: There are provided a shift register unit and a driving method thereof. The shift register unit includes: an input circuit, whose first terminal receives an input signal of the shift register unit, and second terminal is connected to a pull-up node, the input circuit being configured to output the input signal to the pull-up node; an output circuit, whose first terminal is connected to a clock signal terminal, second terminal is connected to the pull-up node, third terminal is connected to an output terminal of the shift register unit, the output circuit being configured to output a signal of the clock signal terminal to the output terminal under the control of the pull-up node; a pull-up node control circuit, and the pull-up node control circuit being configured to discharge the pull-up node through third power supply voltage terminal under the control of a first power supply voltage terminal.

Abstract: Embodiments of structures and methods for testing three-dimensional (3D) memory devices are disclosed. In one example, a 3D memory device includes a memory array structure, a peripheral device structure, and an interconnect layer in contact with a front side of the memory array structure and a front side of the peripheral device structure, and a conductive pad at a back side of the memory array structure and that overlaps the memory array structure. The memory array structure includes a memory array stack, a through array contact (TAC) extending vertically through at least part of the memory array stack, and a memory array contact. The peripheral device structure includes a test circuit. The interconnect layer includes an interconnect structure. The conductive pad, the TAC, the interconnect structure, and at least one of the test circuit and the memory array contact are electrically connected.

Abstract: Read-assist circuits for memory bit cells employing a P-type Field-Effect Transistor (PFET) read port(s) are disclosed. Related memory systems and methods are also disclosed. It has been observed that as node technology is scaled down in size, PFET drive current (i.e., drive strength) exceeds N-type FET (NFET) drive current for like-dimensioned FETs. In this regard, in one aspect, it is desired to provide memory bit cells having PFET read ports, as opposed to NFET read ports, to increase memory read times to the memory bit cells, and thus improve memory read performance. To mitigate or avoid a read disturb condition that could otherwise occur when reading the memory bit cell, read-assist circuits are provided for memory bit cells having PFET read ports.

Abstract: Apparatuses and methods for latching redundancy repair addresses at a memory are disclosed. An example apparatus includes block of memory including primary memory and a plurality of redundant memory units and repair logic. The repair logic including a plurality of repair blocks. A repair block of the plurality of repair blocks is configured to receive a set of repair address bits associated with a memory address for defective memory of the block of memory and to latch the set of repair address bits at a respective set of latches. The repair block is further configured to, in response to receipt of a memory access request corresponding to the set of repair address bits latched at the repair block, redirecting the memory access request to a redundant memory unit associated with the repair block.

Abstract: Point of care drug of abuse test system configured to allow a small number of general test kits to be used to analyze many different combinations of analytes, while preserving privacy and the chain of custody. The system uses disposable multiple-analyte test kits and allows the operator to select which subset of kit analytes to run. The computerized device images the test kits and transmits test results to a remote server along with a test specific ID code. The test kit is often obfuscated so that the local operator cannot interpret the results. Other donor information, such as driver's licenses and signatures, are also obtained and transmitted as well. The remote server uses the test specific ID code to retrieve an obfuscation code (answer key) from the server's database, allowing the server to interpret the results. The annotated results are transmitted to a recipient along with suitable donor verification information.

Abstract: An automated medical note generation system utilizes text, audio and video data to automatically create medical notes in real-time from data sources that are generated actively during clinical events.

Abstract: A system and method for managing data of one or more patients is provided. The method includes the steps of: (a) processing a first set of data and a second set of data to consolidate (i) the first set of data and (ii) the second set of data into a single source data; (b) tagging, by a primary physician, the first set of data and/or the second set of data with selected each of one or more secondary physicians; (c) integrating the patient health management system with one or more health monitoring devices to obtain the data and to communicate the first set of data and/or the second set of data to their the one or more of physicians; and (d) consolidating the first set of data and/or the second set of data in standard formats.

Abstract: The purpose of the present invention is to establish methods for: building medical big data taking privacy into consideration; deriving a more appropriate medicine dosage corresponding to medicine dosage and attribute information of patients; and discovering, in addition to the effect of the medicine on one disease symptom, the effect on another disease symptom. In the present invention, a data collection unit 40 collects health examination data and the like. A patient attribute information acquisition unit 61 acquires at least one attribute of a patient input from a patient terminal 1. A corresponding information acquisition unit 62 acquires, from a corresponding information database 82, corresponding information indicating a correspondence relationship between a medicine dosage having an effect on a disease symptom of which the patient is aware and the at least one attribute.

Abstract: Systems and methods for rapid importation of data including temporally tracked object recognition. One of the methods includes receiving a request to authorize a prescription for a patient, the request being from a medical professional and the request being received of a network. The request is determined to be approved based on information associated with the patient. Transaction information is generated that is associated with the prescription, the transaction information specifying that the patient is authorized to obtain an associated pharmaceutical, and the transaction information being included in a transaction record associated with the patient. Authorization information associated with the prescription is generated, the authorization information being provided to a user device of the patient, and the authorization information enabling confirmation by an outside system that the prescription is authorized.

Abstract: A method of recording a medicament dose using a data collection device comprises capturing, by a video camera of said data collection device, a video showing a medicament dose indicator of a medicament delivery device, adjusting a scale of an image of said medicament dose indicator in said video, adjusting said image for skew of one or more characters displayed on a component of the medicament delivery device in said video, determining the position of at least one of said one or more characters in the image, identifying the at least one character using optical character recognition and determining a medicament dose shown by the medicament dose indicator based on a result of said optical character recognition. The method may include determining whether more than one delivery of medicament is recorded in the video and, if so, whether said more than one delivery includes one or more prime shots, so that an overall dosage delivered to a user may be determined based on multiple determined medicament doses.

Abstract: Methods, systems, and apparatus monitor medication usage data for one patient or a population of patients, which can be processed to determine compliance patterns. Such methods and systems can associate, analyze, organize and present medication usage data, compliance patterns, and correlations between compliance patterns and outcomes data for electronic analysis or analysis by a caretaker. Such methods, systems, and apparatus permit analysis of compliance patterns to enable, for example, establishment or adjustment of safe and effective treatment regimens, and may include feedback systems for ensuring authenticity of medication and/or effects of medication on a patient.

Abstract: A system for monitoring diet. The system for monitoring diet includes: an information transmitter configured to transmit information of a food to be eaten in response to an operation of an eater taking out the food to be eaten; and an information processor configured to receive the information of the food from the information transmitter and to determine whether the food to be eaten meets requirements or not according to the information of the food to be eaten and a pre-stored information regarding the food that the eater needs to ingest.