Abstract: A method of forming a semiconductor device includes providing a starting structure including a substrate having thereon a plurality of gate regions alternately arranged with a plurality of source/drain (S/D) regions, wherein each of the gate regions includes a nanochannel structure having an intermediate portion surrounded by a replacement gate, and opposing end portions surrounded by respective gate spacers such that the nanochannel structure extends through the replacement gate and the gate spacers of the gate region. Each of the S/D regions includes an S/D structure extending through the S/D region to connect nanochannel structures of first and second adjacent gate regions provided on opposing sides of the S/D region respectively.

Abstract: Modified silicon-on-insulator (SOI) substrates having a trap rich layer, and methods for making such modifications. The modified regions eliminate or manage accumulated charge that would otherwise arise because of the interaction of the underlying trap rich layer and active layer devices undergoing transient changes of state, thereby eliminating or mitigating the effects of such accumulated charge on non-RF integrated circuitry fabricated on such substrates. Embodiments retain the beneficial characteristics of SOI substrates with a trap rich layer for RF circuitry requiring high linearity, such as RF switches, while avoiding the problems of a trap rich layer for circuitry that is sensitive to accumulated charge effects caused by the presence of the trap rich layer, such as non-RF analog circuitry and amplifiers (including power amplifiers and low noise amplifiers).

Abstract: A laser annealing apparatus including a carrying platform with a fixing surface, a laser source and a driving device. The laser source is configured to emit a laser beam toward the fixing surface, the laser beam having an illumination area which covers a center of the fixing surface and extends toward an edge of the fixing surface, in an extending direction of the illumination area the illumination area having a length which is not less than a distance between the center of the fixing surface and the edge of the fixing surface. The driving device is configured to drive the carrying platform to rotate around the center of the fixing surface.

Abstract: A method of forming fine line patterns of semiconductor devices includes: forming a plurality of linear core structures on at least one hard mask layer disposed on a target layer; forming first spacers on sidewalls of the linear core structures; removing the linear core structures; forming second spacers on sidewalls of the first spacers; etching exposed portions of the hard mask layer exposed by the first spacers and the second spacers; and removing the first spacers and the second spacers.

Abstract: A method of forming fine line patterns of semiconductor devices includes: forming a plurality of lower linear core structures on at least one lower hard mask layer disposed on a target layer; forming a spacer layer on the hard mask layer to cover the lower linear core structures; forming an upper hard mask layer on the spacer layer; thinning the upper hard mask layer to expose potions of the spacer layer; and removing the exposed portions of the spacer layer to form a plurality of line patterns on the lower hard mask layer.

Abstract: A method of forming a pattern includes forming a lower layer on a substrate, forming a mask pattern on the lower layer, the mask pattern extending in a first direction parallel to a top surface of the substrate, and performing an etching process using an ion beam on the substrate, such that the ion beam is irradiated in parallel to a plane defined by the first direction and a direction perpendicular to the top surface of the substrate, and is irradiated at a tilt angle with respect to the top surface of the substrate, wherein performing the etching process includes adjusting the tilt angle of the ion beam to selectively etch the lower layer or the mask pattern.

Abstract: A semiconductor device that includes a semiconductor layer disposed on a semiconductor substrate, a first semiconductor region provided in an upper layer portion of the semiconductor layer, a second semiconductor region provided in an upper layer portion of the first semiconductor region, a gate insulation film, a gate electrode, a first main electrode that is provided on an interlayer insulation film that covers the gate electrode and that is electrically connected to the second semiconductor region via a contact hole, and a second main electrode disposed on a second main surface of the semiconductor substrate. The first main electrode includes an underlying electrode film connected to the second semiconductor region via the contact hole, and a copper film provided on the underlying electrode film. The copper film includes at least a portion that serves as a stress relaxation layer having a smaller grain size than the other portion of the copper film.

Abstract: Implementations of a method of forming a semiconductor package may include forming electrical contacts on a first side of a wafer, applying a photoresist layer to the first side of the wafer, patterning the photoresist layer, and etching notches into the first side of the wafer using the photoresist layer. The method may include applying a first mold compound into the notches and over the first side of the wafer, grinding a second side of the wafer opposite the first side of the wafer to the notches formed in the first side of the wafer, applying one of a second mold compound and a laminate resin to a second side of the wafer, and singulating the wafer into semiconductor packages. Six sides of each semiconductor package may be covered by one of the first mold compound, the second mold compound, and the laminate resin.

Abstract: Wafers processed by methods of plasma etching are disclosed. In one embodiment, a wafer is prepared by a process including positioning the wafer within a chamber of a plasma etcher, generating plasma ions using a radio frequency power source and a plasma source gas, directing the plasma ions toward the wafer using an electric field, focusing the plasma ions using a plasma focusing ring to increase a flux of plasma ions arriving at a surface of the wafer, and etching a plurality of through-wafer vias in the wafer.

Abstract: A semiconductor device and fabrication method thereof are provided. The fabrication method include: providing a to-be-etched material layer; forming a plurality of discrete sacrificial layers on the to-be-etched material layer; forming first initial spacers on sidewalls of each sacrificial layer, where each first initial spacer includes a first bottom region and a first top region on the first bottom region; removing the sacrificial layers; removing the first bottom region of the first initial spacer to form a first spacer from the first top region; forming second spacers on sidewalls of each first spacer; removing the first spacer; and etching the to-be-etched material layer by using the second spacers as an etch mask.

Abstract: A process for chemical mechanical polishing a substrate containing titanium nitride and titanium is provided comprising: providing a polishing composition, containing, as initial components: water; an oxidizing agent; a linear polyalkylenimine polymer; a colloidal silica abrasive with a positive surface charge; a carboxylic acid; a source of ferric ions; and, optionally pH adjusting agent; wherein the polishing composition has a pH of 1 to 4; providing a chemical mechanical polishing pad, having a polishing surface; creating dynamic contact at an interface between the polishing pad and the substrate; and dispensing the polishing composition onto the polishing surface at or near the interface between the polishing pad and the substrate; wherein at least some of the titanium nitride and at least some of the titanium is polished away with a selectivity between titanium nitride and titanium.

Abstract: A silicon oxide film or a silicon nitride film is selectively etched by using an etching gas composition including a hydrofluorocarbon that has an unsaturated bond in its molecule and is represented by CxHyFz, wherein x is an integer of from 3 to 5, and relationships y+z?2x and y?z are satisfied. Also, a silicon oxide film is etched with high selectivity relative to a silicon nitride film by controlling the ratio among the hydrofluorocarbon, oxygen, argon, etc., included in the hydrofluorocarbon-containing etching gas composition.

Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing semiconductor substrates. In one embodiment, a batch processing chamber is disclosed. The batch processing chamber includes a chamber body enclosing a processing region, a gas panel configured to provide a processing fluid into the processing region, a condenser fluidly connected to the processing region and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The processing region is configured to retain a plurality of substrates during processing. The condenser is configured to condense the processing fluid into a liquid phase.

Abstract: Many aspects of an IC package are disclosed. The IC package includes a substrate, an integrated circuit die, a vertical capacitor and a conductive layer. The substrate includes a first plurality of substrate pads. The integrated circuit die is coupled to the first plurality of substrate pads embedded in a first layer of the substrate. The vertical capacitor has a first electrode, a second electrode and a first resistive layer. The first electrode is coupled to the first resistive layer. The first resistive layer is coupled to a first substrate pad embedded in the first layer of the substrate. The conductive layer is formed over a first surface and the second electrode of the vertical capacitor. The conductive layer encapsulates the vertical capacitor. The first and second electrodes are parallel to each other and perpendicular to a planar surface of the substrate.

Abstract: An imprint apparatus that molds an imprint material on a substrate with a mold, the imprint apparatus including a applying device that includes a discharge surface in which a discharge opening is formed, the applying device applying the imprint material to the substrate through the discharge opening, and a measuring device that measures the position of the discharge opening by having the measuring device measure a position of an uneven structure formed in a protruded shape or a recessed shape with respect to a direction perpendicular to the discharge surface.

Abstract: A nozzle includes a nozzle body having a hollow portion, and a mixing chamber and a discharge guide sequentially connected to the hollow portion, and an engagement member having a gas supply passage formed to supply a gas therethrough, inserted and fixed into the hollow portion and spaced apart from an inner face of the hollow portion to form a liquid gas supply passage which supplies a liquid toward a central axis of an exit of the gas supply passage. The mixing chamber is connected to the gas supply passage and the liquid supply passage to form liquid droplets. The gas supply passage has a first cross-sectional area, the mixing chamber has a second cross-sectional area substantially the same as the first cross-sectional area, and the discharge guide has a third cross-sectional area smaller than the first cross-sectional area.

Abstract: The present invention provides a wafer cleaning apparatus including: a cleaning tank; and a cleaning unit installed to be capable of moving upward or downward into the cleaning tank, and configured to inject a cleaning solution onto an inner wall of the cleaning tank.

Abstract: Disclosed are relate to an apparatus for supplying a cleaning liquid to a substrate. The cleaning liquid supply unit includes a mixing container having a liquid mixing space in the interior thereof, a first supply member configured to supply a first liquid into the liquid mixing space, a second supply member configured to supply a second liquid that is different from the first liquid into the liquid mixing space, and a mixing member configured to mix the first liquid and the second liquid supplied into the liquid mixing space, and the mixing member may include a circulation line, through which the liquids in the liquid mixing space circulate, and a pressure adjusting member configured to provide a pressure to the liquids such that the liquids in the liquid mixing space flows into the circulation line and adjust the pressure.

Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.

Abstract: A temperature measuring method and system for a thin film solar cell process device are provided. The method includes: sending a temperature measuring apparatus into a feeding chamber, a heating chamber, a process chamber, a cooling chamber and a discharging chamber of the thin film solar cell process device in sequence, and measuring and storing a current temperature of each heating zone in the heating chamber, the process chamber and the cooling chamber in sequence; and comparing the current temperature with a preset temperature, and adjusting a heating temperature of a heater of each heating zone in the heating chamber, the process chamber and the cooling chamber according to a comparison result.

Abstract: An apparatus and method for real-time sensing of properties in industrial manufacturing equipment are described. The sensing system includes first plural sensors mounted within a processing environment of a semiconductor device manufacturing system, wherein each sensor is assigned to a different region to monitor a physical or chemical property of the assigned region of the manufacturing system, and a reader system having componentry configured to simultaneously and wirelessly interrogate the plural sensors. The reader system uses a single high frequency interrogation sequence that includes (1) transmitting a first request pulse signal to the first plural sensors, the first request pulse signal being associated with a first frequency band, and (2) receiving uniquely identifiable response signals from the first plural sensors that provide real-time monitoring of variations in the physical or chemical property at each assigned region of the system.

Abstract: The invention provides a beam intensity/positioning monitor substrate comprising a first metal foil in physical contact with a second metal foil.

Abstract: Embodiments include systems, devices, and methods for monitoring etch or deposition rates, or controlling an operation of a wafer fabrication process. In an embodiment, a processing tool includes a processing chamber having a liner wall around a chamber volume, and a monitoring device having a sensor exposed to the chamber volume through a hole in the liner wall. The sensor is capable of measuring, in real-time, material deposition and removal rates occurring within the chamber volume during the wafer fabrication process. The monitoring device can be moved relative to the hole in the liner wall to selectively expose either the sensor or a blank area to the chamber volume through the hole. Accordingly, the wafer fabrication process being performed in the chamber volume may be monitored by the sensor, and the sensor may be sealed off from the chamber volume during an in-situ chamber cleaning process. Other embodiments are also described and claimed.

Abstract: A substrate processing apparatus according to an embodiment includes a cassette placing section, a processing unit, a transfer area, and an image capturing unit. On the cassette placing section, a cassette accommodating a plurality of substrates is placed. The processing unit washes or etches a peripheral portion of each substrate taken out from the cassette. The transfer area is interposed between the cassette placing section and the processing unit, and the substrate is transferred therein. The image capturing unit is disposed in the transfer area to capture an image of the substrate processed by the processing unit. The image includes both of (i) a peripheral portion of an upper surface or a lower surface of the substrate and (ii) an end face of the substrate.

Abstract: A method includes dicing a wafer to form discrete components; transferring the discrete components onto a transparent carrier, including adhering the discrete component to a carrier release layer on the transparent carrier; and releasing one of the discrete components from the transparent carrier, the one of the discrete components being deposited onto a device substrate after the releasing.

Abstract: A wafer processing method includes: a protective member placing step of placing a protective member on the face side of a wafer; a shield tunnel forming step of applying a laser beam, which has a wavelength that is transmittable through single-crystal silicon, to areas of the wafer that correspond to projected dicing lines from a reverse side of the wafer, thereby successively forming a plurality of shield tunnels in the wafer, each including a fine pore extending from the reverse side to the face side of the wafer and an amorphous region surrounding the fine pore; and a dividing step of dividing the wafer into individual device chips by etching the shield tunnels according to plasma etching. The pulsed laser beam used in the shield tunnel forming step has a wavelength of 1950 nm or higher.

Abstract: An apparatus including a controller; a robot drive; a robot arm connected to the robot drive, where the robot arm has links including an upper arm, a first forearm connected to a first end of the upper arm, a second forearm connected to a second opposite end of the upper arm, a first end effector connected to the first forearm and a second end effector connected to the second forearm; and a transmission connecting the robot drive to the first and second forearms and the first and second end effectors. The transmission is configured to rotate the first and second forearms relative to the upper arm and rotate the first and second end effectors on their respective first and second forearms. The upper arm is substantially rigid and movement of the upper arm by the robot drive moves both the first and second forearms in opposite directions.

Abstract: To detach a substrate from a table without damaging the substrate. According to Embodiment 1, provided is a substrate processing apparatus including a table to hold a substrate, a plurality of lift pins that are arranged at periphery of the table and configured to arrange or separate the substrate on or from the table and to be movable in a direction perpendicular to a surface of the table, a drive mechanism that includes a motor to move the lift pins in the direction perpendicular to the surface of the table, and a control device that is configured to control the drive mechanism. The control device is configured to be capable of moving the lift pins at a first speed and at a second speed different from the first speed.

Abstract: A manufacturing method of an interconnect structure including the following steps is provided. A dielectric layer is formed on a silicon layer, wherein an opening exposing the silicon layer is in the dielectric layer. A metal layer is formed on the surface of the opening. A stress adjustment layer is formed on the metal layer. A thermal process is performed to react the metal layer with the silicon layer to form a metal silicide layer on the silicon layer. The stress adjustment layer is removed after the thermal process is performed. A barrier layer is formed on the surface of the opening.

Abstract: A method for making a semiconductor device may include forming first and second spaced apart shallow trench isolation (STI) regions in a semiconductor substrate, and forming a superlattice on the semiconductor substrate and extending between the first and second STI regions. The superlattice may include stacked groups of layers, each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming a first semiconductor stringer comprising a non-monocrystalline body at an interface between a first end of the superlattice and the first STI region, and forming a gate above the superlattice.

Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a silicon oxynitride layer having a gradient oxygen concentration.

Abstract: Disclosed is a three-dimensional semiconductor device including a horizontal semiconductor layer including a plurality of well regions having a first conductivity and a separation impurity region having a second conductivity, and a plurality of cell array structures provided on the well regions of the horizontal semiconductor layer, respectively. The separation impurity region is between and in contact with the well regions. Each of the cell array structures comprises a stack structure including a plurality of stacked electrodes in a vertical direction to a top surface of the horizontal semiconductor layer, and a plurality of vertical structures penetrating the stack structure and connected to a corresponding well region.

Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

Abstract: Implementations of a method of forming a semiconductor package may include forming a plurality of notches into a first side of a wafer, the first side of the wafer including a plurality of electrical contacts. The method may also include coating the first side of the wafer and an interior of the plurality of notches with a molding compound, grinding a second side of the wafer to thin the wafer to a desired thickness, forming a back metal on a second side of the wafer, exposing the plurality of electrical contacts through grinding a first side of the molding compound, and singulating the wafer at the plurality of notches to form a plurality of semiconductor packages.

Abstract: A method of processing a device wafer comprising applying a sacrificial material to a surface of a carrier wafer, adhering a surface of the device wafer to an opposing surface of the carrier wafer, planarizing an exposed surface of the sacrificial material by removing only a portion of a thickness thereof, and planarizing an opposing surface of the device wafer. A wafer assembly is also disclosed.

Abstract: According to one embodiment, a dicing method is provided. The dicing method includes detecting a first distance between a first portion of a substrate and a first substrate information detection unit. The method also includes detecting a second distance between a second portion of the substrate a second substrate information detection unit, the second portion different from the first portion. Distance information is calculated between the substrate and a processing lens, which is located farther from the second substrate information detection unit than from the first substrate information detection unit, based on the detected first distance and the detected second distance, and he substrate is irradiated with laser light from the processing lens based on the distance information.

Abstract: A 3D semiconductor device, the device including: a first layer including a first single crystal transistor; a second layer including second transistors; a third layer including third transistors; a fourth layer including fourth transistors, where the first layer is overlaid by the second layer, where the second layer is overlaid by the third layer, and where the third layer is overlaid by the fourth layer; where a plurality of the fourth transistors are aligned to the plurality of the first single crystal transistor with less than 40 nm alignment error, where the third transistors are junction-less transistors (JLT), where each of the fourth transistors include a transistor channel, a drain and a source, and where the transistor channel is significantly narrower than the drain or the source.

Abstract: An integrated circuit and method with dual stress liners and with NMOS transistors with gate overhang of active that is longer than the minimum design rule and with PMOS transistors with gate overhang of active that are not longer than the minimum design rule.

Abstract: In a method for manufacturing a semiconductor device, a substrate is provided. A hard mask and a mask layer are formed on a first region and a second region of the substrate. The substrate is recessed using the hard mask and the mask layer to form a fin structure in the first region and a raised structure in the second region. First isolation structures and second isolation structures are formed on lower portions of opposite sidewalls of the fin structure and opposite sidewalls of the raised structure. A first gate structure is formed on a portion of the fin structure, and a second gate structure is formed on a portion of the raised structure. A first source and a first drain are formed on opposite sides of the first gate structure, and a second source and a second drain are formed on opposite sides of the second gate structure.

Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.

Abstract: A semiconductor device including a contact structure is provided. The semiconductor device includes an isolation region defining a lower active region. First and second source/drain regions and first and second gate electrodes are on the lower active region. The first and second source/drain regions are adjacent to each other. First and second gate capping patterns are on the first and second gate electrodes, respectively. First and second contact structures are on the first and second source/drain regions, respectively. A lower insulating pattern is between the first and second source/drain regions. An upper insulating pattern is between the first and second contact structures. Silicon oxide has etching selectivity with respect to an insulating material which the upper insulating pattern, the first gate capping pattern, and the second gate capping pattern are formed of.

Abstract: In an embodiment, a method for fabricating a FinFET device includes providing a semiconductor substrate, etching the semiconductor substrate to form dummy fins and active fins. The group of dummy fins is etched through a patterned mask layer. An isolation feature is formed on the semiconductor substrate after etching the first group of dummy fins.

Abstract: A semiconductor structure includes a substrate and a CMOS structure. The CMOS structure includes a PMOS structure and a NMOS structure. The PMOS structure includes two first source/drain regions disposed in the substrate, a first gate dielectric disposed partially in the substrate between the first source/drain regions, and a fully silicided gate electrode disposed on the first gate dielectric. The NMOS structure includes two second source/drain regions disposed in the substrate, a second gate dielectric disposed partially in the substrate between the second source/drain regions, and a non-silicided conductive gate electrode disposed on the second gate dielectric.

Abstract: Embodiments of the disclosure provide a metrology system. In one example, a metrology system includes a laser source adapted to transmit a light beam, a lens adapted to receive at least a portion of the light beam from the laser source, a first beam splitter positioned to receive at least the portion of the light beam passing through the lens, a first beam displacing device adapted to cause a portion of the light beam received from the beam splitter to be split into two or more sub-light beams a first recording device having a detection surface, and a first polarizer that is positioned between the first displacing device and the first recording device, wherein the first polarizer is configured to cause the two or more sub-light beams provided from the first displacing device to form an interference pattern on the detection surface of the first recording device.

Abstract: An electronic package is provided, which includes: a first circuit structure; a plurality of first electronic elements disposed on a surface of the first circuit structure; at least a first conductive element formed on the surface of the first circuit structure; and a first encapsulant formed on the surface of the first circuit structure and encapsulating the first electronic elements and the first conductive element, with a portion of the first conductive element exposed from the first encapsulant. By directly disposing the electronic elements having high I/O functionality on the circuit structure, the present disclosure eliminates the need of a packaging substrate having a core layer, thereby reducing the thickness of the electronic package. The present disclosure further provides a method for fabricating the electronic package.

Abstract: An embodiment of the disclosure is a structure comprising an interposer. The interposer has a test structure extending along a periphery of the interposer, and at least a portion of the test structure is in a first redistribution element. The first redistribution element is on a first surface of a substrate of the interposer. The test structure is intermediate and electrically coupled to at least two probe pads.

Abstract: Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Abstract: According to the present invention, a power module includes an insulating substrate, a semiconductor device provided on the insulating substrate, an internal terminal provided on the insulating substrate and electrically connected to the semiconductor device, a sealing material that seals the internal terminal, the semiconductor device and the insulating substrate so that an end portion of the internal terminal is exposed, a case that is separate from the sealing material and covers the sealing material and an elastic member that connects the case and the end portion of the internal terminal.

Abstract: Hybrid microelectronic substrates, and related devices and methods, are disclosed herein. In some embodiments, a hybrid microelectronic substrate may include a low-density microelectronic substrate having a recess at a first surface, and a high-density microelectronic substrate disposed in the recess and coupled to a bottom of the recess via solder.

Abstract: A device includes a substrate with a die over the substrate. A molding compound surrounds the die and includes a structural interface formed along a peripheral region of the molding compound.