Abstract: An electronic package and a method of fabricating the same are provided. The method includes disposing an electronic component on a first side of an interposer, forming a first encapsulant on the first side of the interposer to encapsulate the electronic component, forming a plurality of conductive elements on a second side of the interposer, and forming a second encapsulant on the second side of the interposer to encapsulate the conductive elements. During thermal cycling of the electronic package, shrinkage forces of the first encapsulant and the second encapsulant can offset each other so as to mitigate warping of the interposer.

Abstract: A chip structure is provided. The chip structure includes: a first lower chip structure; and an upper chip structure on the first lower chip structure and having a pixel array region. The first lower chip structure includes: a first lower semiconductor substrate having a first side and a second side opposing each other; a first portion on the first side of the first lower semiconductor substrate; and a second portion on the second side of the first lower semiconductor substrate, the first portion of the first lower chip structure includes a gate wiring, the second portion of the first lower chip structure includes a second side wiring and a heating element, and the heating element is on the same plane as that of the second side wiring and has a length greater than that of the second side wiring.

Abstract: A semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a stackable semiconductor device with small size and fine pitch and a method of manufacturing thereof.

Abstract: A method for manufacturing a semiconductor package includes: (a) providing a package device, the package device comprising a substrate, a package body and a plurality of connecting elements, the substrate having a first surface, the package body being disposed adjacent to the first surface of the substrate, and the connecting elements being disposed adjacent to the first surface of the substrate and encapsulated by the package body; and (b) removing a portion of the package body along one or more machining paths to expose the connecting elements, wherein each machining path has one or more first paths passing over, between, or along a side of at least two connecting elements, wherein a portion of each of the at least two connecting elements is within the package body, and another portion of each of the at least two connecting elements protrudes from a surface of the package body.

Abstract: In an electronic device including an electronic component, a sealing resin body, a first member having at least a portion located in the sealing resin body, and a second member connected to the first member via a solder in the sealing resin body, the first member includes a base material formed of a metal material and a coated film at least on a surface of the base material which is adjacent to a back surface of the first member opposite to a facing surface of the first member facing the second member. The coated film includes a metal thin film on a surface of the base material and an uneven oxide film on the metal thin film and made of an oxide of a same metal as a main component of the metal thin film.

Abstract: The present disclosure relates to a packaging process to enhance thermal and electrical performance of a wafer-level package. The wafer-level package with enhanced performance includes a first thinned die having a first device layer, a multilayer redistribution structure, a first mold compound, and a second mold compound. The multilayer redistribution structure includes package contacts on a bottom surface of the multilayer redistribution structure and redistribution interconnects connecting the first device layer to the package contacts. The first mold compound resides over the multilayer redistribution structure and around the first thinned die, and extends beyond a top surface of the first thinned die to define a cavity within the first mold compound and over the first thinned die. The second mold compound fills the cavity and is in contact with the top surface of the first thinned die.

Abstract: In an embodiment, an assembly includes an electronic component, a fixing member, a resilient member and a substrate having a first surface. The electronic component includes a heat-generating semiconductor device, a die pad and a plastic housing. The heat-generating semiconductor device is mounted on a first surface of the die pad, and the die pad is at least partially embedded in the plastic housing. The resilient member is engaged under compression between an upper side of the electronic component and a lower surface of the fixing member and the fixing member secures the electronic component to the first surface of the substrate.

Abstract: A semiconductor package includes a substrate including an antenna; a heating element disposed on a first surface of the substrate and connected to the antenna; a heat radiating part coupled to the heating element; and a signal transfer part disposed on the first surface of the substrate and configured to electrically connect the substrate to a main substrate. The heat radiating part may include a heat transfer part connected to the heating element and heat radiating terminals connecting the heat transfer part and the main substrate to each other.

Abstract: A CNT-metal composite structure is formed by forming a plurality of CNTs which stand side by side from a base substance, forming a sheet-shaped support film which covers upper ends of the CNTs, and filling gaps each present between adjacent ones of the CNTs with a metal. By this structure, highly reliable bonding sheet and heat dissipation mechanism which are very excellent in heat dissipation efficiency, and manufacturing methods of these are realized.

Abstract: A heat dissipation sheet includes a first sheet composed of a plurality of first carbon nanotubes, and a second sheet composed of a plurality of second carbon nanotubes, wherein the first sheet and the second sheet are coupled in a stacked state, and the first carbon nanotubes and the second carbon nanotubes are different in an amount of deformation when pressure is applied.

Abstract: A component coupled to a heat dissipation unit, allowing a screwing element to be pivotally coupled to a heat dissipation unit, includes a body, a stop portion, a first inner engagement portion, a second inner engagement portion and a first outer engagement portion. The body has a first part and a second part and forms therein a through hole which extends axially. The stop portion is circumferentially disposed at the rim of the first or second part. The first inner engagement portion has checking plates and corresponds in position to the stop portion. The second inner engagement portion has stop blocks disposed at the first or second part. The first outer engagement portion is disposed at the rim of the body and opposite the stop portion. The screwing element is fixed to the heat dissipation unit temporarily but firmly, thereby preventing disintegration and disconnection during transport.

Abstract: A lead frame (4) includes an inner lead (5), an outer lead (2) connected to the inner lead (5), and a power die pad (7). A power semiconductor device (9) is bonded onto the power die pad (7). A first metal thin line (11) electrically connects the inner lead (5) and the power semiconductor device (9). Sealing resin (1) seals the inner lead (5), the power die pad (7), the power semiconductor device (9), and the first metal thin line (11). The sealing resin (1) includes an insulating section (15) directly beneath the power die pad (7). A thickness of the insulating section (15) is 1 to 4 times a maximum particle diameter of inorganic particles in the sealing resin (1). A first hollow (14) is provided on an upper surface of the sealing resin (1) directly above the power die pad (7) in a region without the first metal thin line (11) and the power semiconductor device (9).

Abstract: Modules, devices and methods of manufacturing a dual-sided module are disclosed. A dual-sided module includes a packaging substrate having an upper side, a lower side, and a ground plane, a radio-frequency circuit assembly implemented on both of the upper and lower sides of the packaging substrate and an upper overmold implemented on the upper side of the packaging substrate defining one or more openings dimensioned to expose contact pads on the upper side. The module further includes a conductive layer configured to provide shielding for a region on the upper side of the packaging substrate, a lower overmold implemented on the lower side of the packaging substrate to cover a lower portion of the radio-frequency circuit assembly, the lower overmold defining a plurality of openings, and a contact feature implemented within each of the openings of the lower overmold to be in contact with the packaging substrate.

Abstract: A semiconductor package substrate, in which a base substrate having an upper surface and a lower surface and formed of a conductive material is filled with resin formed of an insulating material, includes a die pad formed of the conductive material on the upper surface and a lead arranged on the upper surface by being electrically separated from the die pad and comprising a bonding pad that is a wire bonding area. A protrusion protruding toward the lower surface is formed in a central area of the bonding pad. A central thickness of the bonding pad is greater than a peripheral thickness of the bonding pad.

Abstract: A semiconductor package structure includes an encapsulant, a chip module, at least one auxiliary conduction block, and a redistribution layer. The chip module is encapsulated by the encapsulant. The chip module has a chip. Each of the at least one auxiliary conduction block has a plurality of auxiliary conductive bumps and a mold layer encapsulating the plurality of auxiliary conductive bumps. The redistribution layer is disposed on the encapsulant. The redistribution layer is used to electrically connect the chip of the chip module and the at least one auxiliary conduction block.

Abstract: A semiconductor structure includes a first die including a first surface and a second surface opposite to the first surface; a molding surrounding the first die; a first via extended through the molding; an interconnect structure including a dielectric layer and a conductive member, wherein the dielectric layer is disposed below the first surface of the first die and the molding, and the conductive member is disposed within the dielectric layer; and a second die disposed over the molding, wherein the second die is electrically connected to the first via.

Abstract: A method for forming a package structure may comprise applying a die and vias on a carrier having an adhesive layer and forming a molded substrate over the carrier and around the vias, and the ends of the vias and mounts on the die exposed. The vias may be in via chips with one or more dielectric layers separating the vias. The via chips 104 may be formed separately from the carrier. The dielectric layer of the via chips may separate the vias from, and comprise a material different than, the molded substrate. An RDL having RDL contact pads and conductive lines may be formed on the molded substrate. A second structure having at least one die may be mounted on the opposite side of the molded substrate, the die on the second structure in electrical communication with at least one RDL contact pad.

Abstract: A redistribution layer structure of the semiconductor package includes a dielectric layer having a thickness, at least one upper conductive wire disposed on a first surface of the dielectric layer, at least one lower conductive wire disposed on a second surface of the dielectric layer, and vias penetrating the dielectric layer and connecting the at least one upper conductive wire and the at least one lower conductive wire. Each via has a cross-section at one upper conductive wire. The cross-section has a third width. The ratio of the third width to the thickness of the dielectric layer is less than or equal to 1. The ratio of the pitch between every two adjacent vias to the third width is greater than or equal to 0.5.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes a first interlayer dielectric (ILD) layer disposed on a semiconductor substrate. A metal pad is disposed in the first ILD layer. A contact self-alignment structure is disposed on the first ILD layer. The contact self-alignment structure has an opening that is disposed directly above the metal pad. A second interlayer dielectric (ILD) layer is disposed on the first ILD layer. A contact plug penetrates through the second ILD layer and is electrically connected to the metal pad via the opening of the contact self-alignment structure.

Abstract: A transmissive composite film is described that may be applied to the backside of a microelectronic device, for example an integrated circuit die or a bridge. A microelectronic die package in one example has a substrate, an integrated circuit die attached and electrically connected to the substrate, the die having a front side with electrical attachments and a backside, and a composite film attached to a backside of the die, the composite film having a polymer base with nano-fillers to protect the backside of the die.

Abstract: A hybrid microelectronic substrate may be formed by the incorporation of a high density microelectronic patch substrate within a lower density microelectronic substrate. The hybrid microelectronic substrate may allow for direct flip chip attachment of a microelectronic device having high density interconnections to the high density microelectronic patch substrate portion of the hybrid microelectronic substrate, while allowing for lower density interconnection and electrical routes in areas where high density interconnections are not required.

Abstract: A chip on glass package assembly includes a glass substrate, a first type chip, a second type chip and a plurality of connecting lines. The glass substrate includes an active area and a peripheral area connected to the active area. The first type chip is mounted on the peripheral area and including a processor. The second type chip is mounted on the peripheral area and located on a side of the first type chip, wherein the second type chip is different from the first type chip. The connecting lines are disposed on the peripheral area and connecting the first type chip and the second type chip.

Abstract: A method of manufacturing a semiconductor device includes forming a first photoresist film over a substrate, exposing a first pattern including an alignment pattern in a first region, forming, on the substrate, an alignment mark corresponding to the exposed alignment pattern, forming a second photoresist film over the substrate on which the alignment mark is formed, dividing a second pattern into a plurality of regions and exposing the divided regions separately in a second region while performing positioning with respect to the alignment mark, and developing the second photoresist film and forming the second photoresist film having the second pattern, wherein at least a part of the second region is located outside an effective exposure region of an exposure apparatus in exposure of the first pattern.

Abstract: Disclosed herein are stairstep interposers with integrated conductive shields, and related assemblies and techniques. In some embodiments, an interposer may include: an insulating material having a stairstep structure with a first step surface, a second step surface, and a bottom surface to face a package substrate, wherein a first thickness of the insulating material between the first step surface and the bottom surface is greater than a second thickness of the insulating material between the second step surface and the bottom surface; a conductive signal pathway extending from the first step surface to the bottom surface; and a conductive shield disposed within the insulating material to shield the conductive signal pathway.

Abstract: An integrated shield electronic component package includes a substrate having as upper surface, a lower surface, and sides extending between the upper surface and the lower surface. An electronic component is mounted to the upper surface of the substrate. An integrated shield is mounted to the upper surface of the substrate and includes a side shielding portion directly adjacent to and covering the sides of the substrate. The integrated shield covers and provides an electromagnetic interference (EMI) shield for the electronic component, the upper surface and sides of substrate. Further, the integrated shield is integrated within toe integrated shield electronic package. Thus, separate operations of mounting an electronic component package and then mounting a shield are avoided thus simplifying manufacturing and reducing overall assembly costs.

Abstract: In a described example, an integrated circuit includes: a semiconductor substrate having a first surface and an opposite second surface; at least one dielectric layer overlying the first surface of the semiconductor substrate; at least one inductor coil in the at least one dielectric layer with a plurality of coil windings separated by coil spaces, the at least one inductor coil lying in a plane oriented in a first direction parallel to the first surface of the semiconductor substrate, the at least one inductor coil electrically isolated from the semiconductor substrate by a portion of the at least one dielectric layer; and trenches extending into the semiconductor substrate in a second direction at an angle with respect to the first direction, the trenches underlying the inductor coil and filled with dielectric replacement material.

Abstract: A semiconductor package device comprises a substrate, a die, an encapsulant and an antenna layer. The substrate has a top surface and a bottom surface opposite to the top surface. The die is disposed on the top surface of the substrate. The encapsulant is disposed on the top surface of the substrate and surrounds the die. The encapsulant has a top surface and defines a recess on the top surface of the encapsulant. The antenna layer is disposed on the top surface of the encapsulant and extends within the recess on the top surface of the encapsulant.

Abstract: A fan-out semiconductor package includes: a core member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the core member and the semiconductor chip; and a connection member disposed on the core member and an active surface of the semiconductor chip and including a redistribution layer connected to the connection pads. The core member includes a plurality of wiring layers disposed on different levels, a dielectric is disposed between the plurality of wiring layers of the core member, one of the plurality of wiring layers includes an antenna pattern, the other of the plurality of wiring layers includes a ground pattern, and the antenna pattern is connected to the connection pads through the redistribution layer in a signal manner.

Abstract: The present invention relates to a transition arrangement (100) comprising a transition between a substrate integrated waveguide, SIW, (20) of a circuit arrangement and a waveguide and/or antenna structure (10). It comprises a first conducting plate (1) and a second conducting plate (2). The SIW (20) is arranged on said first conducting plate, and an impedance matching structure (4) is connected to the second conducting plate.

Abstract: An integrated circuit structure includes a metal pad, a passivation layer including a portion over the metal pad, a first polymer layer over the passivation layer, and a first Post-Passivation Interconnect (PPI) extending into to the first polymer layer. The first PPI is electrically connected to the metal pad. A dummy metal pad is located in the first polymer layer. A second polymer layer is overlying the first polymer layer, the dummy metal pad, and the first PPI. An Under-Bump-Metallurgy (UBM) extends into the second polymer layer to electrically couple to the dummy metal pad.

Abstract: Implementations of semiconductor packages may include: a semiconductor die having a first side and a second side; one or more bumps included on the first side of the wafer, the bumps comprising a first layer having a first metal and a second layer including a second metal. The first layer may have a first thickness and the second layer may have a second thickness. The semiconductor package may also have a mold compound encapsulating all the semiconductor die except for a face of the one or more bumps.

Abstract: A chip package structure includes a chip package layer and at least one conductive structure layer. The chip package layer includes at least one chip and an encapsulant. The chip has an upper surface, and the encapsulant is used to encapsulate the chip and expose the upper surface. The conductive structure layer includes a plurality of first conductive pillars and a plurality of second conductive pillars. The first conductive pillars are disposed on the upper surface, the second conductive pillars are disposed on the upper surface and located between an edge of the upper surface and the first conductive pillars. A density of the second conductive pillars along an extending direction of the edge is greater than or equal to 1.2 times of a density of the first conductive pillars along the extending direction of the edge.

Abstract: A semiconductor package can include a mold substrate having opposite first and second surfaces where a semiconductor chip can be embedded inside the mold substrate. The semiconductor chip can include chip pads where a redistribution layer can be on the first surface of the mold substrate, and the redistribution layer can include redistribution lines therein electrically connected to the chip pads and can include a capacitor redistribution line. A capacitor can include a first electrode including a plurality of conductive pillars connected to the capacitor redistribution line. A dielectric layer can be on the first electrode and a second electrode can be on the dielectric layer.

Abstract: An embodiment includes an apparatus comprising: a first device layer included in a top edge of a semiconductor substrate; metal layers, on the first device layer, including first and second metal layers; a second device layer on the metal layers; and additional metal layers on the second device layer; wherein the second device layer is not included in any semiconductor substrate. Other embodiments are described herein.

Abstract: A semiconductor device manufacturing method includes: applying solder to an arrangement area of a substrate, the substrate having a connection area to which a wiring member is to be directly connected, the connection area neighboring the arrangement area; arranging a component on the arrangement area via the solder; and soldering the component to the arrangement area by heating the solder while covering the connection area. A soldering support jig includes a columnar covering member having a covering surface at a bottom of the columnar covering member.

Abstract: A stack type sensor package structure includes a substrate, a semiconductor chip disposed on the substrate, a frame disposed on the substrate and aside the semiconductor chip, a sensor chip disposed on the frame, a plurality of wires electrically connecting the sensor chip and the substrate, a transparent layer being of its position corresponding to the sensor chip, a support maintaining the relative position between the sensor chip and the transparent layer, and a package compound disposed on the substrate and partially covering the frame, the support, and the transparent layer. Thus, through disposing a frame within the stack type sensor package structure, the structural strength of the overall sensor package structure is reinforced, and the stability of the wiring of the sensor chip is effectively increased.

Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.

Abstract: A light emitter device includes a submount with a top surface and a bottom surface, electrically conductive traces on the top surface of the submount, light emitting diodes (LEDs) arranged on the top surface of the submount in light emitter zones, with the LEDs being electrically connected to respective traces of the traces, a retention material disposed over the top surface of the submount in a form of walls which physically separate the light emitter zones, and encapsulants that are dispensed in respective light emitter zones of the light emitter zones. The LEDs are individually addressable to independently control an output of light from each of the LEDs to produce a specified light output.

Abstract: A video wall module includes a plurality of light emitting diode chips, each including first contact electrodes and second contact electrodes arranged at a contact side, wherein the light emitting diode chips are arranged at a top side of a multilayer circuit board, and the contact electrodes electrically conductively connect to a first metallization layer arranged at the top side of the circuit board.

Abstract: An electronic module comprising a first electronic unit 51 which has a first insulating substrate 61 and a first electronic element 41 provided on the first insulating substrate 61 via a first conductor layer 21, a second electronic unit 52 which has a second insulating substrate 62 and a second electronic element 42 provided on the second insulating substrate 62 via a second conductor layer 22, a connecting body 29 provided between the first electronic unit 51 and the second electronic unit 52 and a coil 70 wound around the connecting body 29.

Abstract: There is disclosed a transparent light field display device including a transparent substrate, an array of light-emitting picture elements formed on the transparent substrate, and a sparse microlens array formed over the array of light-emitting picture elements. The sparse microlens array includes a plurality of lens elements with spaces between adjacent lens elements. When the transparent light field display device is disposed with the sparse microlens array proximate a viewer's eye, the spaces between adjacent lens elements allow the viewer to see objects beyond the transparent light field display device.

Abstract: An optoelectronic apparatus is provided having a carrier device that has at least one optoelectronic transmitter and/or at least one optoelectronic receiver at an upper side; at least one first optical element, a second optical element, and a third optical element that are arranged in a layer arrangement above the carrier device, with the second optical element being arranged above the first optical element and the third optical element being arranged above the second optical element, and with each of the at least three optical elements comprising a lens element, an aperture element or a filter element; and a holding device that holds at least the first optical element and the second optical element relative to the carrier device and partly surrounds them, with the holding device furthermore either holding the third optical element relative to the carrier device and partly surrounding the third optical element or forming the third optical element.

Abstract: A semiconductor device, the device including: a first level of logic circuits, the logic circuits include a plurality of first transistors interconnected by a plurality of metal layers; a thermal isolation layer overlaying the first level; a second level of memory circuits, the memory circuits include an array of memory cells, where the second level is overlaying the thermal isolation layer; and connections from the logic circuits to the memory array including vias, where the vias have a diameter of less than 400 nm, and where a majority of the thermal isolation layer includes a material with a less than 0.5 W/m·K thermal conductivity.

Abstract: Disclosed is a semiconductor device having an e1ectrostatic discharge protection structure. The e1ectrostatic discharge protection structure is a diode connected between a gate e1ectrode and a source e1ectrode of the semiconductor device. The diode comprises a diode body and two connection portions connected to two ends of the diode body and respectively used for electrically connecting to the gate e1ectrode and the source e1ectrode. Lower parts of the two connection portions are respective1y provided with a trench. An insulation 1ayer is provided on an inner surface of the trench and the surface of a substrate between trenches. The diode body is provided on the insu1ation 1ayer on the surface of the substrate. The connection portions respectively extend downwards into respective trenches from one end of the diode body. A dielectric layer is provided on the diode, and a meta1 conductor 1ayer is provided on the dielectric layer.

Abstract: A method of forming a LDMOS with a self-aligned P+ implant and LVPW region at the source side and the resulting device are provided. Embodiments include forming a DNWELL in a p-sub; forming a PWHV in the DNWELL; forming an NW in the DNWELL; forming a LVPW in the PWHV; forming STI structures through the LVPW and through the DNWELL and NW, respectively; forming a gate over the PWHV; forming a first and a second P+ implant in the LVPW, an edge of the second P+ implant aligned with an edge of the gate; forming a first N+ implant in the LVPW between the first STI structure and the second P+ implant and a second N+ in the NW adjacent to the second STI structure; and forming contacts over the first and second P+ and N+ implants, respectively, and an electrical contact over the second N+ implant.

Abstract: A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.

Abstract: An electronic chip is provided that includes a plurality of first transistors electrically coupled to one another in parallel. A plurality of first isolating trenches is included in the electronic chip, and the first transistors are separated from one another by the first isolating trenches. Each of the first isolation trenches has a depth and a maximum width, and the depth depends on, or is a function of, the maximum width.

Abstract: An exemplary semiconductor device includes first spacers disposed along sidewalls of a first gate structure and second spacers disposed along sidewalls of a second gate structure. A source/drain region is disposed between the first gate structure and the second gate structure. A first ILD layer is disposed between the first spacers and the second spacers. A portion of the first ILD layer has a first recessed upper surface. A dielectric layer is disposed over the first spacers, the second spacers, and the first recessed upper surface of the first ILD layer. A portion of the dielectric layer has a second recessed upper surface that is disposed over the portion of the first ILD layer having the first recessed upper surface. A second ILD layer is disposed over the dielectric layer. A contact extends through the second ILD layer, the dielectric layer, and the first ILD layer to the source/drain region.

Abstract: A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain structure and a source structure is provided. The fin structure is disposed to extend on the semiconductor substrate between two insulating areas. The gate dielectric layer is disposed to extend across two sides of the fin structure. The gate electrode structure is disposed on the gate dielectric layer. The drain structure is disposed at a first side of the gate electrode structure and has a first resistance relative to the gate electrode. The source structure is disposed at a second side of the gate electrode structure and has a second resistance relative to the gate electrode. The first resistance is larger than the second resistance.

Abstract: A semiconductor device includes: a substrate including a field region that defines an active region; source/drain regions in the active region; a channel region between the source/drain regions; a lightly doped drain (LDD) region between one of the source/drain regions and the channel region; and a gate structure disposed on the channel region. An upper portion of the active region may include an epitaxial growth layer having a larger lattice constant than silicon (Si), and the source/drain regions and the LDD region may be doped with gallium (Ga).