Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for presenting notifications in an enterprise system. In one aspect, a method include actions of obtaining enrollment acoustic data representing an enrollment utterance spoken by a user, obtaining a set of candidate acoustic data representing utterances spoken by other users, determining, for each candidate acoustic data of the set of candidate acoustic data, a similarity score that represents a similarity between the enrollment acoustic data and the candidate acoustic data, selecting a subset of candidate acoustic data from the set of candidate acoustic data based at least on the similarity scores, generating a detection model based on the subset of candidate acoustic data, and providing the detection model for use in detecting an utterance spoken by the user.

Abstract: The techniques disclosed herein provide apparatuses and related methods for the communication of spatial audio and related metadata. In some implementations, a source provides prerecorded spatial audio that has embedded metadata. A computing device processes the prerecorded spatial audio to generate an audio codec that is segmented to include a first section of audio data and a second section that includes metadata extracted from the prerecorded spatial audio. The generated audio codec may be received by a device that includes an encoder. The encoder may process the generated audio codec to generate audio data that includes the metadata.

Abstract: An apparatus for encoding a multi-channel signal having at least two channels is provided. The apparatus includes a time-spectral converter, converting sequences of blocks of sample values of the two channels into a frequency domain representation having sequences of blocks of spectral values for the two channels, a block of sampling values having an associated input sampling rate, a block of spectral values of the sequences of blocks that has spectral values up to a maximum input frequency related to the input sampling rate; a multi-channel processor to obtain a result sequence of blocks of spectral values having information related to the two channels; a spectral domain resampler to obtain a resampled sequence of blocks of spectral values; a spectral-time converter for converting the resampled sequence of blocks into a time domain representation; and a core encoder for encoding the output sequence of blocks to obtain an encoded multi-channel signal.

Abstract: A device includes a receiver and a decoder. The receiver is configured to receive bitstream parameters corresponding to at least an encoded mid signal. The decoder is configured to generate a synthesized mid signal based on the bitstream parameters. The decoder is also configured to generate a synthesized side signal selectively based on the bitstream parameters in response to determining whether the bitstream parameters correspond to an encoded side signal.

Abstract: An apparatus and a method to encode and decode a speech signal using an encoding mode are provided. An encoding apparatus may select an encoding mode of a frame included in an input speech signal, and encode a frame having an unvoiced mode for an unvoiced speech as the selected encoding mode.

Abstract: In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for formatting a payload for transmission of multi-mode speech/audio codec data. The method comprises deciding whether a header-less or a header-full payload format is used for transmission of a coded frame. The decision is based on a codec mode and a required functionality. The payload data is packetized with or without the payload header depending on the decision.

Abstract: A phone stand includes a phone holder for coupling to a phone conducting a voice session, a plurality of directional speakers positioned to project sound to a focused audio area corresponding to a location where a user is expected to be positioned, other speaker(s), and a system controller. The system controller is configured to receive audio signals of the voice session from the phone, separate the audio signals into speech signals and non-speech signals, obtain output mixing attributes, generate mixed signals by combining the speech signals and the non-speech signals according to the output mixing attributes, and send the mixed signals to the plurality of directional speakers. The other speaker(s) can include non-directional speakers, and the system controller is further configured to send the speech signals in the mixed signals to the plurality of directional speakers and the non-speech signals in the mixed signals to the other speaker(s).

Abstract: A method for speech enhancement, the method may include receiving or generating sound samples that represent sound signals that were received during a given time period by an array of microphones; frequency transforming the sound samples to provide frequency-transformed samples; clustering the frequency-transformed samples to speakers to provide speaker related clusters, wherein the clustering is based on (i) spatial cues related to the received sound signals and (ii) acoustic cues related to the speakers; determining a relative transfer function for each speaker of the speakers to provide speakers related relative transfer functions; applying a multiple input multiple output (MIMO) beamforming operation on the speakers related relative transfer functions to provide beamformed signals; and inverse-frequency transforming the beamformed signals to provide speech signals.

Abstract: Signals are received from audio pickup channels that contain signals from multiple sound sources. The audio pickup channels may include one or more microphones and one or more accelerometers. Signals representative of multiple sound sources are generated using a blind source separation algorithm. It is then determined which of those signals is deemed to be a voice signal and which is deemed to be a noise signal. The output noise signal may be scaled to match a level of the output voice signal, and a clean speech signal is generated based on the output voice signal and the scaled noise signal. Other aspects are described.

Abstract: An audio processing apparatus includes a transform unit that transforms time series audio data obtained from first and second microphones into first and second frequency spectrum data; a driving noise computation processing unit that computes a subtraction amount of the driving noise for each of frequencies from the first and second frequency spectrum data obtained by the transform unit; a generating unit that, on the basis of the first and the second frequency spectrum data obtained by the transform unit and the driving noise subtraction amount obtained by the driving noise computation processing unit, generates left and right channel frequency spectrum data in which the driving noise is respectively suppressed; and an inverse transform unit that inverse-transforms the left and right channel frequency spectrum data generated by the generating unit into left and right channel time series audio data, respectively.

Abstract: A head-mounted wearable device incorporates a transducer that operates as a bone conduction (BC) microphone. Vibrations from a user's speech are transferred through the head of the user to the BC microphone. An air conduction (AC) microphone detects sound transferred via air. Signals from the BC microphone and the AC microphone are compared to determine if a common signal is present in both. For example, both signals may have a cross-correlation that exceeds a threshold value. Based on the comparison, voice activity data is generated that indicates the user wearing the device is speaking.

Abstract: According to some embodiments, an analog processing portion may receive an audio signal from a microphone. The analog processing portion may then convert the audio signal into sub-band signals and estimate an energy statistic value, such as a Signal-to-Noise Ratio (“SNR”) value, for each sub-band signal. A classification element may classify the estimated energy statistic values with analog processing such that a wakeup signal is generated when voice activity is detected. The wakeup signal may be associated with, for example, a battery-powered, always-listening audio application.

Abstract: A magnetic-disk glass substrate has a circular center hole a pair of main surfaces and an edge surface. The edge surface has a side wall surface and chamfered surfaces interposed between the side wall surface and the main surfaces, and a roundness of an edge surface on an outer circumferential side is 1.5 ?m or less. Also, a midpoint A between centers of two least square circle respectively derived from outlines in a circumferential direction respectively obtained at two positions spaced apart by 200 ?m in a substrate thickness direction on the side wall surface on the outer circumferential side, and centers B and C respectively derived from a respective one of two chamfered surfaces on the outer circumferential side in the substrate thickness direction, are located such that a sum of respective distances between A and B, and A and C, is 1 ?m or less.

Abstract: The metal oxide particle dispersion for manufacturing a particulate magnetic recording medium contains metal oxide particles, solvent, and a polyester compound having one or more groups selected from the group consisting of a carboxyl group and a salt thereof, a phosphoric acid group and a salt thereof, a hydroxyl group and a nitrogen-substituted alkylene group, but substantially not containing ferromagnetic powder.

Abstract: A data object has a lock and a condition indicator associated with it. Based at least partly on detecting a first setting of the condition indicator, a reader stores an indication that the reader has obtained read access to the data object in an element of a readers structure and reads the data object without acquiring the lock. A writer detects the first setting and replaces it with a second setting, indicating that the lock is to be acquired by readers before reading the data object. Prior to performing a write on the data object, the writer verifies that one or more elements of the readers structure have been cleared.

Abstract: It is possible to accurately and securely execute conversion from an MPEG-2TS format to an MP4 format. A data converting unit that executes format conversion from an MPEG-2TS format to an MP4 format sorts out TS packets storing video data from MPEG-2TS format data, selects a TS packet having a start code (SC) at the top of a payload on the basis of header information of the sorted out TS packets, and extracts payload configuration data other than the start code (SC) and sets the payload configuration data as configuration data of MP4 format data. The data converting unit determines, on the basis of, for example, a value of a transport priority set in a header of the TS packet, whether or not the TS packet is a TS packet in which a start code (SC) is set in a top region of a payload.

Abstract: A system for creating an output comprises a processing unit, a user input module operably connected to the processing unit, and a video monitor operably connected to the processing unit. The processing unit provides on the video monitor: a grid image comprising multiple cells, each cell representing a duration of time; and a selection area comprising multiple select icons, each select icon representing a source data file. The processing unit is configured such that a user can create a grid layout representing the correlation between individual selected source data files and one or more of the multiple cells. The processing unit produces the output based on the correlation.

Abstract: Techniques are provided for video summarization, based on speaker segmentation and clustering, to identify persons and scenes of interest. A methodology implementing the techniques according to an embodiment includes extracting audio content from a video stream and detecting one or more segments of the audio content that include the voice of a single speaker. The method also includes grouping the one or more detected segments into an audio cluster associated with the single speaker and providing a portion of the audio cluster to a user. The method further includes receiving an indication from the user that the single speaker is a person of interest. Segments of interest are then extracted from the video stream, where each segment of interest is associated with a scene that includes the person of interest. The extracted segments of interest are then combined into a summarization video.

Abstract: A method for synchronizing an audio track that is being recorded at a first location with a video track that is being recorded at a second location, such as on a flying UAV, is disclosed. First, the audio and video recorders being to record sound and video. Then, a GPS receive is used to pick up the very accurate GPS clock signal. A real-time clock is also used locally to generate a real-time value. At a predetermined time, the GPS time data is interrogated and a time-stamp is generated. A video encoder is then used to embed the time-stamp, either during recording, or shortly thereafter. A networked audio recording device records audio with a time stamp acquired from the network. These respective time-stamps are then used in post-processing to accurately synchronize the audio and video tracks.

Abstract: At least one video stream that is encoded video information, and a management information file indicating attributes relating to the entire recording medium, are recorded in a recording medium. The management information file includes attribute information indicating whether the dynamic range of luminance of an initial video stream, which is played first out of the at least one video stream when the recording medium is inserted into a playback device, is a first dynamic range, or a second dynamic range that is broader than the first dynamic range.

Abstract: At least one video stream that is encoded video information, and a management information file indicating attributes relating to the entire recording medium, are recorded in a recording medium. The management information file includes attribute information indicating whether the dynamic range of luminance of an initial video stream, which is played first out of the at least one video stream when the recording medium is inserted into a playback device, is a first dynamic range, or a second dynamic range that is broader than the first dynamic range.

Abstract: Provided is an information processing system, including a moving image data acquiring unit that acquires moving image data, a communication unit that receives sensor data associated with the moving image data and chronological data corresponding to a shooting time of the moving image data, an image signal processing unit that performs image analysis on the moving image data and generate image analysis result data, and a control unit that generates an interface including the moving image data and graphs of at least two pieces of data among the sensor data, the chronological data, and the image analysis result data.

Abstract: The present disclosure provides a hard disk assembly device for assembling a hard disk into a case. Two opposite sides of the hard disk respectively have at least one first positioning portion and at least one second positioning portion. The hard disk assembly device includes a flexible fixing frame and a fixing bracket. One side of the flexible fixing frame includes at least one third positioning portion and at least one first guiding portion, and the other side of the flexible fixing frame includes at least one fourth positioning portion, a draw tape, and two fastening portions. The two fastening portions are respectively correspondingly connected with two ends of the draw tape. The hard disk is fixed in the flexible fixing frame. The flexible fixing frame is fixed to the fixing bracket.

Abstract: According to one embodiment, a magnetic disk device includes a rotatable disk-shaped recording medium, a head which processes data on the recording medium and a housing including a base accommodating the recording medium and the head and a cover including a welded portion laser-welded to the base. The welded portion includes a first welded portion welded by a first weld width and a second welded portion welded by a second weld width greater than the first weld width.

Abstract: Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies.

Abstract: A latching current sensing amplifier circuit for memory arrays and a current sensing technique using the latching current sensing amplifier circuit are provided. The current sense-amplifier circuit includes a first and second pair of series connected transistors configured with a common gate node for a sense operation and reconfigurable as a cross-coupled pair for a latching operation.

Abstract: A semiconductor device includes a data detection circuit configured to detect a number of bits having a predetermined logic level among bits included in data to generate a detection signal. The semiconductor device also includes a selection/transmission circuit configured to output the detection signal or a control data signal as a pre-masking signal based on a selection/transmission signal. The semiconductor device further includes a masking signal generation circuit configured to latch the pre-masking signal based on a pipe input control signal and configured to output the latched signal of the pre-masking signal as a masking signal for controlling a data masking operation based on a pipe output control signal.

Abstract: Systems and methods of synchronous memories and synchronous memory operation are disclosed. According to one illustrative implementation, a memory device is disclosed comprising memory circuitry having a memory output, the memory circuitry including a sense amplifier having a first output and a second output, a first data path coupled to the first output of the sense amplifier, the first data path including 2 latches/registers, and a second data path coupled to the second output of the sense amplifier, the second data path including a plurality latches/registers. In further implementations, various control circuitry, connections and control signals may be utilized to operate the latches/registers in the first and second data paths according to specified configurations, control, modes, latency and/or timing domain information, to achieve, for example, pipelined output latching and/or double data rate output.

Abstract: A semiconductor device includes a read mode signal generation circuit and a read alignment circuit. The read mode signal generation circuit compares a read command with at least one of internal clock signal to generate a read mode signal. The read alignment circuit is synchronized with the at least one internal clock signal to generate read data in response to internal data. The read alignment circuit controls an alignment sequence of the internal data in response to the read mode signal.

Abstract: A die includes a plurality of memory cells. The die also includes a calculation circuit configured to determine a difference between a write temperature and a read temperature in response to a read request for user data stored in the memory cells. The die further includes a notification circuit configured to signal a cross-temperature condition in response to the difference satisfying a threshold.

Abstract: The present disclosure includes apparatuses and methods related to performing logical operations using sensing circuitry. An example apparatus comprises an array of memory cells and sensing circuitry comprising a primary latch coupled to a sense line of the array. The sensing circuitry can be configured to perform a first operation phase of a logical operation by sensing a memory cell coupled to the sense line, perform a number of intermediate operation phases of the logical operation by sensing a respective number of different memory cells coupled to the sense line, and accumulate a result of the first operation phase and the number of intermediate operation phases in a secondary latch coupled to the primary latch without performing a sense line address access.

Abstract: A semiconductor integrated circuit includes a register, a detection circuit, and a generation circuit. The register stores a detection start timing of a reference delay amount based on a first clock during a first period. The first period is a period in which the first clock starts to be input. The detection circuit has a plurality of delay stages. The detection circuit detects the reference delay amount at the start timing during the first period and obtains the number of delay stages corresponding to the reference delay amount. The generation circuit adjusts a duty ratio of the first clock based on the number of delay stages obtained by the detection circuit and generates a second clock during a second period. The second period is a period continuing from the first period.

Abstract: Various implementations described herein refer to an integrated circuit having level shifting circuitry and bypass switching circuitry. The level shifting circuitry is arranged for translating an input signal from a first voltage domain to an output signal for a second voltage domain. The bypass switching circuitry is arranged for activating and deactivating the level shifting circuitry based on a bypass control signal.

Abstract: Memory devices and methods include receiving data at an input buffer and outputting serial data. The serial shift data is passed toward a serial shift register that shifts its stored data into a data write bus in a parallel format. Serial shift register loading circuitry controls loading of a serial shift register. The serial shift register loading circuitry is configured to receive a data strobe signal and provide the data strobe to the serial shift register to cause the serial shift register to shift in the serial data during a write operation. The serial register loading circuitry includes gating circuitry that is configured to cutoff provision of the data strobe from the serial register loading circuitry based at least in part on a load signal that indicates that the data write bus has been loaded with the serial data in a parallel format.

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.

Abstract: Provided is a method of operating a controller to control an operation of a semiconductor memory device. The method includes: determining a minimum pass tapped delay of the semiconductor memory device based on a first offset; determining a maximum pass tapped delay of the semiconductor memory device based on a second offset; and determining a tapped delay of the semiconductor memory device based on the determined minimum pass tapped delay and the determined maximum pass tapped delay.

Abstract: The present disclosure is directed to exemplary methods of manufacturing a magnetoresistive device. In one aspect, a method may include forming one or more regions of a magnetoresistive stack on a substrate, wherein the substrate includes at least one electronic device. The method also may include performing a sole annealing process on the substrate having the one or more magnetoresistive regions formed thereon, wherein the sole annealing process is performed at a first minimum temperature. Subsequent to performing the sole annealing process, the method may include patterning or etching at least a portion of the magnetoresistive stack. Moreover, subsequent to the step of patterning or etching the portion of the magnetoresistive stack, the method may include performing all additional processing on the substrate at a second temperature below the first minimum temperature.

Abstract: According to one embodiment, a semiconductor storage device includes: a first conductor coupled to a first end of a first cell; a second conductor which couples between a second end of the first cell and a first end of a second cell; a third conductor coupled to a second end of the second cell; a first current source being capable of coupling to the first cell via the first conductor; a second current source being capable of coupling to the second cell via the third conductor; a first sense amplifier configured to read data from the first cell based on a current flowing from the first current source to the first cell; and a second sense amplifier configured to read data from the second cell based on a current flowing from the second cell to the second current source.

Abstract: A memory device includes a memory cell array that includes memory cells, a row decoder that is connected with the memory cell array through word lines, a column decoder that is connected with the memory cell array through bit lines and source lines, and a write driver that outputs a write voltage in a write operation. The column decoder includes switches, which are respectively connected to the bit lines and are respectively connected to the source lines. During the write operation, a selected switch of the switches transfers the write voltage to a selected bit line of the bit lines. Each unselected switch of the switches electrically separates the write driver from a corresponding unselected bit line of the bit lines by using the write voltage.

Abstract: An electronic device including a memory functional block having multiple ranks of memory and a memory controller functional block coupled to the memory. The memory controller includes refresh logic that detects, based on buffered memory accesses for each rank of memory of the ranks of memory, two or more ranks of memory for which a refresh is to be performed during a refresh interval. Based at least in part on one or more properties of buffered memory accesses for the two or more ranks of memory, the refresh logic determines a refresh order for performing refreshes for the two or more ranks of memory during the refresh interval. The memory controller then performs, in the refresh order, refreshes for the two or more ranks of memory during the refresh interval.

Abstract: A memory device includes a first switch for switching a first power voltage and transmitting the first power voltage to a common node of a first power rail. A second switch switches a second power voltage and transmits the second power voltage to the common node. A control logic generates a first control signal for controlling the first switch during initial driving of the memory device. A masking circuit controls the first switch to maintain a turn on state in at least a partial period of the initial driving period of the memory device by providing a first masking control signal obtained by masking the first control signal to the first switch.

Abstract: Disclosed is a memory device which includes a first memory cell connected to a word line and a first bit line, a second memory cell connected to the word line and a second bit line, and a row decoder selecting the word line, a row decoder configured to select the word line, and a column decoder. A first distance between the row decoder and the first memory cell is shorter than a second distance between the row decoder and the second memory cell. The column decoder selects the first bit line based on a time point when the first memory cell is activated.

Abstract: Devices and methods include, for a memory device, generating a main input-output line signal on a main input-output line using driving circuitry. The main input-output line is coupled to multiple sensing amplifiers. Each of the sensing amplifiers each locally generate a local data line from the main data line. Each of the sensing amplifiers also includes multiple local sensing amplifiers that are selectively coupled to the generated local data line for overwriting data in the respective local sensing amplifiers.

Abstract: Techniques are provided for sensing a memory cell configured to store three or more states. A charge may be transferred between a digit line and a node coupled with a sense component using a charge transfer device. During a single read operation, multiple voltages may be applied to the gate of the charge transfer device. The node may be sensed a number of times based on a number of voltages applied to the gate of the charge transfer device. The charge may be transferred by the charge transfer device based on a value of the signal on a digit line and a voltage applied to the gate of the charge transfer device. Based on the charge being transferred and the sense component sensing the node multiple times, a logic state associated with the memory cell may be determined.

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.

Abstract: Some embodiments include a memory array having a series of bitlines. Each of the bitlines has a first comparative bitline component and a second comparative bitline component. The bitlines define columns of the memory array. Memory cells are along the columns of the memory array. Capacitive units are along the columns of the memory array and are interspersed amongst the memory cells. The capacitive units are not utilized for data storage during operation of the memory array, but rather are utilized for reducing parasitic capacitance between adjacent bitlines.

Abstract: Systems, apparatuses, and methods for efficiently driving level shifted write data are described. In various embodiments, a level-shifting write driver combines a write data bit and a write mask bit that each use a first supply voltage to indicate a logic high level. During a write operation, the driver generates complementary values on two output nodes based on the write data bit. The output nodes use a second supply voltage greater than the first supply voltage. Before a write operation, the driver precharges each of the two output nodes to the second supply voltage. When the write clock enables a write operation and the write mask bit disables the write operation, the level-shifting write driver puts the two output nodes in a tri-state.

Abstract: An apparatus is provided that includes a plurality of memory cells, a programming circuit configured to apply a plurality of programming pulses to the memory cells, and a scanning circuit configured to repeatedly switch between performing an n-state bitscan after each programming pulse until first predetermined criteria are satisfied, and performing an m-state bitscan after each programming pulse until second predetermined criteria are satisfied, where m>n, and n>0.

Abstract: A resistance variable memory apparatus includes a memory cell array region and a peripheral region disposed along an edge of the memory cell region. The memory cell array region may have a plurality of memory banks each of which includes at least one memory block. The resistance variable memory apparatus may include a data transmission block transmitting data between the plurality of memory banks and the peripheral region. The data transmission block includes a plurality of lower global input/output lines shared by pairs of adjacent memory banks, a plurality of lower multiplexers receiving data from pairs of adjacent lower global input/output lines and outputting data inputted from one of the lower global input/output lines, and an upper multiplexer receiving data output from the plurality of lower multiplexers and outputting data input from one of the lower multiplexers.

Abstract: Structures and methods for a multi-bit phase change memory are disclosed herein. A method includes establishing a write-reference voltage that incrementally ramps over a write period. The increments of the write-reference voltage correspond to discrete resistance states of a storage cell of the multi-bit phase change memory.