Abstract: A vacuum pumping line plasma source is provided. The plasma source includes a body defining a generally cylindrical interior volume extending along a central longitudinal axis. The body has an input port for coupling to an input pumping line, an output port for coupling to an output pumping line, and an interior surface disposed about the generally cylindrical interior volume. The plasma source also includes a supply electrode disposed adjacent to a return electrode, and a barrier dielectric member, a least a portion of which is positioned between the supply electrode and the return electrode. The plasma source further includes a dielectric barrier discharge structure formed from the supply electrode, the return electrode, and the barrier dielectric member. The dielectric barrier discharge structure is adapted to generate a plasma in the generally cylindrical interior volume.

Abstract: A data processing device (1) is provided with: a data base storage region (32c) for storing MSn mass spectra of a great number of known compounds in advance; an acquisition unit for acquiring the MSn mass spectrum of an unknown compound (31a); and a score calculation unit (31d) for finding respective scores indicating similarities between the MSn mass spectrum of the unknown compound and MSn mass spectra of the great number of known compounds.

Abstract: Mass spectrometry systems and methods including ionization devices are provided. The ionization device includes either a gas pulse valve or a piezoelectric striker. The ionization device is configured to direct force to the back of a substrate, where an analyte of interest is deposited on the front of the substrate. The impact ionizes the analyte and the ions are directed into a mass spectrometer for analysis.

Abstract: The present disclosure provides an ion migration tube and a method of operation the same. The ion migration tube includes an interior space and an ion gate disposed within the interior space, the interior space includes an ionization region having an absolute value of potential V1 and a migration region. An ion gate is disposed between the ionization region and the migration region and includes a first ion gate grid having an absolute value of potential V2 and a second ion gate grid having an absolute value of potential V3, the migration region comprises at least a first migration region electrode having an absolute value of potential V4 and a second migration region electrode having an absolute value of potential V5. When the ion gate is opened, a potential well is formed for ionized ions between the first ion gate grid and the first migration region electrode so as to compress an ion group entering the migration region.

Abstract: A substrate-treating apparatus includes a liquid-providing part, a first liquid-removing knife and a returning part. The liquid-providing part provides a first liquid chemical for cleaning a substrate that includes a metal pattern and a photoresist pattern on the metal pattern, and for removing an etchant that remains on the substrate. The first liquid-removing knife sprays a second liquid chemical in a direction inclined and opposite to a returning direction of the substrate, so as to remove the first liquid chemical, the first liquid chemical including a metal precipitate. The returning part returns the substrate from the liquid-providing part toward the first liquid-removing knife in the returning direction.

Abstract: A structure and a formation method of a semiconductor device structure are provided. The method includes forming a gate stack over a semiconductor substrate. The method also includes forming a sealing layer over a sidewall of the gate stack using an atomic layer deposition process. The atomic layer deposition process includes alternately and sequentially introducing a first silicon-containing precursor gas and a second silicon-containing precursor gas over the sidewall of the gate stack to form the sealing layer. The second silicon-containing precursor gas has a different atomic concentration of carbon than that of the first silicon-containing precursor gas. The method further includes partially removing the sealing layer to form a sealing element over the sidewall of the gate stack.

Abstract: Provided apparatus and methods for back side passivation of a substrate. The systems comprise an elongate support with an open top surface forming a support ring so that when a substrate is on the support ring, a cavity is formed within the elongate support. A plasma generator is coupled to the cavity to generate a plasma within the cavity to deposit a passivation film on the back side of the substrate.

Abstract: Provided are methods of sealing open pores of a surface of a porous dielectric material using an initiated chemical vapor deposition (iCVD) process. In one example method of sealing open pores, since the polymer thin film having a significantly thin thickness may be formed by a solvent-free vapor deposition method without plasma treatment, it is possible to minimize deterioration of characteristics of the dielectric material vulnerable to plasma and a chemical solution.

Abstract: A method of producing an optoelectronic semiconductor chip includes in order: A) creating a nucleation layer on a growth substrate, B) applying a mask layer on to the nucleation layer, C) growing a coalescence layer, wherein the coalescence layer is grown starting from regions of the nucleation layer not covered by mask islands having a first main growth direction perpendicular to the nucleation layer so that ribs are formed, D) further growing the coalescence layer with a second main growth direction parallel to the nucleation layer to form a contiguous and continuous layer, E) growing a multiple quantum well structure on the coalescence layer, F) applying a mirror having metallic contact regions that impress current into the multiple quantum well structure and mirror islands for the total reflection of radiation generated in the multiple quantum well structure, and G) detaching the growth substrate and creating a roughening by etching.

Abstract: A method for depositing a semiconductor structure on a surface of a substrate is disclosed. The method may include: depositing a first group IVA semiconductor layer over a surface of the substrate; contacting an exposed surface of the first group IVA semiconductor layer with a first gas comprising a first chloride gas; and depositing a second group IVA semiconductor layer over a surface of the first group IVA semiconductor layer. Related semiconductor structures are also disclosed.

Abstract: Improved gate stack designs for Si and SiGe dual channel devices are provided. In one aspect, a method for forming a dual channel device includes: forming fins on a substrate, the fins including Si fins in combination with SiGe fins as dual channels of an analog device and a logic device, with the analog device and the logic device each having a Si fin and a SiGe fin; forming a silicon germanium oxide (SiGeOx) layer on the SiGe fins; annealing the SiGeOx layer to form a Si-rich layer on the SiGe fins via a reaction between SiGeOx and SiGe; and forming metal gates over the Si fins and over the Si-rich layer on the SiGe fins. A dual channel device is also provided.

Abstract: Methods of in situ fabrication and formation of horizontal nanowires for a semiconductor device employ non-catalytic selective area epitaxial growth to selectively grow a semiconductor material in a selective area opening of predefined asymmetrical geometry. The selective area opening is defined in a dielectric layer to expose a semiconductor layer underlying the dielectric layer. The non-catalytic selective area epitaxial growth is performed at a growth temperature sufficient to also in situ form a linear stress crack of nanoscale width that is nucleated from a location in a vicinity of the selective area opening and that propagates in a uniform direction along a crystal plane of the semiconductor layer in both the semiconductor layer and the dielectric layer as a linear nanogap template. The semiconductor material is further selectively grown to fill the linear nanogap template to in situ form the nanowire that is uniformly linear.

Abstract: It is intended to provide a photocured product that is prepared using the photo-imprint method and has favorable pattern precision and improvement in pattern defects. The present invention provides a photocured product obtained by irradiating a coating film in contact with a mold with light, the photocured product containing a fluorine atom-containing surfactant, wherein of secondary ion signals obtained by the surface analysis of the photocured product based on time-of-flight secondary ion mass spectrometry, the intensity of a C2H5O+ ion signal is higher than that of a C3H7O+ ion signal.

Abstract: The present disclosure provides a method in accordance with some embodiments. The method includes forming a material layer that includes an array of fin features, wherein at least one fin feature has a first material on a first sidewall and a second material on a second sidewall that is opposite to the first sidewall, wherein the first material is different from the second material. The method further includes exposing the second sidewall of the at least one fin feature and removing the at least one fin feature.

Abstract: A method of forming a semiconductor device package includes: (1) providing an electronic device including an active surface and a contact pad adjacent to the active surface; (2) forming a package body encapsulating portions of the electronic device; and (3) forming a redistribution stack, including: forming a dielectric layer over a front surface of the package body, the dielectric layer defining a first opening exposing at least a portion of the contact pad; and forming a redistribution layer (RDL) over the dielectric layer, the RDL including a first trace, wherein the first trace includes a first portion extending over the dielectric layer along a first longitudinal direction adjacent to the first opening, and a second portion disposed in the first opening and extending between the first portion of the first trace and the exposed portion of the contact pad, wherein the second portion of the first trace has a maximum width along a first transverse direction orthogonal to the first longitudinal direction, and

Abstract: Provided herein are techniques for treating vertical surface features of a semiconductor device with ions. In some embodiments, a method for forming a semiconductor device, may include providing a set of surface features extending from a substrate, the set of surface features including a sidewall. The method may include treating the sidewall with an ion beam disposed at an angle, the angle being a non-zero angle of inclination with respect to a perpendicular to a plane of an upper surface of the substrate. The method may further include rotating the substrate about the perpendicular to the plane while the sidewall is treated with the ion beam to impact an entire height of the sidewall with the ion beam.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method of fabricating a semiconductor structure. The method includes forming an opening in a substrate and depositing a conformal metal layer in the opening. The depositing includes performing one or more deposition cycles. The deposition includes flowing a first precursor into a deposition chamber and purging the deposition chamber to remove at least a portion of the first precursor. The method also includes flowing a second precursor into the deposition chamber to form a sublayer of the conformal metal layer and purging the deposition chamber to remove at least a portion of the second precursor. The method further includes performing a metallic halide etching (MHE) process that includes flowing a third precursor into the deposition chamber.

Abstract: A method includes forming a first high-k dielectric layer over a first semiconductor region, forming a second high-k dielectric layer over a second semiconductor region, forming a first metal layer comprising a first portion over the first high-k dielectric layer and a second portion over the second high-k dielectric layer, forming an etching mask over the second portion of the first metal layer, and etching the first portion of the first metal layer. The etching mask protects the second portion of the first metal layer. The etching mask is ashed using meta stable plasma. A second metal layer is then formed over the first high-k dielectric layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a semiconductor substrate, a gate structure, a first doped structure, a second doped structure, and a dielectric layer. The method includes forming a through hole in the dielectric layer. The method includes performing a physical vapor deposition process to deposit a first metal layer over the first doped structure exposed by the through hole. The method includes reacting the first metal layer with the first doped structure to form a metal semiconductor compound layer between the first metal layer and the first doped structure. The method includes removing the first metal layer. The method includes performing a chemical vapor deposition process to deposit a second metal layer in the through hole. The method includes forming a conductive structure in the through hole and over the second metal layer.

Abstract: The disclosed subject matter provides thin films including a metal silicide and methods for forming such films. The disclosed subject matter can provide techniques for tailoring the electronic structure of metal thin films to produce desirable properties. In example embodiments, the metal silicide can comprise a platinum silicide, such as for example, PtSi, Pt2Si, or Pt3Si. For example, the disclosed subject matter provides methods which include identifying a desired phase of a metal silicide, providing a substrate, depositing at least two film layers on the substrate which include a first layer including amorphous silicon and a second layer including metal contacting the first layer, and annealing the two film layers to form a metal silicide. Methods can be at least one of a source-limited method and a kinetically-limited method. The film layers can be deposited on the substrate using techniques known in the art including, for example, sputter depositing.

Abstract: A method for forming a film on a substrate in a semiconductor process chamber includes forming a first layer on the substrate using a plasma enhanced process and a gas compound of a chloride-based gas, a hydrogen gas, and an inert gas. The process chamber is then purged and the first layer is thermally soaked with a hydrogen-based precursor gas. The process chamber is then purged again and the process may be repeated with or without the plasma enhanced process until a certain film thickness is achieved on the substrate.

Abstract: A method for forming a titanium oxide film on a substrate to be processed, which has a silicon portion on a surface thereof, the method including: forming a first titanium oxide film on the surface of the substrate to be processed, which includes the silicon portion, by means of thermal ALD by alternately supplying a titanium-containing gas and a gas containing hydrogen and oxygen serving as an oxidizing agent in a first stage; and forming a second titanium oxide film on the first titanium oxide film by means of plasma ALD by alternately supplying a titanium-containing gas and plasma of an oxygen-containing gas as an oxidizing agent in a second stage.

Abstract: Techniques for fin length variability control are provided. In one aspect, a method of patterning fins in a wafer includes: depositing a hardmask and a tone invert layer on the wafer; patterning trenches in the tone invert layer; forming inverse tone etch masks on the hardmask within the trenches, wherein the inverse tone etch masks include inner and outer inverse tone etch masks; forming a save mask with opposite ends thereof aligned with the outer inverse tone etch masks; using the save mask to selectively remove unmasked portions of the tone invert layer; removing the outer inverse tone etch masks, wherein the inner inverse tone etch masks that remain have a uniform length L; patterning the hardmask into individual fin hardmasks using the inner inverse tone etch masks; and patterning fins in the wafer using the fin hardmasks. A device having fins of a uniform length L is also provided.

Abstract: A patterning method for forming a semiconductor device is disclosed. A substrate having a hard mask disposed thereon is provided. A first patterned layer is formed on the hard mask layer. A first self-aligned double patterning process based on the first patterned layer is performed to pattern the hard mask layer into a first array pattern and a first peripheral pattern. After that, a second patterned layer is formed on the substrate. A second self-aligned double patterning process based on the second patterned layer is performed to pattern the first array pattern into a second array pattern. Subsequently, a third patterned layer is formed on the substrate. An etching process using the third patterned mask layer as an etching mask is performed to etch the first peripheral pattern thereby patterning the first peripheral pattern into a second peripheral pattern.

Abstract: A method of etching is described. The method includes providing a substrate having a first material containing organic material and a second material that is different from the first material, forming a first chemical mixture by plasma-excitation of a first process gas containing an inert gas, and exposing the first material on the substrate to the first chemical mixture. Thereafter, the method includes forming a second chemical mixture by plasma-excitation of a second process gas containing C and O, and optionally a noble element, and exposing the first material on the substrate to the second plasma-excited process gas to selectively etch the first material relative to the second material.

Abstract: Methods for patterning in a semiconductor process are described. A dummy layer is formed having a cut therein. A first sacrificial layer is formed over the dummy layer, and at least a portion of the first sacrificial layer is disposed in the cut. A second sacrificial layer is formed over the first sacrificial layer. The second sacrificial layer is patterned to have a first pattern. Using the first pattern of the second sacrificial layer, the first sacrificial layer is patterned to have the first pattern. The second sacrificial layer is removed. Thereafter, a second pattern in the first sacrificial layer is formed comprising altering a dimension of the first pattern of the first sacrificial layer. Using the second pattern of the first sacrificial layer, the dummy layer is patterned. Mask portions are formed along respective sidewalls of the patterned dummy layer. The mask portions are used to form a mask.

Abstract: A semiconductor may include a substrate including a cell array region and a TSV region, an insulation layer disposed on the substrate and having a recess region on the TSV region, a capacitor on the insulation layer of the cell array region, a dummy support pattern disposed on the insulation layer of the TSV region and overlapping the recess region, when viewed in plan, and a TSV electrode penetrating the dummy support pattern and the substrate.

Abstract: A method of fabricating an interposer includes: providing a carrier substrate; forming a unit redistribution layer on the carrier substrate, the unit redistribution layer including a conductive via plug and a conductive redistribution line; and removing the carrier substrate from the unit redistribution layer. The formation of the unit redistribution layer includes: forming a first photosensitive pattern layer including a first via hole pattern; forming a second photosensitive pattern layer including a second via hole pattern and a redistribution pattern on the first photosensitive pattern layer; at least partially filling insides of the first via hole pattern, the second via hole pattern, and the redistribution pattern with a conductive material; and performing planarization to make a top surface of the unit redistribution layer flat.

Abstract: A semiconductor product such as an integrated circuit includes a laminar plastic substrate having first and second opposed surfaces and through holes extending through the substrate, electrically and/or thermally conductive material balls inserted in the through holes at the first surface of the substrate, and one or more semiconductor chips mounted at the first surface of the substrate, the semiconductor chip(s) electrically and/or thermally coupled with electrically and/or thermally conductive material balls inserted in the through holes.

Abstract: A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.

Abstract: A system and/or method for heat treatment of substrates. The system includes a housing that defines a heating chamber and a door assembly that encloses an opening of the heating chamber. The door assembly may be opened and closed. When opened, the door assembly defines a loading slot for loading substrates into and unloading substrates from the heating chamber. The door assembly is coupled to a first actuator and a control unit is coupled to the actuator to move the door assembly between a plurality of loading positions. The system may also include a loading assembly mounted to the door assembly to facilitate insertion and removal of substrates from the heating chamber.

Abstract: A substrate storing container includes a container main body, a lid body, and a lateral substrate support portion. The lateral substrate support portion of the substrate storing container includes substrate contact portions touching a substrate when supporting an edge portion of the substrate, and contact portion support portions supporting the substrate contact portions. The substrate contact portions are made of a material having a heat-resisting property with respect to temperature of the substrate touching the substrate contact portions. The contact portion support portions are made of a material having a lower heat-resisting property than that of the substrate contact portions and having a lower coefficient of moisture absorption than that of the substrate contact portions.

Abstract: The present disclosure relates to a wafer cassette system having an adaptive inset configured to enable wafers having a first diameter to be held by a wafer cassette configured to hold wafers having a second diameter larger than the first diameter. The wafer cassette system includes a wafer cassette having a first plurality of wafer slots configured to receive one or more wafers having a first diameter. An adaptive inset is arranged in an interior cavity of the wafer cassette. The adaptive inset has a second plurality of wafer slots configured to receive one or more wafers having a second diameter that is less than the first diameter. The adaptive inset allows for the wafer cassette to hold wafers having the second diameter, thereby enabling semiconductor processing tools to processes wafer having a different diameter than those able to be held by wafer cassettes that the tools can receive.

Abstract: Various embodiments provide a wafer box. The wafer box may include a housing with a receiving space for receiving at least one wafer arranged above a housing base, at least one fixing structure which is connected to the housing base and which extends from the housing base, and at least one fixing device which is fastenable to the at least one fixing structure at a variable distance from the housing base. The fixing device and the fixing structure are designed such that the at least one wafer for arrangement in the receiving space can be fixed in a position by means of the at least one fixing device fastened to the fixing structure.

Abstract: A teaching jig includes: a first plate that determines a substrate loading position in a forward/backward direction with respect to a substrate holder which holds a substrate; a second plate that determines the substrate loading position in a leftward/rightward direction with respect to the substrate holder, the second plate being installed to be perpendicular to the first plate and movable in the forward/backward direction; and a positioning target pin installed in the first plate.

Abstract: Implementations described herein provide a substrate support assembly which enables both lateral and azimuthal tuning of the heat transfer between an electrostatic chuck and a heating assembly. The substrate support assembly comprises a body having a substrate support surface and a lower surface, one or more main resistive heaters disposed in the body, a plurality of spatially tunable heaters disposed in the body, and a spatially tunable heater controller coupled to the plurality of spatially tunable heaters, the spatially tunable heater controller configured to independently control an output one of the plurality of spatially tunable heaters relative to another of the plurality of spatially tunable heaters.

Abstract: A substrate fixing device includes a baseplate, an electrostatic chuck, and an insulating layer interposed between the baseplate and the electrostatic chuck. The insulating layer includes a heating element formed of a first material and a wiring line connected in series to the heating element. The wiring line includes a first conductive layer formed of the first material and a second conductive layer joined onto the first conductive layer. The second conductive layer is formed of a second material having a resistivity lower than the resistivity of the first material.

Abstract: This disclosure is related to arranging micro devices in the donor substrate by either patterning or population so that there is no interfering with unwanted pads and the non-interfering area in the donor substrate is maximized. This enables to have transfer the devices to receiver substrate with fewer steps.

Abstract: A semiconductor diode includes an engineered substrate including a substantially single crystal layer, a buffer layer coupled to the substantially single crystal layer, and a semi-insulating layer coupled to the buffer layer. The semiconductor diode also includes a first N-type gallium nitride layer coupled to the semi-insulating layer and a second N-type gallium nitride layer coupled to the first N-type gallium nitride layer. The first N-type gallium nitride layer has a first doping concentration and the second N-type gallium nitride layer has a second doping concentration less than the first doping concentration. The semiconductor diode further includes a P-type gallium nitride layer coupled to the second N-type gallium nitride layer, an anode contact coupled to the P-type gallium nitride layer, and a cathode contact coupled to a portion of the first N-type gallium nitride layer.

Abstract: A substrate holding apparatus that holds a substrate is provided. The apparatus comprises a rotary shaft which rotates about a vertical axis and includes a suction path leading from an upper end of the rotary shaft, and a holding unit which includes a suction hole formed in a rotation center, is fixed at the upper end of the rotary shaft such that the suction hole communicates with the suction path, and holds the substrate by sucking the substrate, wherein a plurality of vent holes for introducing an external gas into a space between the holding unit and the substrate are formed at positions rotationally symmetric with respect to the rotation center of the holding unit with an angle to face a back surface of the substrate placed on the holding unit.

Abstract: Embodiments of lift pin holders are disclosed herein. In some embodiments, a lift pin holder includes a housing member having an upper portion and a lower portion, wherein the upper portion includes an annular wall defining a central space; a support member disposed at least partially within the central space and having a base and an upwardly protruding portion configured to support a lift pin; a first gripper disposed atop the support member and having a first plurality of prongs protruding upward from a body of the first gripper and configured to grip the lift pin; and a second gripper disposed atop the base of the support member and having a second plurality of prongs protruding upward from a body of the second gripper and are configured to grip the lift pin, wherein the first gripper is disposed within the third central opening.

Abstract: A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p-and n-terminals formed in an i-region above a substrate.

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

Abstract: A semiconductor device includes a trench extending through a semiconductor substrate and an epitaxial layer disposed over a first side of the semiconductor substrate. The epitaxial layer partially fills a portion of the trench. The semiconductor device further includes a back side metal layer disposed over a second side of the semiconductor substrate. The back side metal layer extends into the trench and fills the remaining portion of the trench. The epitaxial layer partially filling the trench contacts the back side metal layer filling the remaining portion within the trench.

Abstract: A method for sawing a semiconductor wafer is provided. The method includes sawing a semiconductor wafer to form a first opening. In addition, the semiconductor wafer includes a dicing tape and a substrate attached to the dicing tape by a die attach film (DAF), and the first opening is formed in an upper portion of the substrate. The method further includes sawing through the substrate and the DAF of the semiconductor wafer from the first opening to form a middle opening under the first opening and a second opening under the middle opening, so that the semiconductor wafer is divided into two dies. In addition, a slope of a sidewall of the middle opening is different from slopes of sidewalls of the first opening and the second opening.

Abstract: A method includes forming a transistor including forming a source/drain region on a side of a dummy gate stack, forming a first Inter-Layer Dielectric (ILD) covering the source/drain region, and replacing the dummy gate stack with a replacement gate stack. The method further includes forming a second ILD over the first ILD and the replacement gate stack, and forming a lower source/drain contact plug electrically coupling to the source/drain region. The lower source/drain contact plug penetrates through both the first ILD and the second ILD. A third ILD is formed over the second ILD. A gate contact plug is formed in the second ILD and the third ILD. An upper source/drain contact plug is formed overlapping and contacting the lower source/drain contact plug. The upper source/drain contact plug penetrates through the third ILD. The upper source/drain contact plug and the gate contact plug are formed of different materials.

Abstract: A semiconductor device is disclosed, including a plurality of conductive features disposed over a substrate. A dielectric layer separates the conductive features. A conductive line is provided, connecting a subset of the conductive features. The conductive line includes a line-like portion and a line-end portion.

Abstract: A method of forming a semiconductor device includes depositing a flowable dielectric layer on a substrate and annealing the flowable dielectric layer. The method further includes performing a high temperature (HT) doping process on the flowable dielectric layer. The HT doping process may include implanting dopant ions into the flowable dielectric layer and heating the substrate during the implanting of the dopant ions. The heating of the substrate may include heating a substrate holder upon which the substrate is disposed and maintaining the substrate at a temperature above 100° C. An example benefit reduced the wet etch rate (WER) of the flowable dielectric layer.