Abstract: A method of forming a semiconductor device fabrication is described that includes forming a material layer over a substrate, forming a first trench in the material layer, forming a first dielectric capping layer along sidewalls of the first trench, forming a second trench in the material layer while the capping layer disposed along sidewalls of the first trench, forming a second dielectric capping layer along sidewalls of the second trench and along the sidewalls of the first trench and forming a conductive feature within the second trench and the first trench.

Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphene barrier layer. The present disclosure provides a method of forming a graphene barrier layer on select surfaces using a self-assembly monolayer (SAM). The SAM layer can be selectively formed on dielectric surfaces and annealed to form thin graphene barrier layers. The thickness of the graphene barrier layers can be selected by choosing different alkyl groups of the SAM layer.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a first conductive feature in a first dielectric layer and a second conductive feature over the first dielectric layer. The semiconductor device structure also includes a conductive via between the first conductive feature and the second conductive feature. The conductive via includes an etching stop layer over the first conductive feature, a conductive pillar over the etching stop layer, and a capping layer surrounding the conductive pillar and the etching stop layer. The first conductive feature and the second conductive feature are electrically connected to each other through the capping layer, the conductive pillar, and the etching stop layer. The semiconductor device structure further includes a second dielectric layer over the first dielectric layer and below the second conductive feature. The second dielectric layer surrounds the conductive via.

Abstract: Methods of dicing semiconductor wafers are described. In an example, a method of dicing a semiconductor wafer having integrated circuits thereon involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a multiple pass laser scribing process to provide a patterned mask with gaps exposing regions of the semiconductor wafer between the integrated circuits, the multiple pass laser scribing process including a first pass along a first edge scribing path, a second pass along a center scribing path, a third pass along a second edge scribing path, a fourth pass along the second edge scribing path, a fifth pass along the center scribing path, and a sixth pass along the first edge scribing path. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.

Abstract: A processing method for a workpiece includes: a holding step of holding the workpiece by a chuck table; a groove forming step of moving the chuck table in a processing feeding direction at a first speed, and sequentially cutting a plurality of division lines extending in a first direction by a first cutting blade to form the workpiece with grooves along the division lines; a first deep-cutting step of further cutting the grooves, by a second cutting blade, to thereby deep-cut the grooves, during when the groove forming step is performed; and a second deep-cutting step of moving the chuck table in the processing feeding direction at a second speed higher than the first speed, and further cutting by the second cutting blade those of the grooves which have not been deep-cut in the first deep-cutting step, to thereby deep-cut those grooves, after the groove forming step.

Abstract: A processing method for a substrate having a metal exposed and having cutting lines of a predetermined width set thereon includes: a structural body disposing step of disposing two structural bodies on the metal along respective edges in regard of the width direction of the cutting line, with a gap corresponding to the width therebetween; and a cutting step of causing a cutting blade to cut into the substrate from between the two structural bodies to cut the substrate along the cutting lines, after the structural body disposing step is carried out.

Abstract: A device and method of forming the device that includes cavities formed in a substrate of a substrate device, the substrate device also including conductive vias formed in the substrate. Chip devices, wafers, and other substrate devices can be mounted to the substrate device. Encapsulation layers and materials may be formed over the substrate device in order to fill the cavities.

Abstract: A workpiece dividing method includes: a laser processing step of forming along each street a plurality of minute holes extending in a pulsed laser beam application direction; and a dividing step of pressing the streets by a pressing member to divide a wafer along the streets. The minute hole has one end opening at least one of a front surface and a back surface of the wafer and is decreased in diameter from the one end toward the other end. In the dividing step, the pressing member is pressed against that surface of the front surface and the back surface of the wafer at which the one end of the minute hole is not opening.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A method for manufacturing a semiconductor device includes forming a hardmask layer on a substrate, patterning the hardmask layer to form a plurality of patterned hardmask portions on the substrate, depositing a dummy hardmask layer on the substrate, patterning the dummy hardmask layer to form a plurality of patterned dummy hardmask portions on the substrate, wherein each of the plurality of patterned dummy hardmask portions is positioned adjacent respective outermost patterned hardmask portions of the plurality of patterned hardmask portions, and transferring a pattern of the plurality of patterned hardmask portions and the plurality of patterned dummy hardmask portions to the substrate to form a plurality of fins and a plurality of dummy fins from the substrate.

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.

Abstract: A method includes forming a gate dielectric layer on a semiconductor fin, and forming a gate electrode over the gate dielectric layer. The gate electrode extends on sidewalls and a top surface of the semiconductor fin. A gate spacer is selectively deposited on a sidewall of the gate electrode. An exposed portion of the gate dielectric layer is free from a same material for forming the gate spacer deposited thereon. The method further includes etching the gate dielectric layer using the gate spacer as an etching mask to expose a portion of the semiconductor fin, and forming an epitaxy semiconductor region based on the semiconductor fin.

Abstract: Methods for forming cointegrated III-V and Ge channels for vertical field effect transistors are described. Aspects of the invention include forming a first fin and a second fin on a substrate, wherein the first fin includes a first material including a first semiconductor material at a first concentration level, and wherein the second fin includes a second material including a second semiconductor material at a second concentration. A condensation oxidation is performed to increase the first concentration level to a targeted first final concentration level and increase the second concentration level to a targeted second final concentration level. The second fin is replaced with a third fin including a third material including a combination of a group III element with a group V element.

Abstract: Disclosed herein are methods, structures, and devices for wafer scale testing of photonic integrated circuits.

Abstract: An assembly includes a wafer having a top wafer surface and a wafer circumference and a device arrangement structure. The device arrangement structure includes a first surface having a perimeter, the perimeter being encircled by the wafer circumference in a plan view. The device arrangement structure also includes an array of devices, each device of the array of devices having an electrical contact on the first surface. The assembly has an adhesive element that affixes the device arrangement structure in a stationary position relative to the wafer.

Abstract: Disclosed herein is a method for forming a test key system for characterizing wafer processing states, the method comprising forming a plurality of shallow trench isolation structures (STIs) on a substrate of a wafer and in a scribe line of the wafer and forming a test key on the substrate of a wafer and in the scribe line of the wafer. Forming the test key comprises forming at least one test key group having a plurality of test key series, each of the plurality of test key series having a plurality of test pads, each one of the plurality of test key series having a first physical characteristic different from the first physical characteristic of other test key series the at least one first test key group.

Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.

Abstract: An interposer includes a substrate having a mounting area and a test area, first conductive plugs separate from each other, the first conductive plugs being disposed along a first direction and into the test area of the substrate, a first line pattern group including first non-conductive patterns disposed on first centers of the first conductive plugs, and first conductive patterns disposed to bridge first peripheries of a first adjacent pair of the first conductive plugs, and first pads connected to the first conductive patterns at both first ends of the first line pattern group.

Abstract: In one embodiment, a semiconductor device includes a first contact pad disposed at a top side of a workpiece, a second contact pad disposed at the top side of the workpiece. An isolation region is disposed between the first contact pad and the second contact pad. A metal strip is disposed at least partially within the isolation region. The metal strip is not coupled to an external potential node.

Abstract: In a semiconductor device, a plurality of semiconductor chips included in an upper-arm circuit are connected in parallel between a pair of upper-arm plates, while a plurality of semiconductor chips included in a lower-arm circuit are connected in parallel between a pair of lower-arm plates. In each of the arm circuits, the plurality of semiconductor chips are arranged in a direction perpendicular to a direction in which emitter electrodes and pads are arranged, the pads are disposed on the same side of the emitter electrodes, and signal terminals extend in the same direction. A series-connecting part between the upper- and lower-arm circuits includes a joint part 20 continued to respective side surfaces of the corresponding upper- and lower-arm plates. Each of inductances of respective parallel-connecting parts of the upper- and lower-arm plates which connect the semiconductor chips in parallel is smaller than an inductance of the series-connecting part.

Abstract: A semiconductor device includes a plurality of circuit regions formed at a circuit semiconductor layer of a semiconductor die. The semiconductor device includes an etch stop layer of the semiconductor die arranged between the circuit semiconductor layer of the semiconductor die and a handling layer of the semiconductor die. The semiconductor device includes one or more trench structures extending through the handling layer of the semiconductor die. The one or more trench structures extends to at least the etch stop layer and to at most the circuit semiconductor layer of the semiconductor die.

Abstract: A power semiconductor device and package includes multiple electrically parallel semiconductor device legs designed to share source regions and share a drain region between two devices in each leg laterally staggered from each other to distribute thermal conductivity across the shared source regions. A multitude of jigsaw patterned lateral isolation trenches are formed in a substrate of the device. The trenches are configured to isolate the laterally staggered line-in and line-out source regions from a common drain region of the plurality of semiconductor device legs. The staggered devices are also designed for staggered time and staggered heat conductivity delays and current spreading from the package input to an output of a respective pair of devices to improve current and heat conductivity from the package input to an output of a subsequent pair of devices.

Abstract: A die includes a semiconductor substrate, a through-via penetrating through the semiconductor substrate, a seal ring overlying and connected to the through-via, and an electrical connector underlying the semiconductor substrate and electrically coupled to the seal ring through the through-via.

Abstract: A module 1a includes an electronic component 3a, and also includes a wiring substrate 2 on one principal surface of which the electronic component 3a is mounted and in which a radiator 4 for dissipating heat generated from the electronic component 3 is provided. The radiator 4 includes a heat dissipation section 4a that is provided so that a part thereof is exposed to a side surface of the wiring substrate 2. In this case, because the heat dissipation section 4a is provided so that a part thereof is exposed to the side surface of the wiring substrate 2, the heat from the electronic component 3a can be dissipated through the side surface of the wiring substrate 2.

Abstract: A semiconductor thermal-conductive heat sink structure includes a substrate and a thermal-conductive heat sink device. The substrate includes opposed upper and lower planes. A top conductive copper foil is provided on the upper plane to carry a semiconductor device. The thermal-conductive heat sink device includes at least one cooling fin and a high thermal-conductive rivet. A clearance is formed between the cooling fin and a thermal-conductive heat sink device socket or between two adjacent cooling fins such that greater cooling areas are available to the thermal-conductive heat sink device. With the thermal-conductive rivet joining the top conductive copper foil and the cooling fins, heat generated by the activated semiconductor device is quickly conducted through the rivet and dissipated from the greater cooling areas of the cooling fins to prevent malfunction of the semiconductor device attributed to heat accumulation induced by poor heat dissipation.

Abstract: An electrostatic discharge (ESD) protection device includes a substrate including a device region and an ESD protection structure formed on the substrate in the device region. The device region includes a center region and edge regions separated by the center region, while the ESD protection structure includes a plurality of gate structures. The ESD protection device also includes a dielectric layer formed to cover the plurality of gate structures and a plurality of heat dissipation structures formed on the dielectric layer with each heat dissipation structure aligned with a corresponding gate structure along a direction perpendicular to a surface of the substrate. The area size of each heat dissipation structure aligned with a corresponding gate structure in the center region is larger than the area size of each heat dissipation structure aligned with a corresponding gate structure in the edge region.

Abstract: A power electronic arrangement having a power semiconductor module and an external load-connecting element is provided with the external load-connecting element has a first connection device, and the power semiconductor module has a housing, a base plate and an internal load-connecting element with a second connection device, wherein the base plate has a first cut out through which the first connection device extends into the interior of the power semiconductor module and is connected there in a frictionally locking and electrically conductive fashion to a second connection device of the internal load-connecting element.

Abstract: In one general aspect, an integrated passive device (IPD) die includes at least one passive component that is embedded in an insulator material disposed on a front surface of a substrate. The IPD die includes a through-substrate via (TSV) extending from the backside of the substrate toward the front surface of the substrate. The TSV defines interconnect access to at least one passive component embedded in the insulator material disposed on the front surface of the substrate. The substrate has a thickness less than three-quarters of an original thickness of the substrate.

Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.

Abstract: Packaged semiconductor device having a frame, of conductive material; a body of semiconductor material, fixed to the frame through a first adhesive layer; a heat-sink element, fixed to the body through a second adhesive layer; and a packaging mass surrounding the body and, at least partially, the frame and the heat-sink element. The heat-sink element is formed by a heat-sink die facing, and coplanar to, a main face of the device and by a spacer structure, which includes a pair of pedestals projecting from the perimeter of the heat-sink die towards the body and rest on the body.

Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.

Abstract: A clip structure and a semiconductor package using the same include different metals in multiple layers so as to selectively, easily and exactly fix semiconductor chips, which consists of a lightweight material so as to lighten the weight of semiconductor packages and to help reduce manufacturing costs, and which in particular, maintains the width of a self-welding layer consisting of a clip structure so as to help improve the quality of adhesion. That is, according to a clip structure of the present invention, which electrically connects package elements in a semiconductor package, the clip structure includes a main metallic layer that is configured to maintain a shape, and a first functional layer that is piled on one surface of the main metallic layer and consists of a metal different from that of the main metal layer.

Abstract: A multi-layer solder-resist provides useful adhesion to a semiconductor device package substrate while allowing for increasingly small geometries of bond pads and spacings.

Abstract: A semiconductor device includes a substrate, electrical conductors and a passivation layer. Each of the electrical conductors includes a first portion through the substrate, and a second portion over the surface of the substrate and connected to the first portion. The passivation layer is over the surface of the substrate, wherein the passivation layer partially covers an edge of the second portion of each of the electrical conductors.

Abstract: A barrier layer is formed over electrically conductive contact pads on a substrate such as a wafer. A photoresist layer is applied over the barrier layer, and openings in the photoresist layer are filled with solder to form solder bumps. The barrier layer may be removed from within the openings prior to filling the openings with solder. The process is applicable to fine pitch architectures and chip size packaging substrates. The photoresist layer and portions of the barrier layer outside of the openings are removed following solder fill.

Abstract: A package structure including a circuit substrate, a semiconductor die, a redistribution layer, a plurality of conductive balls and a circuit substrate is provided. The redistribution layer is disposed on the semiconductor die, and being electrically connected to the semiconductor die. The plurality of conductive balls is disposed between the redistribution layer and the circuit substrate. The semiconductor die is electrically connected to the circuit substrate through the conductive balls. Each of the conductive balls has a ball foot with a first width D1, a ball head with a third width D3 and a ball waist with a second width D2 located between the ball foot and the ball head. The ball foot is connected to the redistribution layer, the ball head is connected to the circuit substrate, and the ball waist is the narrowest portion of each of the conductive balls.

Abstract: A semiconductor device comprises an interposer with extruded feed-through vias and a semiconductor die. The interposers includes a substrate having a plurality of through-vias. A dielectric liner lining said through-vias. A plurality of feed-thru electrically conducting features provided by a plurality of extruded metal wires within said dielectric liner. A semiconductor die attached to said interposer.

Abstract: Embodiments are generally directed to a conductive base embedded interconnect. An embodiment of an apparatus includes a substrate; an embedded interconnect layer in a first side of the substrate, the embedded interconnect layer including a plurality of contacts; and one or more conductive paths through the substrate, the one or more conductive paths being connected with the embedded interconnect layers.

Abstract: Various embodiments of a feedthrough assembly and methods of forming such assemblies are disclosed. In one or more embodiments, the feedthrough assembly can include a non-conductive substrate and a feedthrough. The feedthrough can include a via from an outer surface to an inner surface of the non-conductive substrate, a conductive material disposed in the via, and an external contact disposed over the via on the outer surface of the non-conductive substrate. The external contact can be electrically coupled to the conductive material disposed in the via. And the external contact can be hermetically sealed to the outer surface of the non-conductive substrate by a bond surrounding the via. In one or more embodiments, the bond can be a laser bond.

Abstract: The present disclosure provides a semiconductor package device, which includes an interposer die. The interposer die includes a semiconductor substrate and a plurality of through-silicon-vias (TSVs) extending through the semiconductor substrate. The semiconductor package device also includes a semiconductor die spaced apart from the interposer die, a first redistribution layer disposed on a first side of the interposer die and electrically coupling the interposer die with the semiconductor die, and a second redistribution layer on a second side of the interposer die opposite the first side.

Abstract: A semiconductor device includes: a plurality of vertical conductive structures, wherein each of the plurality of vertical conductive structures extends through an isolation layer; and an insulated extension disposed horizontally between a first one and a second one of the plurality of vertical conductive structures.

Abstract: An integrated circuit (IC) device includes: a channel region that extends on the substrate to penetrate a plurality of word lines; a bit line contact pad that contacts an upper surface of the channel region; a bit line that contacts the bit line contact pad and extends on the bit line contact pad in a direction parallel to the main surface of the substrate; a common source line that partially fills a word line cut region and has a height lower than that of the channel region; and a common source via contact that contacts an upper surface of the common source line in the word line cut region.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including a lower wiring, a first interlayer insulating film disposed on the substrate and including a first region and a second region over the first region, an etch stop film on the first interlayer insulating film, a second interlayer insulating film on the etch stop film, a first upper wiring in the second interlayer insulating film, the etch stop film, and the second region of the first interlayer insulating film and the first upper wiring is spaced apart from the lower wiring and a via in the first region of the first interlayer insulating film, and the via connects the lower wiring and the first upper wiring, wherein the first upper wiring includes a first portion in the second interlayer insulating film, and a second portion in the etch stop film and the second region of the first interlayer insulating film, and a sidewall of the second portion of the first upper wiring includes a stepwise shape.

Abstract: An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.

Abstract: An integrated circuit structure includes a first fuse line formed in a first metal layer; a second fuse line formed in the first metal layer; a first pair of fuse wings formed in the first metal layer on opposite sides of a first end of the first fuse line; a second pair of fuse wings formed in the first metal layer on opposites sides of a first end of the second fuse line; a third pair of fuse wings formed in the first metal layer on opposite sides of a second end of the first fuse line; and a fourth pair of fuse wings formed in the first metal layer on opposites sides of a second end of the second fuse line. The first and second pairs of fuse wings share a first common fuse wing and the third and fourth pairs of wings share a second common fuse wing.

Abstract: A method includes depositing a dielectric structure on a first conductive structure, etching the dielectric structure to form a via opening, etching the dielectric structure to form a trench over the via opening, depositing a first protective layer on a bottom surface of the trench, filling the trench and the via opening with a second conductive structure, and removing the first protective layer to form an air gap between the second conductive structure and the dielectric structure.

Abstract: A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.

Abstract: A semiconductor memory device includes word lines extending in a first direction on a semiconductor substrate, bit line structures crossing over the word lines and extending in a second direction intersecting the first direction, and contact pad structures between the word lines and between the bit line structures in plan view. A spacer structure extends between the bit line structures and the contact pad structures. The spacer structure includes a first air gap extending in the second direction along sidewalls of the bit line structures and a second air gap surrounding each of the contact pad structures and coupled to the first air gap.

Abstract: A method of making a semiconductor device includes forming a first source/drain trench and a second source/drain trench over a first and second source/drain region, respectively; forming a first silicon dioxide layer in the first source/drain trench and a second silicon dioxide layer in the second source/drain trench; forming a first source/drain contact over the first source/drain region, the first source/drain contact including a first tri-layer contact disposed between the first silicon dioxide layer and a first conductive material; and forming a second source/drain contact over the second source/drain region, the second source/drain contact including a second tri-layer contact disposed between the second silicon dioxide layer and a second conductive material; wherein the first tri-layer contact includes a first metal oxide layer in contact with the first silicon dioxide layer, and the second tri-layer contact includes a second metal oxide layer in contact with the second silicon dioxide layer.

Abstract: There is provided a field-effect transistor including: a gate electrode; a semiconductor layer having a source region and a drain region with the gate electrode in between; contact plugs provided on the source region and the drain region; first metals stacked on the contact plugs; and a low-dielectric constant region provided in a region between the first metals along an in-plane direction of the semiconductor layer and provided at least in a first region below bottom surfaces of the first metals along a stacking direction.