Patents Issued in March 17, 2020
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Patent number: 10592239Abstract: In an embodiment, a matrix computation engine is configured to perform matrix computations (e.g. matrix multiplications). The matrix computation engine may perform numerous matrix computations in parallel, in an embodiment. More particularly, the matrix computation engine may be configured to perform numerous multiplication operations in parallel on input matrix elements, generating resulting matrix elements. In an embodiment, the matrix computation engine may be configured to accumulate results in a result memory, performing multiply-accumulate operations for each matrix element of each matrix.Type: GrantFiled: May 28, 2019Date of Patent: March 17, 2020Assignee: Apple Inc.Inventors: Eric Bainville, Tal Uliel, Erik Norden, Jeffry E. Gonion, Ali Sazegari
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Patent number: 10592240Abstract: An electronic apparatus includes a permutation circuit and an arbitration circuit. The permutation circuit is configured to apply to an input vector a permutation selected from a plurality of predefined permutations in response to a control word. The arbitration circuit is configured to receive a vector of requests for a resource, to instruct the permutation circuit to apply a randomly-selected permutation to the vector of requests, by configuring the permutation circuit with a corresponding randomly-selected control word so as to produce a permuted vector, to select an element of the permuted vector, to apply to the permuted vector an inverse of the randomly-selected permutation so as to produce an inversely-permuted vector, to identify an element of the inversely-permuted vector to which the selected element of the permuted vector is mapped, and to assign the resource to a client corresponding to the identified element of the inversely-permuted vector.Type: GrantFiled: October 15, 2018Date of Patent: March 17, 2020Assignee: MELLANOX TECHNOLOGIES TLV LTD.Inventors: Liron Mula, Gil Levy
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Patent number: 10592241Abstract: Aspects for matrix multiplication in neural network are described herein. The aspects may include a master computation module configured to receive a first matrix and transmit a row vector of the first matrix. In addition, the aspects may include one or more slave computation modules respectively configured to store a column vector of a second matrix, receive the row vector of the first matrix, and multiply the row vector of the first matrix with the stored column vector of the second matrix to generate a result element. Further, the aspects may include an interconnection unit configured to combine the one or more result elements generated respectively by the one or more slave computation modules to generate a row vector of a result matrix and transmit the row vector of the result matrix to the master computation module.Type: GrantFiled: October 25, 2018Date of Patent: March 17, 2020Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITEDInventors: Xiao Zhang, Shaoli Liu, Tianshi Chen, Yunji Chen
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Patent number: 10592242Abstract: Systems, methods, devices, and non-transitory media of various embodiments render vector data on static and dynamic surfaces by a computing device for a graphic display or for a separate computing device and/or algorithm to generate an image. Complex vector data associated with a surface for rendering may be rendered. The complex vector data may be decomposed into one or more vector subunits. A geometry corresponding to a volume and a mathematical description of an extrusion of each corresponding vector subunit may be generated. The volume and the mathematical description of the extrusion may intersect a surface level-of-detail of the surface. The geometry may be rasterized as a screen-space decal. Also, a surface depth texture may be compared for the surface against the extrusion using at least the screen-space decal. In addition, geometry batching may be performed for drawing simultaneously a plurality of the one or more vector subunits.Type: GrantFiled: July 19, 2019Date of Patent: March 17, 2020Assignee: Cesium GS, Inc.Inventors: Kangning Li, Daniel Bagnell
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Patent number: 10592243Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine fetches stream data ahead of use by the central processing unit core in a stream buffer constructed like a cache. The stream buffer cache includes plural cache lines, each includes tag bits, at least one valid bit and data bits. Cache lines are allocated to store newly fetched stream data. Cache lines are deallocated upon consumption of the data by a central processing unit core functional unit. Instructions preferably include operand fields with a first subset of codings corresponding to registers, a stream read only operand coding and a stream read and advance operand coding.Type: GrantFiled: September 10, 2018Date of Patent: March 17, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Joseph Zbiciak
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Patent number: 10592244Abstract: An example processor that includes a decoder, an execution circuit, a counter, and a last branch recorder (LBR) register. The decoder may decode a branch instruction for a program. The execution circuit may be coupled to the decoder, where the execution circuit may execute the branch instruction. The counter may be coupled to the execution circuit, where the counter may store a cycle count. The LBR register coupled to the execution circuit, where the LBR register may include a counter field to store a first value of the counter when the branch instruction is executed and a type field to store type information indicating a type of the branch instruction.Type: GrantFiled: February 2, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Michael W. Chynoweth, Jonathan D. Combs, Joseph K. Olivas, Beeman C. Strong, Rajshree A. Chabukswar, Ahmad Yasin, Jason W. Brandt, Ofer Levy, John M. Esper, Andreas Kleen, Christopher M. Chrulski
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Patent number: 10592245Abstract: Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.Type: GrantFiled: May 19, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Gilbert M. Wolrich, Vinodh Gopal, Sean M. Gulley, Kirk S. Yap, Wajdi K. Feghali
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Patent number: 10592246Abstract: A computer processing system is provided. The computer processing system includes a processor configured to crack a record form FP instruction into two internal instructions. A first one of the two internal instructions executes out-of-order to compute a target FP register and a second one of the two internal instructions executes in-order to compute a condition register (CR) to improve a processing speed of the record form FP instruction.Type: GrantFiled: July 12, 2017Date of Patent: March 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brian J. D. Barrick, Maarten J. Boersma, Niels Fricke, Michael J. Genden
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Patent number: 10592247Abstract: An arithmetic circuit comprises first to N-th, N being an integer equal to or larger than two, element circuits respectively including: input circuits which input first operand data and second operand data; and element data selectors which select operand data of any one of the element circuits on the basis of a request element signal; and a data bus which supplies the operand data from the input circuits to the element data selectors. When a control signal is in a first state, the element data selectors select, on the basis of the request element signal included in the second operand data, the first operand data of any of the element circuits and output the first operand data.Type: GrantFiled: August 24, 2015Date of Patent: March 17, 2020Assignee: FUJITSU LIMITEDInventor: Tomonori Tanaka
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Patent number: 10592248Abstract: Techniques for improving branch target buffer (“BTB”) operation. A compressed BTB is included within a branch prediction unit along with an uncompressed BTB. To support prediction of up to two branch instructions per cycle, the uncompressed BTB includes entries that each store data for up to two branch predictions. The compressed BTB includes entries that store data for only a single branch instruction for situations where storing that single branch instruction in the uncompressed BTB would waste space in that buffer. Space would be wasted in the uncompressed BTB due to the fact that, in order to support two branch lookups per cycle, prediction data for two branches must have certain features in common (such as cache line address) in order to be stored together in a single entry.Type: GrantFiled: August 30, 2016Date of Patent: March 17, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventor: Steven R. Havlir
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Patent number: 10592249Abstract: Processing of an instruction fetch from an instruction cache is provided, which includes: determining whether the next instruction fetch is from a same address page as a last instruction fetch from the instruction cache; and based, at least in part, on determining that the next instruction fetch is from the same address page, suppressing for the next instruction fetch an instruction address translation table access, and comparing for an address match results of an instruction directory access for the next instruction fetch with buffered results of a most-recent, instruction address translation table access for a prior instruction fetch from the instruction cache.Type: GrantFiled: October 17, 2017Date of Patent: March 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Valentina Salapura
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Patent number: 10592250Abstract: Disclosed herein are techniques for self-refilling an instruction buffer by an execution engine while the execution engine executes instructions in the instruction buffer. An instruction loader splits instruction code into sections of code and creates a data store (e.g., a DMA ring) for loading the sections of code into the instruction buffer. In some embodiments, an instruction is added to some sections of code. The instruction, when executed by the execution engine, triggers the loading of one or more sections of code into the instruction buffer based on one or more entries in the data store. In some embodiments, a hardware logic in the execution engine is configured to trigger the loading of the sections of code into the instruction buffer. In some embodiments, the one or more sections of code are loaded into the instruction buffer through a refill page that is different from the instruction buffer.Type: GrantFiled: June 21, 2018Date of Patent: March 17, 2020Assignee: Amazon Technologies, Inc.Inventors: Ron Diamant, Ilya Minkin
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Patent number: 10592251Abstract: Register restoration using transactional memory register snapshots. An indication that a transaction is to be initiated is obtained. Based on obtaining the indication, a determination is made as to whether register restoration is in active use. Based on obtaining the indication and determining register restoration is in active use, register restoration is deactivated. To recover one or more architected registers of the transaction, a transactional rollback snapshot is created.Type: GrantFiled: November 14, 2017Date of Patent: March 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael K. Gschwind, Valentina Salapura
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Patent number: 10592252Abstract: Efficient instruction processing for sparse data includes extensions to a processor pipeline to identify zero-optimizable instructions that include at least one zero input operand, and bypass the execute stage of the processor pipeline, determining the result of the operation without executing the instruction. When possible, the extensions also bypass the writeback stage of the processor pipeline.Type: GrantFiled: December 31, 2015Date of Patent: March 17, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Trishul A. Chilimbi, Olatunji Ruwase, Vivek Seshadri
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Patent number: 10592253Abstract: Technologies for pre-memory phase initialization include a computing device having a processor with a cache memory. The computing device may determine whether a temporary memory different from the cache memory of the processor is present for temporary memory access prior to initialization of a main memory of the computing device. In response to determining that temporary memory is present, a portion of the basic input/output instructions may be copied from a non-volatile memory of the computing device to the temporary memory for execution prior to initialization of the main memory. The computing device may also initialize a portion of the cache memory of the processor as Cache as RAM for temporary memory access prior to initialization of the main memory in response to determining that temporary memory is not present. After initialization, the main memory may be configured for subsequent memory access. Other embodiments are described and claimed.Type: GrantFiled: February 7, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Giri P. Mudusuru, Rangasai V. Chaganty, Chasel Chiu, Satya P. Yarlagadda, Nivedita Aggarwal, Nuo Zhang
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Patent number: 10592254Abstract: Technologies for fast low-power startup include a computing device with a processor having a power management integrated circuit. The computing device initializes platform components into a low-power state and determines, in a pre-boot firmware environment, the battery state of the computing device. The computing device determines a minimum-power startup (MPS) configuration that identifies platform components to be energized and determines whether the battery state is sufficient for the MPS configuration. If sufficient, the computing device energizes the platform components of the MPS configuration and boots into an MPS boot mode. In the MPS boot mode, the computing device may execute one or more user-configured application(s). If the battery state is sufficient for normal operation, the computing device may boot into a normal mode. In the normal mode, the user may configure the MPS configuration by selecting features for the future MPS boot mode. Other embodiments are described and claimed.Type: GrantFiled: September 5, 2017Date of Patent: March 17, 2020Assignee: Intel CorporationInventors: Rajesh Poornachandran, Vincent J. Zimmer, Karunakara Kotary, Venkatesh Ramamurthy, Pralhad M. Madhavi
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Patent number: 10592255Abstract: A computer-implemented method, for booting a computer system, that provides a list with entries of startup processes. Each startup process defines a resource of the computer system. For each startup process a requirement is defined. The method further comprises fetching one of the entries of the list with entries of startup processes; determining whether the requirement is satisfied for the one of the entries of the list with entries of startup processes; fetching, in case the requirement is not fulfilled, a next one of the entries of the list with entries of startup processes; starting, in case the required resource is fulfilled, the startup process; and repeating the fetching a next one of the entries, the determining and the starting until all startup processes of the list of startup processes have been started.Type: GrantFiled: October 24, 2017Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Reinhard T. Buendgen, Jakob C. Lang, Volker Boenisch, Angel Nunez Mencias
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Patent number: 10592256Abstract: A secondary processing system that is coupled to a primary processing system and a display system accesses a first memory system to load initial boot instructions and a video interpreter binary during a boot operation. The secondary processing system initializes the display controller included in the display system to provide a first graphical user interface for display on the display screen using the video interpreter binary and executes the initial boot instructions. The secondary processing system then detects a first interrupt event during the execution of the initial boot instructions and, in response, triggers the video interpreter binary to update the first graphical user interface displayed on the display screen to provide a second graphical user interface for display on the display screen.Type: GrantFiled: May 1, 2018Date of Patent: March 17, 2020Assignee: Dell Products L.P.Inventor: Anh Dinh Luong
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Patent number: 10592257Abstract: Embodiments of the present disclosure relate to a method, device and computer program product for kernel management. The method comprises: receiving, from a server, a plurality of instances of a kernel module to be loaded into a kernel, the plurality of instances corresponding to a plurality of candidate versions, determining a current version of the kernel in response to the kernel being started or updated, and loading, to the kernel, an instance of the plurality of instances corresponding to the current version. Embodiments of the present disclosure may improve the security of the operating system, meet close-source requirement of a commercial operating system and also simplify the process of the kernel module referring to one or more APIs.Type: GrantFiled: August 31, 2018Date of Patent: March 17, 2020Assignee: EMC IP Holding Company LLCInventors: Yizhou Zhou, Zhibin Zhang
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Patent number: 10592258Abstract: Systems, methods, and non-transitory computer-readable media can determine a set of feature components corresponding to a software application, wherein each feature component corresponds to a modularized feature provided by the software application. An order for loading the set of feature components upon execution of the software application can be determined. The set of feature components can be loaded in memory based at least in part on the determined order.Type: GrantFiled: November 10, 2017Date of Patent: March 17, 2020Assignee: Facebook, Inc.Inventors: Julian Krzeminski, Cheng Huang
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Patent number: 10592259Abstract: Various examples for application management detection are described. In one example, depending upon whether an installation token includes a unique token value, a client device can determine whether an application is managed or unmanaged. Additionally, the client device can determine whether the application is managed or unmanaged based on whether a keychain installation token includes a unique token value, a value of a keychain installation token, and a value of a launched flag for the application. Using the concepts described herein, an unmanaged application can proceed to execute with limited functionality, present a notification that it should be reinstalled by the management service, stop executing, or take other measures.Type: GrantFiled: June 20, 2017Date of Patent: March 17, 2020Assignee: AIRWATCH LLCInventors: Lucas Chen, Raghuram Rajan, Jonathan Blake Brannon
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Patent number: 10592260Abstract: A system provides a design interface for designing and implementing graphical user interfaces that users can access through web browsers. Depending on the configuration of the graphical user interfaces, the users may be able to monitor and control industrial processes by interacting with components that correspond to the industrial processes as displayed in user interfaces at client devices. The design interface includes functionality for selecting preprogrammed components, or for generating new components for display. The design interface further allows designers to associate data values received from a variety of sources with properties of the components in the user interfaces. In particular, properties associated with a component of an interface are stored in property tree structures, making dynamic changes to the components possible. Data bindings between subtrees representing components and sets of data from industrial and other sources allows for designs that scale with the availability of the data.Type: GrantFiled: September 18, 2018Date of Patent: March 17, 2020Assignee: Inductive Automation, LLCInventors: Carl Reuben Gould, Perry Linn Arellano-Jones
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Patent number: 10592261Abstract: Systems and methods are provided for automating user input using onscreen content. For example, a method includes receiving a selection of a first screen capture image representing a screen captured on a mobile device associated with a user, the first image having a first timestamp. The method also includes determining, using a data store of images of previously captured screens of the mobile device, a reference image from the data store that has a timestamp prior to the first timestamp, identifying a plurality of images in the data store that have respective timestamps between the timestamp for the reference image and the first timestamp, and providing the reference image, the plurality of images, and the first image to the mobile device.Type: GrantFiled: April 1, 2019Date of Patent: March 17, 2020Assignee: GOOGLE LLCInventors: Matthew Sharifi, David Petrou
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Patent number: 10592262Abstract: Techniques are described for automatically managing shared computing environments, such as a shared computing environment made available by a provider entity for simultaneous use by multiple third-party clients in exchange for fees. The functionality provided by a shared computing environment may have various forms, including in some situations to enable a client to execute a client-provided software program within the shared computing environment. The managing of shared computing environments may include performing various automated operations, including monitoring operational performance of particular shared computing environments and the use of shared computing environments by particular clients, and using information from the monitoring to provide additional functionality to the clients and/or to the providers of the shared computing environments.Type: GrantFiled: June 27, 2011Date of Patent: March 17, 2020Assignee: Amazon Technologies, INC.Inventors: William Alexander Strand, David C. Yanacek
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Patent number: 10592263Abstract: The subject disclosure is directed towards a technology for efficiently emulating program code that is protected by one or more various code virtualization techniques to detect the presence of malware. An emulation engine emulates a program containing a mix of native code, custom (e.g., virtualized obfuscated) code, and at least one emulator and/or interpreter that understands the custom code, by building a custom emulation component that is built by detecting and analyzing the internal emulator or interpreter. The custom emulation component may access a translation table built from the analysis, and also may simplify a plurality of instructions in the program into a lesser number of instructions in an intermediate language used for emulation.Type: GrantFiled: March 27, 2015Date of Patent: March 17, 2020Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Xun Wang, Adrian Emil Stepan, Timothy David Ebringer
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Patent number: 10592264Abstract: A method may include generating, from an expression, an expression tree including an arithmetic operation and conversion operations each converting an operand of the arithmetic operation from an initial decimal format to an optimized decimal format. The initial decimal format may include a shape. The method may further include at runtime, evaluating the arithmetic operation with initial operands represented in the initial decimal format, and specializing one of the conversion operations according to the shape of the corresponding initial operand.Type: GrantFiled: May 16, 2018Date of Patent: March 17, 2020Assignee: Oracle International CorporationInventors: Alexey Karyakin, Laurent Daynes
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Patent number: 10592265Abstract: An application execution apparatus that is capable of preventing display of an incomplete image. A virtual machine controls an installed application. A reference unit refers to attribute information showing whether an application draws a background of an image when the application draws the image. And a setting unit sets so that the virtual machine draws the background when it is not set that the application draws the background of the image to the attribute information.Type: GrantFiled: July 24, 2017Date of Patent: March 17, 2020Assignee: CANON KABUSHIKI KAISHAInventor: Masao Akuzawa
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Patent number: 10592266Abstract: A method and apparatus are disclosed of monitoring a number of virtual machines operating in an enterprise network. One example method of operation may include identifying a number of virtual machines currently operating in an enterprise network and determining performance metrics for each of the virtual machines. The method may also include identifying at least one candidate virtual machine from the virtual machines to optimize its active application load and modifying the candidate virtual machine to change its active application load.Type: GrantFiled: April 30, 2015Date of Patent: March 17, 2020Assignee: OPEN INVENTION NETWORK LLCInventor: John Michael Suit
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Patent number: 10592267Abstract: Mechanisms to protect the integrity of a data structure that is traversed to locate protected memory pages are provided. Leaf nodes of the data structure store mappings that indicate which memory pages are protected. Both the pages indicated by the mappings and the pages that store the data structure are monitored by a tracing service that sends a notification to the hypervisor when a write to a traced page occurs. When system software receives such a notification, the system software traverses the data structure to determine whether any of the memory pages of the data structure is the traced page that was written to. If so, the alert action for that page is performed. If not, the system software determines whether any of the mappings in the leaf nodes include such a page and, if so, the alert action for that page is performed.Type: GrantFiled: January 10, 2017Date of Patent: March 17, 2020Assignee: VMware, Inc.Inventors: David Dunn, Alok Nemchand Kataria, Wei Xu, Jeffrey W. Sheldon
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Patent number: 10592268Abstract: The management computer has a memory which stores management information and management programs, and a CPU which refers to the management information and executes the management programs; the management information includes storage management information for allowing determination as to whether the plurality of storage resources can be paired in a redundant configuration, and couplable configuration management information for determining whether the plurality of storage resources and the plurality of server resources can be connected to each other; and when the CPU deploys a virtual machine, the CPU first determines, by reference to the storage management information, storage resources to be paired in a redundant configuration, then selects, by reference to the couplable configuration management information, server resources each of which can be connected to a respective one of the storage resources that are to be paired in a redundant configuration, and pairs the selected server resources in the redundant cType: GrantFiled: April 6, 2015Date of Patent: March 17, 2020Assignee: Hitachi, Ltd.Inventors: Hiroshi Nasu, Tomohiro Kawaguchi, Yoshinori Ohira, Shunji Kawamura
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Patent number: 10592269Abstract: A system for providing dynamic code deployment and versioning is provided. The system may be configured to receive a first request to execute a newer program code on a virtual compute system, determine, based on the first request, that the newer program code is a newer version of an older program code loaded onto an existing container on a virtual machine instance on the virtual compute system, initiate a download of the newer program code onto a second container on the same virtual machine instance, and causing the first request to be processed with the older program code in the existing container.Type: GrantFiled: July 24, 2017Date of Patent: March 17, 2020Assignee: Amazon Technologies, Inc.Inventors: Timothy Allen Wagner, Sean Philip Reque, Derek Steven Manwaring, Xin Zhao, Dylan Chandler Thomas
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Patent number: 10592270Abstract: The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.Type: GrantFiled: October 16, 2017Date of Patent: March 17, 2020Assignee: Infineon Technologies AGInventors: Simon Brewerton, Glenn Farrall, Neil Hastie, Frank Hellwig, Richard Knight, Antonio Vilela
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Patent number: 10592271Abstract: Methods and systems for a virtual machine environment are provided. One method includes allocating a memory for storing a dirty pages data structure for tracking writes to a virtual machine memory by an adapter coupled to a computing device and shared by a plurality of virtual machines; initiating a tracking operation by the adapter or a virtual function driver to track writes to the virtual memory; providing access to the dirty pages data structure in response to a query command, while the adapter or the virtual function driver tracks writes to the virtual machine memory; and providing a number of dirty pages within the dirty pages data structure and a pointer the dirty pages data structure by the adapter or the virtual function driver.Type: GrantFiled: March 5, 2018Date of Patent: March 17, 2020Assignee: Cavium, LLCInventors: Merav Sicron, Rafi Shalom
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Patent number: 10592272Abstract: Embodiments of the present invention provide memory optimization by phase-dependent data residency. Application programs are profiled a priori or in real time for temporal memory usage. Memory regions such as initialization data are proactively removed from memory when the application transitions to a new phase. A hypervisor monitors application activity and coordinates the removal of memory regions that are no longer needed by the application. Additionally, memory regions that are anticipated to be needed in the future are proactively preloaded.Type: GrantFiled: March 4, 2019Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Peter D. Bain, Peter D. Shipton
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Patent number: 10592273Abstract: A method and apparatus are provided in which a source and target perform bidirectional forwarding of traffic while a migration guest is being transferred from the source to the target. In some examples, the migration guest is exposed to the impending migration and takes an action in response. A virtual network programming controller informs other devices in the network of the change, such that those devices may communicate directly with the migration guest on the target host. According to some examples, an “other” virtual network device in communication with the controller and the target host facilitates the seamless migration. In such examples, the forwarding may be performed only until the other virtual machine receives an incoming packet from the target host, and then the other virtual machine resumes communication with the migration guest on the target host.Type: GrantFiled: March 16, 2018Date of Patent: March 17, 2020Assignee: Google LLCInventors: Brian Matthew Fahs, Jinnah Dylan Hosein, Venkatesh Babu Chitlur Srinivasa, Guy Shefner, Roy Donald Bryant, Uday Ramakrishna Naik, Francis Edward Swiderski, III, Nan Hua
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Patent number: 10592274Abstract: This computer system includes: at least one computer having a memory and a plurality of CPU cores; and a storage sub device having a plurality of logical storage units configured using storage devices. In the computer, a plurality of queues are configured in the memory, and at least one of the plurality of CPU cores is assigned to each of the plurality of queues. The queue is enqueued with an I/O command dispatched from a CPU core, to which the queue is assigned, to a logical storage unit. The computer system has access control information including information concerning whether to accept or refuse access from each queue to each logical storage unit.Type: GrantFiled: October 26, 2015Date of Patent: March 17, 2020Assignee: HITACHI, LTD.Inventors: Katsuto Sato, Tetsuro Honmura
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Patent number: 10592275Abstract: A parallel processing architecture includes a CPU, a task pool populated by the CPU, and a plurality of autonomous co-processing cells each having an agent configured to proactively interrogate the task pool to retrieve tasks appropriate for a particular co-processor. Each co-processor communicates with the task pool through a switching fabric, which facilitates connections for data transfer and arbitration between all system resources. Each co-processor notifies the task pool when a task or task thread is completed, whereupon the task pool notifies the CPU.Type: GrantFiled: December 22, 2017Date of Patent: March 17, 2020Assignee: Swarm Technology LLCInventor: Alfonso Iniguez
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Patent number: 10592276Abstract: Some computing devices have limited resources such as, for example, battery power. When a user ceases to interact with an application, execution of the application can be moved to background and the application can be paused. During the time period in which the application is paused, the application consumes no CPU cycles because executing managed threads of the paused application are stopped, and native threads are prevented from running using asynchronous procedure calls.Type: GrantFiled: June 22, 2018Date of Patent: March 17, 2020Assignee: Microsoft Technology Licensing, LLCInventors: Abhinaba Basu, Jan Kotas
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Patent number: 10592277Abstract: In accordance with an embodiment, described herein is a system and method for determining the migration success of an application (e.g., a batch application) from a second computing platform (e.g., a mainframe platform) to a first computing platform (e.g., an open platform). A first database associated with the first computing platform and a second database associated with the second computing platform can include the same data baseline. A set of triggers can be created on each database to capture database modification events generated by the execution of a job associated with the application on each computing platform, and to store the database modification events in a table in each database. The database modification events from each computing platform can be downloaded and compared to determine the success of the application migration.Type: GrantFiled: July 26, 2017Date of Patent: March 17, 2020Assignee: ORACLE INTERNATIONAL CORPORATIONInventors: Wade (Weixuan) Zhang, Hui Shen, Fangzhi Tang, Weiguo Zhu
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Patent number: 10592278Abstract: In one embodiment, a computing device detects an event corresponding to a change in a graphical user interface displayed by the computing device; the computing device identifies at least one operation based on the detected event; the computing device determines a state of the identified operation; the computing device also defers the identified operation based at least in part on the determined state.Type: GrantFiled: March 15, 2013Date of Patent: March 17, 2020Assignee: Facebook, Inc.Inventors: Qixing Du, Kang Zhang
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Patent number: 10592279Abstract: A method and processing apparatus for accelerating program processing is provided that includes a plurality of processors configured to process a plurality of tasks of a program and a controller. The controller is configured to determine, from the plurality of tasks being processed by the plurality of processors, a task being processed on a first processor to be a lagging task causing a delay in execution of one or more other tasks of the plurality of tasks. The controller is further configured to provide the determined lagging task to a second processor to be executed by the second processor to accelerate execution of the lagging task.Type: GrantFiled: June 23, 2016Date of Patent: March 17, 2020Assignee: ADVANCED MICRO DEVICES, INC.Inventors: Arkaprava Basu, Dmitri Yudanov, David A. Roberts, Mitesh R. Meswani, Sergey Blagodurov
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Patent number: 10592280Abstract: A scheduler of a batch job management service determines that a set of resources a client is insufficient to execute one or more jobs. The scheduler prepares a multi-dimensional statistical representation of resource requirements of the jobs, and transmits it to a resource controller. The resource controller uses the multi-dimensional representation and resource usage state information to make resource allocation change decisions.Type: GrantFiled: November 23, 2016Date of Patent: March 17, 2020Assignee: Amazon Technologies, Inc.Inventors: Dougal Stuart Ballantyne, James Edward Kinney, Jr., Aswin Damodar, Chetan Hosmani, Rejith George Joseph, Chris William Ramsey, Kiuk Chung, Jason Roy Rupard
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Patent number: 10592281Abstract: A wait optimizer circuit can be coupled to a processor to monitor an entry of a virtual CPU (vCPU) into a wait mode to acquire a ticket lock. The wait optimizer can introduce an amount of delay, while the vCPU is in the wait mode, with an assumption that the spinlock may be resolved before sending a wake up signal to the processor for rescheduling. The wait optimizer can also record a time stamp only for a first entry of the vCPU from a plurality of entries into the wait mode within a window of time. The time stamps for vCPUs contending for the same ticket lock can be used by a hypervisor executing on the processor for rescheduling the vCPUs.Type: GrantFiled: September 28, 2017Date of Patent: March 17, 2020Assignee: Amazon Technologies, Inc.Inventor: Ali Ghassan Saidi
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Patent number: 10592282Abstract: The technology disclosed relates to providing strong ordering in multi-stage processing of near real-time (NRT) data streams. In particular, it relates to maintaining current batch-stage information for a batch at a grid-scheduler in communication with a grid-coordinator that controls dispatch of batch-units to the physical threads for a batch-stage. This includes operating a computing grid, and queuing data from the NRT data streams as batches in pipelines for processing over multiple stages in the computing grid.Type: GrantFiled: January 28, 2019Date of Patent: March 17, 2020Assignee: salesforce.com, inc.Inventors: Elden Bishop, Jeffrey Chao
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Patent number: 10592283Abstract: A computer-implemented method mitigates distractions that are provided by a computer system in order to improve an overall functionality of the computer system. One or more processors identify a task T that has a completion deadline, where task T is performed on a computer system. The processor(s) identify one or more activities At that are required to complete task T, as well as a dedicated focus of attention time Ft that is required of a user to perform the activities At. The processor(s) monitor activities of the user to determine a focus of attention time Fi for each activity Ai performed by the user, and accumulate the focus of attention time Fi for activities into a bucket for Ft and a bucket not for Ft. The processor(s) then alter a functionality of the computer system in order to improve an overall functionality of the computer system when performing task T.Type: GrantFiled: November 21, 2017Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Al Chakra, Jonathan Dunne, Liam S. Harpur, Asima Silva
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Patent number: 10592284Abstract: The system and method generally relate to reducing heat dissipated within a data center, and more particularly, to a system and method for reducing heat dissipated within a data center through service level agreement analysis, and resultant reprioritization of jobs to maximize energy efficiency. A computer implemented method includes performing a service level agreement (SLA) analysis for one or more currently processing or scheduled processing jobs of a data center using a processor of a computer device. Additionally, the method includes identifying one or more candidate processing jobs for a schedule modification from amongst the one or more currently processing or scheduled processing jobs using the processor of the computer device. Further, the method includes performing the schedule modification for at least one of the one or more candidate processing jobs using the processor of the computer device.Type: GrantFiled: July 31, 2018Date of Patent: March 17, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Christopher J. Dawson, Vincenzo V. Di Luoffo, Rick A. Hamilton, II, Michael D. Kendzierski
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Patent number: 10592285Abstract: An information handling system includes a processor complex with a root complex that provides N serial data lanes, where N is an integer. The information handling system also includes boot process logic that determines that a device is coupled to X of the serial data lanes, where X is an integer less than N, determines that no device is coupled to Y of the serial data lanes, where Y is an integer less than or equal to N?X, and allocates a portion of bus resources of the root complex to the device, the portion being greater (X+Y)/N.Type: GrantFiled: May 31, 2017Date of Patent: March 17, 2020Assignee: Dell Products, LPInventors: John C. Beckett, Robert W. Hormuth
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Patent number: 10592286Abstract: Methods and systems for implementing a highly available distributed queue using replicated messages are disclosed. An enqueue request is received from a client at a particular queue host of a plurality of queue hosts. The enqueue request comprises a message and a replica count greater than one. One or more copies of a replication request are sent from the particular queue host to one or more additional queue hosts. The replication request comprises the message. The quantity of copies of the replication request is determined based at least in part on the replica count. An initial replica of the message is enqueued at the particular queue host. One or more additional replicas of the message are enqueued at the one or more additional queue hosts. A quantity of the one or more additional replicas is determined based at least in part on the replica count.Type: GrantFiled: July 13, 2018Date of Patent: March 17, 2020Assignee: Amazon Technologies, Inc.Inventors: Andrew Ross Evenson, Ayan Kumar
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Patent number: 10592287Abstract: Implementations for a user interface for MapReduce job are disclosed. A method of the disclosure includes receiving a request to submit a MapReduce job to a cluster and providing a first graphical user interface (GUI) to input a first set of arguments and first argument values for a first portion of the arguments. The method may include receiving, from the first GUI, the first argument values and a second portion of the arguments, associated with a configuration of the cluster and without a corresponding argument value. The method may provide a second GUI that is to display the arguments, first argument values, and allow for a selection of second argument values for the second portion of the arguments. In response to a selection, the method may execute the MapReduce job in view of the first argument values from the first GUI and the second argument values from the second GUI.Type: GrantFiled: November 20, 2015Date of Patent: March 17, 2020Assignee: Red Hat, Inc.Inventor: Ethan Gafford
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Patent number: 10592288Abstract: A computing system includes a computer in communication with a tiered storage system. The computing system identifies a set of data transferring to a storage tier within the storage system. The computing system identifies a program to which the data set is allocated and determines to increase or reduce resources of the computer allocated to the program, based on the set of data transferring to the storage tier. The computing system discontinues transferring the set of data to the storage tier if a resource allocated to the program cannot be increased.Type: GrantFiled: October 16, 2018Date of Patent: March 17, 2020Assignee: International Business Machines CorporationInventors: Rahul M. Fiske, Akshat Mithal, Sandeep R. Patil, Subhojit Roy