Abstract: Continuous development pipeline systems and in-field synthetic performance test systems are interlocked to provide for automated control of promotion of program code elements within the development pipeline and in the deployment environment using relative comparative performance values rather than absolute performance thresholds, in order to better accommodate “last mile” variations in client device conditions.

Abstract: Methods and systems for detecting anomalous function execution in a program, such as a video game or simulation program, are described herein. Certain methods attempt to isolate and score functions that behave in a particular manner that is deemed to be problematic within a repetitive program. Other methods can use the repetitive nature of the program to directly compare and isolate problematic functions.

Abstract: A computer-implemented automated review method for transaction and datasource configuration source code files seeking to access a data store comprises the steps of receiving a request to review configuration source code files seeking to access the data store; checking the configuration source code files for a definition of a transaction manager; setting an issue flag if the configuration source code files do not include the definition of the transaction manager; checking the configuration source code files to determine whether a transaction definition is at an outer boundary of a service object or a method; setting the issue flag if the transaction definition does not appear before the start of the service object class or method definition; reviewing the status of the issue flag; issuing a halt signal if the issue flag is set; and issuing a proceed signal if the issue flag is not set.

Abstract: This invention relates to generating benchmarks without the need for executing the application on a specific benchmarking platform or by testing the application against known inputs and outputs. Instead, the system, in an embodiment, allows for source code comparisons to known systems to predict performance. The benchmarking can be done for varying deployment platforms and various usage patterns. The source code comparison process allows for fast performance prediction by using a distance vector.

Abstract: A method for firmware debug trace capture includes creating a hand-off block (“HOB”), capturing first debug trace statements during a boot sequence of a computer and writing the first debug trace statements to the HOB. A trace memory buffer can be created and the first debug trace statements can be copied from the HOB to the trace memory buffer. Second debug trace statements are captured during the boot sequence and appended to the trace memory buffer. In some configurations, the first debug trace statements can be written to the HOB during the pre-Extensible Firmware Interface initialization (“PEI”) phase of the boot sequence and the second debug trace statements can be written to the trace memory buffer during the driver execution (“DXE”) phase of the boot sequence.

Abstract: In an embodiment, a system is configured to replay and/or reconstruct execution events and system states in real time or substantially in real time starting from the point when execution of a target program has stopped to the point when the user desires to step through the target program's execution in order to debug the software. In an embodiment, a system is configured to efficiently collect trace data that is sufficient to reconstruct the state of a computer system at any point of time from the start of execution to the time execution was stopped. Efficient and effective debugging of the software can be performed using embodiments of the disclosed methods, systems, and devices.

Abstract: A method includes associating an associated processor address register with a predetermined operation, invoking an instruction including a reference to a referenced processor address register, and, if the referenced processor address register is the associated processor address register, performing the predetermined operation.

Abstract: Presenting historical state associated with prior execution of an entity. Based on replaying segment(s) of execution of an entity based on a trace, embodiments could present an indication of whether a value of a code element is, at a first execution time point, unknown, known, previously known, and/or known in the future. Additionally, or alternatively, embodiments could present an indication of a value relied upon by simulated execution of a function at a second execution time point, along with an indication of a timing of knowledge of the value in relation to the second execution time point. Additionally, or alternatively, embodiments could present an indication that a return value of a function would be known if the function had executed at a third execution time point, or an indication that the return value would be unknown if the function had executed at the third execution time point.

Abstract: A device may instrument a codebase associated with a software application. The device may execute a test on the instrumented codebase as the instrumented codebase executes, wherein the instrumented codebase generates test data based on the test being executed. The device may generate, based on the test data, a live graphical model of the codebase from a composite graphical model of the codebase, wherein the composite graphical model includes historical information, associated with the codebase, mapped to a graphical model of the codebase. The device may generate an extended reality rendered view of the live graphical model. The device may provide, to an extended reality device, the extended reality rendered view of the live graphical model for display by the extended reality device.

Abstract: A device may determine probabilities for test scripts associated with a test to be executed on a software element, where a respective probability is associated with a respective test script, indicates a likelihood that the respective test script will be unsuccessful in a test cycle, and is determined based on historical test results, associated with the software element, for the respective test script. The device may generate, based on the probabilities, a test script execution order, of the test scripts, for the test cycle, and may execute, based on the test script execution order, the test on the software element in the test cycle. The device may dynamically generate, based on results for the test in the test cycle, an updated test script execution order, and may execute, based on the updated test script execution order, the test on the software element in the test cycle.

Abstract: An example system includes a processor to crawl a plurality of web pages of a web application to be tested. The processor is to also receive an intercepted input to the web application and an output from a web application associated with each crawled web page. The processor is to further detect testable elements in the intercepted input and the output. The processor is also to generate a fingerprint for each web page based on the detected testable elements. The processor is to generate a list of clusters comprising one or more similar web pages based on the fingerprints. The processor is to test a single web page from each cluster.

Abstract: System and methods for creating one or more variants of test data during various test stages are disclosed. The system and methods facilitate a user to create a primary variant for test data and to store the primary variant of the test data in a test data variant repository. Any changes performed in the test database by the user are identified by using a tracking mechanism to store one or more new variants along with a variant number with respect to the changes performed in the test database in response to the user's request. The primary variant and the new variants are accessed by the user to perform a comparative analysis and to modify the test data at any test stage.

Abstract: A method of validating a design for a graphical user interface of a motor vehicle includes creating a tentative design, and/or a few drafts or prototype for the graphical user interface. A blurred version of the tentative graphical user interface design is produced. The blurred version of the tentative graphical user interface design is tested for readability and whether the overall GUI design is suited to be perceived at a glance. If it is determined that the blurred version of the tentative graphical user interface design is not readable or understandable, then the graphical user interface is redesigned and the producing and testing steps are repeated for the redesigned graphical user interface. After the blurred graphical user interface design has been determined to be readable, then a higher fidelity graphical user interface is made.

Abstract: Automated software-testing systems and computer program products use mock software entities to perform integration testing on a microservices-based application. The mock entities emulate the behavior of other microservices or external software applications that would normally interact with the tested microservices in a production environment. The mock entities are managed by a mock server that communicates with the test system through a messaging system. The mock server determines how the mock entities should respond to the tested application's service requests by referring to test guidelines stored in a behavior store. During testing, the test system dynamically updates the behavior store in response to the tested application's service requests and to other indicators of the current state of the tested application. If the tested application interacts with the mock entities during the test as expected, the test system deems the application to have passed the integration test.

Abstract: A method for integration-testing a microservices-based application is performed by an automated software-testing system by using mock software entities. The mock entities emulate the behavior of other microservices or external software applications that would normally interact with the tested microservices in a production environment. The mock entities are managed by a mock server that communicates with the test system through a messaging system. The mock server determines how the mock entities should respond to the tested application's service requests by referring to test guidelines stored in a behavior store. During testing, the test system dynamically updates the behavior store in response to the tested application's service requests and to other indicators of the current state of the tested application. If the tested application interacts with the mock entities during the test as expected, the test system deems the application to have passed the integration test.

Abstract: A method and system for testing performance of a software product. One or more complete executions of a performance test of corresponding versions of the software product are performed. The complete executions of the performance test identifies a steady state value of each performance parameter monitored during the performance test after each performance parameter has transitioned to a steady state during the performance test. A performance profile of the software product is determined according to the complete executions of the performance test. Partial executions of the performance test of corresponding further versions of the software product are performed, each partial execution having a partial duration preceding the steady state of each performance parameter. Corresponding results of the partial executions of the performance test are estimated according to the performance profile from corresponding partial trends of each performance parameter during the partial executions of the performance test.

Abstract: Vulnerability testing of applications may include one or more of identifying a number of paths from a software application being tested, identifying a number of nodes associated with the paths, determining one or more of the paths which share one or more of the nodes, designating the paths which share the nodes as overlapping paths, and displaying the overlapping paths and the shared nodes as an interactive visualization to identify to identify optimal locations to fix one or more vulnerability findings.

Abstract: A memory access unit for handling transfers of samples in a d-dimensional array between a one of m data buses, where m?1, and k*m memories, where k?2, is disclosed. The memory access unit comprises k address calculators, each address calculator configured to receive a bus address to add a respective offset to generate a sample bus address and to generate, from the sample bus address according to an addressing scheme, a respective address in each of the d dimensions for access along one of the dimensions from the bus address according to an addressing scheme, for accessing a sample. The memory access unit comprises k sample collectors, each sample collector operable to generate a memory select for a one of the k*m memories so as to transfer the sample between a predetermined position in a bus data word and the respective one of the k*m memories.

Abstract: Short pointer mode applications are able to execute in long pointer mode environments. A plurality of actions is performed to prepare a short pointer mode application for execution in the long pointer mode environment. These actions include allocating memory for one or more in-memory short pointers of the application. The memory being allocated for an in-memory short pointer is of a size corresponding to a size of the in-memory short pointer. Further, a register is allocated for an in-register short pointer of the application. The register is allocated at a size corresponding to a long pointer mode. The size corresponding to the long pointer mode is different from the size of the in-memory short pointer.

Abstract: Provided are an apparatus, computer program product, system, and method for managing multiple regions of a non-volatile memory device. A first group of logical bands is assigned to a first memory region in which metadata will be stored and a second group of logical bands is assigned to a second memory region to which host data is written, wherein the second group of logical bands is larger than the first group of logical bands. Physical bands are mapped to the first number of logical bands and the second number of logical bands. Indication is returned to the host system of the first and second groups of logical bands assigned to the first and second memory regions, respectively. The host system directs requests for metadata to logical addresses in the first group of logical bands and directs request for file data to logical addresses in the second group of logical bands.

Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.

Abstract: A data storage device includes a memory device and a controller. The memory device includes a first buffer, a second buffer, and a backup memory block. The first buffer is an MLC block and the second buffer is an SLC block. The controller is coupled to the memory device, receives a write command to write predetermined data in the memory device and determines whether the predetermined data has to be written into different buffers. When the controller determines that the predetermined data has to be written into different buffers, the controller writes a portion of the predetermined data that has been written in one or more predetermined pages of the first buffer into the backup memory block.

Abstract: Methods and systems for reclaiming disk space via consolidation and deletion of expired snapshots are described. The expired snapshots may comprise snapshots of a virtual machine that are no longer required to be stored within a data storage domain (e.g., a cluster of data storage nodes or a cloud-based data store). In some cases, rather than storing an incremental file corresponding with a particular snapshot of the virtual machine, a full image of the particular snapshot may be generated and stored within the data storage domain. The generation of the full image may allow a chain of dependencies supporting the expired snapshots to be broken and for the expired snapshots to be deleted or consolidated. The full image of the particular snapshot may be generated using compute capacity in the cloud or may be generated locally by a storage appliance and uploaded to the data storage domain.

Abstract: A data storage device for dynamically executing the garbage-collection process is provided which includes a flash memory and a controller. The flash memory includes a plurality of blocks wherein each of the blocks includes a plurality of pages. The controller is coupled to the flash memory and is utilized to execute the garbage-collection process on the flash memory according to a number of at least one spare block in the flash memory and the number of non-spare blocks corresponding to different ratios of effective pages. The garbage-collection process is utilized for merging at least two non-spare blocks to release at least one spare block.

Abstract: To deliver up-to-date, coherent user data to applications upon request, the disclosed technology includes systems and methods for caching data and metadata after it has been synchronously loaded—for future retrieval with a page load time close to zero milliseconds. To provide this experience, data needs to be stored as locally to a user as possible, in the cache on the local device or in an edge cache located geographically nearby, for use in responding to requests. Applications which maintain caches of API results can be notified of their invalidation, and can detect the invalidation, propagate the invalidation to any further client tiers with the appropriate derivative type mapping, and refresh their cached values so that clients need not synchronously make the API requests again—ensuring that the client has access to the most up-to-date copy of data as inexpensively as possible—in terms of bandwidth and latency.

Abstract: Improving access to a cache by a processing unit. One or more previous requests to access data from a cache are stored. A current request to access data from the cache is retrieved. A determination is made whether the current request is seeking the same data from the cache as at least one of the one or more previous requests. A further determination is made whether the at least one of the one or more previous requests seeking the same data was successful in arbitrating access to a processing unit when seeking access. A next cache write access is suppressed if the at least one of previous requests seeking the same data was successful in arbitrating access to the processing unit.

Abstract: An embodiment of the invention may include a method, computer program product and system for optimizing a wide area network caching infrastructure in a file based object storage architecture. The embodiment may include creating, by a parent partition, a heat map. The embodiment may include prioritizing prefetching by multiple dependent partitions based on the heat map. In response to prioritized prefetching by the multiple dependent partitions, the embodiment may include allocating wide area network caching threads. The embodiment may include providing, by the parent partition, objects for prefetching by the multiple dependent partitions utilizing the allocated wide area network caching threads.

Abstract: A storage device uses non-volatile memory devices for caching. The storage device operates in a mode referred to herein as write-back mode. In write-back mode, a storage device responds to a request to write data by persistently writing the data to a cache in a non-volatile memory device and acknowledges to the requestor that the data is written persistently in the storage device. The acknowledgement is sent without necessarily having written the data that was requested to be written to primary storage. Instead, the data is written to primary storage later.

Abstract: A system is described for playing embedded video on the Web inside the virtual desktop. A video element, such as an HTML5 video element, in a webpage accessed through a browser in the virtual desktop can be detected and video content for the video element can be intercepted before it is decoded in the virtual desktop. The encoded video data can be transmitted to the client device. On the client device, a counterpart video rendering application can receive the transmitted video data, decode it, and render it in a window that is overlaid onto a corresponding area of the virtual desktop graphical user interface (GUI) in a client application. Headless video composition can be implemented for rendering the video on the client, giving the illusion of the video playing inside the virtual desktop, while it is actually playing on the client itself.

Abstract: Shared memory caching resolves latency issues in computing nodes associated with a cluster in a virtual computing environment. A portion of random access memory in one or more of the computing nodes is allocated for shared use by the cluster. Whenever local cache memory is unable in one of the computing nodes, a cluster neighbor cache allocated in a different computing node may be utilized as remote cache memory. Neighboring computing nodes may thus share their resources for the benefit of the cluster.

Abstract: A memory system includes: a memory module including: a first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; and a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a processor suitable for executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

Abstract: One embodiment is related to a method for redistributing cache space, comprising: determining a request by a first client of a plurality of clients for additional cache space, each of the plurality of clients being associated with a guaranteed minimum amount (MIN) and a maximum amount (MAX) of cache space; and fulfilling or denying the request based on an amount of cache space the first client currently occupies, an amount of cache space requested by the first client, and the MIN and the MAX cache space associated with the first client.

Abstract: Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.

Abstract: A microprocessor has a data-less history buffer. Operands associated with a program instructions are stored in logical registers (LREGs) which are resolvable to physical registers that are not part of the history buffer. Register re-naming maintains integrity of data dependencies for instructions processed out of program order. The history buffer has pointers (RTAGs) to the LREGs. Entries in the history buffer are grouped into ranges. A mapper has a single port associated with each LREG, and each port receives data, from a single range of entries in the history buffer. Multiple entries, one from each range, may be restored concurrently from the history buffer to the mapper.

Abstract: According to one embodiment, a magnetic disk device includes heads and a controller. The heads write data in a recording region of the magnetic disk. The controller divides in order, by a track group with a constant size, an entire region of the recording region where management regions indicating physical positions corresponding to the heads, respectively, creates the track groups so as to straddle the management regions at boundaries of the management regions, and controls writing of the data for each of the track groups. The controller assigns unique and logically consecutive numbers to the track groups and manages information on the management regions to which the track groups belong.

Abstract: A mechanism is provided for efficient coherence state modification of cached data stored in a range of addresses in a coherent data processing system in which data coherency is maintained across multiple caches. A tag search structure is maintained that identifies address tags and coherence states of cached data indexed by address tags. In response to a request from a device internal to or external from the coherence network, the tag search structure is searched to identify address tags of cached data for which the coherence state is to be modified and requests are issued in the data processing system to modify a coherence state of cached lines with the identified address tags. The request from the external device may specify a range of addresses for which a coherence state change is sought. The tag search structure may be implemented as search tree, for example.

Abstract: Techniques for virtualizing NVDIMM WPQ flushing with minimal overhead are provided. In one set of embodiments, a hypervisor of a computer system can allocate a virtual flush hint address (FHA) for a virtual machine (VM), where the virtual flush hint address is associated with one or more physical FHAs corresponding to one or more physical memory controllers of the computer system. The hypervisor can further determine whether one or more physical NVDIMMs of the computer system support WPQ flushing. If so, the hypervisor can write protect a guest physical address (GPA) to host physical address (HPA) mapping for the virtual FHA in the page tables of the computer system, thereby enabling the hypervisor to trap VM writes to the virtual FHA and propagate those write to the physical FHAs of the system.

Abstract: A method for accessing a physical region page (PRP) list includes obtaining a PRP address of a PRP list, in which the PRP address has M bits; performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain a page base address if the PRP address is within a page boundary; and performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain next PRP address pointer if the PRP address reaches the page boundary. N is an integer, and M is an integer larger than N.

Abstract: Logical to physical tables each including logical to physical address translations for first logical addresses can be stored. Logical to physical table fragments each including logical to physical address translations for second logical address can be stored. A first level index can be stored. The first level index can include a physical table address of a respective one of the logical to physical tables for each of the first logical addresses and a respective pointer to a second level index for each of the second logical addresses. The second level index can be stored and can include a physical fragment address of a respective logical to physical table fragment for each of the second logical addresses.

Abstract: A translation buffer is provided in parallel to a translation lookaside buffer (TLB) to cache translations between intermediate physical addresses (IPAs) and pointers for entries in the TLB corresponding to the IPAs. The pointers can be used to identify and invalidate only certain entries in the TLB as compared to invalidating the whole TLB.

Abstract: Cache memory for resistive switching memory modules is provided herein. The cache memory can reside on a separate DIMM from the resistive switching memory, in some embodiments, or can share a common DIMM with the resistive switching memory. Cache management protocols are provided to service read and write policies for managing interaction of data between the cache memory and the resistive switching memory. In various embodiments, memory controllers are optimized for physical characteristics of resistive switching memory, and cache management protocols can be implemented to take advantage of these characteristics.

Abstract: The present disclosure relates to a memory hierarchy for a system-in-package. An example memory hierarchy is connectable to a processor via a memory management unit arranged for translating a virtual address sent by the processor into a physical address. The memory hierarchy has a data cache memory and a memory structure having at least a L1 memory array comprising at least one cluster. The memory structure comprises a first data access controller arranged for managing one or more banks of scratchpad memory of at least one of the clusters of at least the L1 memory array, comprising a data port for receiving at least one physical address and arranged for checking at run-time, for each received physical address, bits of the physical address to see if the physical address is present in the one or more banks of the at least one cluster of at least the L1 memory array.

Abstract: According to examples, an apparatus may include a processor to address a physical memory having memory sections, in which a first set of memory sections may be shared between processes and a second set of memory sections may be specific to an individual process. The apparatus may also include a shared virtual address space register to provide translation for the first set of memory sections shared between processes and a process virtual address space register to provide translation for the second set of memory sections specific to the individual process. The translation for the second set of memory sections may be independent from the translation for the first set of memory sections.

Abstract: Provided are a computer program product, system, and method for adjusting active cache size based on cache usage. An active cache in at least one memory device caches tracks in a storage during computer system operations. An inactive cache in the at least one memory device is not available to cache tracks in the storage during the computer system operations. During caching operations in the active cache, information is gathered on cache hits to the active cache and cache hits that would occur if the inactive cache was available to cache data during the computer system operations. The gathered information is used to determine whether to configure a portion of the inactive cache as part of the active cache for use during the computer system operations.

Abstract: A method for processing addressable encrypted data representing addressable cleartext data uses an integrated circuit including a processor circuit. The method includes processing the addressable cleartext data in the processor circuit without storing said cleartext data outside the processor circuit.

Abstract: Methods and systems for securing memory within a computing fabric are disclosed. One method includes allocating memory of one or more host computing systems in the computing fabric to a partition, the partition included among a plurality of partitions, the computing fabric including a hypervisor installed on the one or more host computing platforms and managing interactions among the plurality of partitions. The method includes defining an address range associated with the memory allocated to the partition, receiving a memory operation including an address within the address range, and, based on the memory operation including an address within the address range, issuing, by the hypervisor, an indication that the memory operation is occurring at an encrypted memory location. The method also includes performing the memory operation, and performing an encryption operation on data associated with the memory operation.

Abstract: In one embodiment, an apparatus includes: at least one core to execute instructions, the at least one core formed on a semiconductor die; a first memory formed on the semiconductor die, the first memory comprising a non-volatile random access memory, the first memory to store a first entry to be a monotonic counter, the first entry including a value field and a status field; and a control circuit, wherein the control circuit is to enable access to the first entry if the apparatus is in a secure mode and otherwise prevent the access to the first entry. Other embodiments are described and claimed.

Abstract: Secure memory allocation technologies are described. A processor includes a processor core and a memory controller that is coupled between the processor core and main memory. The main memory comprises a protected region including secured pages. The processor, in response to a content copy instruction, is to initialize a target page in the protected region of an application address space. The processor, in response to the content copy instruction, is also to select content of a source page in the protected region to be copied. The processor, in response to the content copy instruction, is also to copy the selected content to the target page in the protected region of the application address space.

Abstract: Memory blocks are associated with each memory level of a hierarchy of memory levels. Each memory block has a matching key capability (MaKC). The MaKC of a memory block governs access to the memory block, in accordance with permissions specified by the MaKC. The MaKC of a memory block can uniquely identify the memory block across the hierarchy of memory levels, and can be globally unique across the memory blocks. An MaKC of a memory block includes a block protection key (BPK) stored with the memory block, and an execution protection key (EPK). If a provided EPK for a memory block matches the memory block's BPK upon comparison, access to the memory block is allowed according to the permissions specified by the MaKC.

Abstract: Technologies are disclosed herein that allow configuration of firmware by a firmware configuration device connected to a target computer. The firmware configuration device may emulate keystroke and/or mouse movement data to transmit firmware configuration data to the target computer. The target computer can also transmit status information and/or commands through keyboard status light signals.