Patents Issued in December 24, 2020
  • Publication number: 20200402537
    Abstract: The present disclosure describes techniques of presenting audio/video (AV) files. The disclosed techniques include displaying a first interface, wherein the first interface comprises a list of a plurality of AV files and an editing area; generating a plot graph based at least in part on an input by a first user via the first interface, wherein the plot graph has a directed structure, and the at least one first type of AV file and the at least one second type of AV file are associated with different nodes of the plot graph; playing a first type of AV file; detecting that a preset instruction is received in response to determining that a playing progress of the first type of AV file reaches a first predetermined position; and playing another first type of AV file or a second type of AV file based on the preset instruction.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 24, 2020
    Inventors: Huyang SUN, Zhaoxin TAN, Weijia Li, Jianqiang DING, Yifei PEI, Yuxuan GAO, Kan HU, Xiaofeng JI, Chaoran LI, Fuling CHEN, Dejun SHAN
  • Publication number: 20200402538
    Abstract: Systems and methods for media aggregation are disclosed herein. The system includes a media system that can transform media items into one aggregated media item. A synchronization component synchronizes media items with respect to time. The synchronized media items can be analyzed and transformed into an aggregated media item for storage and/or display. In one implementation, the aggregated media item is capable of being displayed in multiple ways to create an enhanced and customizable viewing and/or listening experience.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Yossi Matias, Matthew Sharifi, Thomas Bugnon, Dominik Roblek, Annie Chen
  • Publication number: 20200402539
    Abstract: The present disclosure describes techniques for playing videos. The disclosed techniques include obtaining a total duration and a playing duration of a first video segment; identifying a first video node corresponding to the first video segment and a first directing message associated with the first video node in a video playing plot graph, wherein the video playing plot graph is pre-generated and comprises a plurality of video nodes, and each video node corresponds to a video segment and is associated with a directing message comprising information related to a second video node; determining the second video node based on the first directing message in response to a determination that a difference between the total duration and the playing duration is equal to a predetermined amount; obtaining the second video segment based on the second video node; and playing the second video segment continuously once the first video segment is finished.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 24, 2020
    Inventors: Jianqiang Ding, Zhaoxin Tan
  • Publication number: 20200402540
    Abstract: A video player includes the user interface comprising: a video display; a texture strip visually representing a series of frames of a video, the texture strip comprising a sequence of textured frame representations, each textured frame representation in sequence of textured frame representations representing a corresponding frame from a series of frames; a control to allow a user to use the texture strip to seek frames in the series of frames in a random manner. An input is received via the control, the input including an indication of a selection of a location in the texture strip, the location in the texture strip having a corresponding temporal location in the series of frames. Based on the input, a frame selected from the series of frames is displayed in the video display, the selected frame located at the corresponding temporal location in the series of frames.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventor: Thomas S. Gilley
  • Publication number: 20200402541
    Abstract: Methods and systems for improving the interactivity of media content. The methods and systems are particularly applicable to the e-learning space, which features unique problems in engaging with users, maintaining that engagement, and allowing users to alter media assets to their specific needs. To address these issues, as well as improving interactivity of media assets generally, the methods and systems described herein provide for annotation and truncation of media assets. More particularly, the methods and systems described herein provide features such as annotation guidance and video condensation.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 24, 2020
    Applicant: Sage Learning Inc.
    Inventors: Morgan Bruce DeWitt Talbot, Vishal Vijay Punwani, Emma Kathryn Giles
  • Publication number: 20200402542
    Abstract: A method and system for recording and playing a video are provided. The method includes receiving an input, from a first user, to start recording of the video. An orientation of a recording device is detected for a plurality of frames while recording the video. An input to stop recording of the video is then received. The video is stored in a video file and the orientation of the recording device for the plurality of frames is stored as metadata associated with the video file. The playing includes receiving an input to play the video from a second user. An orientation of a playing device is detected. The video file is accessed, and the video is played using the metadata, the input received from the second user, and the orientation of the playing device. The video file is used to control speed and direction of the video.
    Type: Application
    Filed: September 9, 2020
    Publication date: December 24, 2020
    Inventors: Celia Mourkogiannis, Guillaume Sabran, Jacob Trefethen, Luis Tueros-Grimaldo
  • Publication number: 20200402543
    Abstract: Provided are a video recording method and apparatus. The video recording method includes: in response to detecting a resume recording instruction, determining duration of a video coded by a video coder, and setting playback progress of an audio player to the duration, where the resume recording instruction is used for instructing to continue collecting video data and continue playing target audio data by using the audio player; starting the audio player, where the video coder is started before the audio player; in the case of playing the target audio data to the playback progress, in response to collecting the video data, transmitting the collected video data to the video coder so that the video coder codes the collected video data.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Inventor: Yi Zhou
  • Publication number: 20200402544
    Abstract: Methods of creating and recreating a mix instructions file for mixing two or more music tracks are disclosed including the comparison of the music tracks used in creation and recreation, respectively. If possible and necessary, the recreation music tracks may be adjusted to correspond better to the creation music tracks.
    Type: Application
    Filed: December 6, 2018
    Publication date: December 24, 2020
    Inventors: Svante STADLER, Daniel Wallner
  • Publication number: 20200402545
    Abstract: An electrical feed-through, such as a PCB connector, involves at least one positioning protrusion protruding from a main body, and may further include multiple positioning protrusions protruding in respective directions from the main body. A data storage device employing such a feed-through includes an enclosure base with which the feed-through is coupled. The base includes an annular recessed surface surrounding an aperture that is encompassed by the feed-through and is at a first level, and at least one recessed positioning surface at a higher level than the first level, and extending in a direction away from the annular recessed surface. The positioning protrusion of the electrical feed-through contacts the recessed positioning surface of the base, such that the position of the feed-through is constrained by the recessed positioning surface.
    Type: Application
    Filed: July 20, 2020
    Publication date: December 24, 2020
    Inventors: Jiro Kaneko, Yuta Onobu
  • Publication number: 20200402546
    Abstract: A method for making a hard disk drive is disclosed. The method includes forming a base deck comprising an aluminum alloy via vacuum casting. The method further includes subjecting the base deck to hot isostatic pressing. The method further includes welding a cover to the base deck.
    Type: Application
    Filed: June 3, 2020
    Publication date: December 24, 2020
    Inventor: Jerome Thomas Coffey
  • Publication number: 20200402547
    Abstract: Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).
    Type: Application
    Filed: June 21, 2019
    Publication date: December 24, 2020
    Inventors: Yogesh Sharma, Atsushi Morishima, Yoshihisa Fukushima
  • Publication number: 20200402548
    Abstract: A semiconductor storage device includes a first word line electrically connected to a first memory cell, a second word line electrically connected to a second memory cell, and a voltage generation circuit configured to supply a first voltage to a first line electrically connected to the first word line and a second voltage to a second line electrically connected to the second word line. The voltage generation circuit includes a first regulator configured to output the first voltage to the first line and output a first signal according to the first voltage, a second regulator configured to output the second voltage to the second line and output a second signal according to the second voltage, and a switch circuit configured to open or close an electrically conductive path between the first line and the second line, based on at least one of the first signal and the second signal.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Inventors: Hiroshi YOSHIHARA, Tetsuya AMANO
  • Publication number: 20200402549
    Abstract: A memory circuit may include a memory array, and the memory array may include a plurality of data columns. The plurality of data columns may be configured to store data bits and provide data signals when selected by a read operation. The memory array may also include one or more reference columns distributed in the memory array and configured to provide a reference signal. The reference signal may track with process, voltage, and temperature variations that are specific to the memory array, and may be used to remove a common signal component and adjust the signal level to distinguish between logic 0 and logic 1 data signals.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 24, 2020
    Applicant: Applied Materials, Inc.
    Inventors: Frank Tzen-Wen Guo, Bhuvaneshwari Ayyagari-Sangamalli, Angada B. Sachid, Blessy Alexander
  • Publication number: 20200402550
    Abstract: A semiconductor storage device includes a sense amplifier configured to read and program data in memory cells, a first latch circuit to store read data or program data, a second latch circuit to store the first data transferred from the first latch circuit or the second data before the second data is transferred into the first latch circuit, an input/output circuit to output the first data stored in the second latch circuit and to transfer the second data received thereby to the second latch circuit, and a control circuit. Upon receiving a read command while the control circuit is performing a program operation on program data stored in second latch circuit, the control circuit interrupts the program operation to perform the read operation and resumes the program operation on the program data in response to a resume write command sequence that does not include the program data.
    Type: Application
    Filed: August 5, 2020
    Publication date: December 24, 2020
    Inventors: Junichi SATO, Akio SUGAHARA
  • Publication number: 20200402551
    Abstract: A method is for operating a nonvolatile dual in-line memory module (NVDIMM). The NVDIMM includes a dynamic random access memory (DRAM) and a nonvolatile memory (NVM) device, the DRAM including a first input/output (I/O) port and a second I/O port, and the second I/O port connected to the NVM device. The method includes receiving an externally supplied command signal denoting a read/write command and a transfer mode, driving a multiplexer to select at least one of the first and second I/O ports according to the transfer mode of the command signal, and reading or writing data according to the read/write command of the command signal in at least one of the DRAM and NVM device using the at least one of the first and second I/O ports selected by driving the multiplexer.
    Type: Application
    Filed: March 17, 2020
    Publication date: December 24, 2020
    Inventors: SUNYOUNG LIM, JAEGON LEE
  • Publication number: 20200402552
    Abstract: A CAM device includes a cell array including a plurality of CAM cells, a search line driving circuit connected to the cell array through a plurality of search lines, and a match line sensing circuit connected to the cell array through a plurality of match lines. Each of the CAM cells includes a first half CAM cell connected to a first match line and a second half CAM cell connected to a second match line different from the first match line. The first match line connected to the first half CAM cell is precharged in a first phase, and the second match line connected to the second half CAM cell is precharged in a second phase after the first phase. Thus, power consumption of the CAM device is reduced and delay is minimized.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 24, 2020
    Applicant: Korea University Research and Business Foundation
    Inventors: Jongsun PARK, Woong CHOI, Geon KO
  • Publication number: 20200402553
    Abstract: A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The control circuit is configured to control the non-volatile memory structure to perform memory operations by generating and applying a set of control signals to the non-volatile memory structure The control circuit includes a programmable and reprogrammable microcontroller. For example, the microcontroller includes one or more processors that are programmed using software (e.g., firmware). The use of a programmable processor and software allows for updates and changes to be made easily. Additionally, to reduce the time taken to make some calculations, the microcontroller also includes one or more combinational logic circuits that are in communication with the one or more processors.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Pao-Ling Koh, Yuheng Zhang, Yan Li
  • Publication number: 20200402554
    Abstract: Disclosed are systems and methods involving memory-side write training to improve data valid window. In one implementation, a method for performing memory-side write training may comprise delaying a rising edge or a falling edge of a first data signal, delaying a rising edge or a falling edge of a second data signal, and aligning the two adjusted signals to reduce a window of time that the data signals are not valid and thereby improve or optimize the data valid window (DVW) of a memory array. According to implementations herein, various edges of data signals and clock signals may be adjusted or delayed via dedicated trim cells or circuitry present in the data paths located on the memory side of a system.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: Agatino Massimo Maccarrone, Luigi Pilolli, Ali Feiz Zarrin Ghalam, Chin Yu Chen
  • Publication number: 20200402555
    Abstract: Inventive concepts relates to a semiconductor memory device. The semiconductor memory device may include a first buffer configured to receive a first signal, a second buffer configured to receive a second signal, a detector configured to compare a first phase of the first signal received by the first buffer to a second phase of the second signal received by the second buffer and to generate a detection signal, and a corrector activated or inactivated in response to a detection signal. The corrector may be configured to correct the first signal received by the first buffer and the second signal received by the second buffer, when the corrector is activated in response to the detection signal.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hun-Dae CHOI, Hwapyong KIM
  • Publication number: 20200402556
    Abstract: A storage device including a nonvolatile memory device including memory blocks and a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line may be provided. The nonvolatile memory device and the controller may be configured to perform training on the data input and output lines by adjusting a delay of a data strobe signal sent through the data strobe line and adjust delays of the data input and output lines based on the training result.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Soong-Man SHIN, Hyungjin KIM, YoungWook KIM
  • Publication number: 20200402557
    Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Toshiyuki Sato, Shinichi Miyatake, Satoshi Yamanaka
  • Publication number: 20200402558
    Abstract: A three-terminal device is disclosed having a magnetic tunnel junction (MTJ) and a spin orbit torque (SOT) generating layer. The MTJ has a first magnetic layer, a tunnel barrier layer underlying the first magnetic layer, and a second magnetic layer underlying the tunnel barrier, wherein the SOT generating layer is directly underlying the second magnetic layer. The second magnetic layer has a shape that is non-symmetrical, such that an average magnetization of a remnant state associated with the second magnetic layer has an in-plane component that is orthogonal to a current direction in the SOT generating layer.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 24, 2020
    Inventors: TIMOTHY PHUNG, CHIRAG GARG
  • Publication number: 20200402559
    Abstract: A perpendicular spin transfer torque MRAM memory cell includes a magnetic tunnel junction stack comprising a pinned layer having a fixed direction of magnetization, a free layer having a direction of magnetization that can be switched, a tunnel barrier between the pinned layer and the free layer, a cap layer above the free layer and one or more in-stack multi-layer thermal barrier layers having multiple internal interfaces between materials. The thermal barrier layers have high enough thermal resistivity to maintain the heat generated in the memory cell and low enough electrical resistivity to not materially change the electrical resistance of the memory cell. One embodiment further includes a thermal barrier liner surrounding the free layer, pinned layer, tunnel barrier and cap layer.
    Type: Application
    Filed: July 1, 2019
    Publication date: December 24, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Goran Mihajlovic, Tiffany Santos, Michael Grobis
  • Publication number: 20200402560
    Abstract: A memory cell is disclosed which includes a conductive layer, an insulating layer disposed atop the conducting layer, a semiconductor layer disposed atop the insulating layer, a first electrode coupled to the semiconductor layer, a second electrode coupled to the semiconductor layer, wherein the first and second electrodes are separated from one another and wherein the semiconductor layer extends beyond the first and second electrodes forming a first wing, a third electrode coupled to the conductive layer, a first magnetic tunnel junction (MTJ) disposed on the first wing, and a first read electrode coupled to the first MTJ.
    Type: Application
    Filed: June 23, 2020
    Publication date: December 24, 2020
    Applicant: Purdue Research Foundation
    Inventors: Sandeep Krishna Thirumala, Sumeet Kumar Gupta, Yi-Tse Hung, Zhihong Chen
  • Publication number: 20200402561
    Abstract: A MRAM memory cell comprises a SHE layer, a magnetic bit layer with perpendicular anisotropy and an Oersted layer. The magnetic bit layer has a switchable direction of magnetization in order to store data. Data is written to the MRAM memory cell using the Spin Hall Effect so that spin current generated in the SHE layer exerts a torque on the magnetic bit layer while the Oersted layer provides heat and an Oersted field to enable deterministic switching. Data is read form the MRAM memory cell using the Anomalous Hall Effect and sensing voltage at the Oersted layer.
    Type: Application
    Filed: July 1, 2019
    Publication date: December 24, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Goran Mihajlovic, Michael Grobis
  • Publication number: 20200402562
    Abstract: Embodiments of 3D memory devices with a static random-access memory (SRAM) and fabrication methods thereof are disclosed herein. In one example, the method for operating a 3D memory device having an input/output circuit, an array of SRAM cells, and an array of 3D NAND memory strings in a same chip. The method may include transferring data through the input/output circuit to the array of SRAM cells, storing the data in the array of SRAM cells, and programming the data into the array of 3D NAND memory strings from the array of SRAM cells.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Inventors: Yue Ping Li, Chun Yuan Hou
  • Publication number: 20200402563
    Abstract: Methods, systems, and devices for digit line management for a memory array are described. A memory array may include a plate that is common to a plurality of memory cells. Each memory cell associated with the common plate may be coupled with a respective digit line. One or more memory cells common to the plate may be accessed by concurrently selecting the plate and each digit line associated with the plate. Concurrent selection of all digit lines associated with the plate may be supported by shield lines between the selected digit lines. Additionally or alternatively, selection of all digit lines associated with the plate may be supported by improved sensing schemes and related amplifier configurations.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Inventors: Xinwei Guo, Daniele Vimercati
  • Publication number: 20200402564
    Abstract: Systems and methods of dynamically calibrating memory control signals during increase of wordline voltage for memory technologies subject to charge loss are disclosed. In one aspect, an exemplary method may comprise using an internal node, such as a wordline regulator output or return feedback line or a replica of the wordline, as proxy for the local wordline voltage. In one or more further embodiments, the proxy signal may be converted to digital signal or code and even determined in the background before the signal is needed for calibration. As a function of the disclosed technology, calibration of memory control signals, such as pass voltage and wordline read-verify voltage, may be performed during increase of the wordlines voltage with no impact or penalty on read/program time.
    Type: Application
    Filed: June 19, 2019
    Publication date: December 24, 2020
    Inventor: Michele Piccardi
  • Publication number: 20200402565
    Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: Micron Technology, Inc.
    Inventors: Toshiyuki Sato, Shinichi Miyatake
  • Publication number: 20200402566
    Abstract: Apparatuses and methods for controlling the discharge of subword lines are described. The rate of discharge and/or the voltage level discharged to may be controlled. In some embodiments, a main word line may be driven to multiple low potentials to control a discharge of a subword line. In some embodiments, a first word driver line signal and/or a second word driver line signal may be reset to control a discharge of a subword line. In some embodiments, a combination of driving the main word line and the first word driver line signal and/or the second word driver line signal resetting may be used to control a discharge of the subword line.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: Micron Technology, Inc.
    Inventor: Toshiyuki Sato
  • Publication number: 20200402567
    Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.
    Type: Application
    Filed: July 2, 2020
    Publication date: December 24, 2020
    Inventors: Frederick A. Ware, John Eric Linstadt, Thomas Vogelsang
  • Publication number: 20200402568
    Abstract: Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh rate for the memory bank based on the operating temperature of the memory bank. Further, the method may include skipping at least one internal auto refresh of the memory bank in response to the operating temperature being less than or equal to a first threshold temperature. A memory device and an electronic system are also described.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Inventors: Yuan He, Yutaka Ito
  • Publication number: 20200402569
    Abstract: Methods of operating a memory device are disclosed. A method may include determining an operating temperature of a memory bank of a memory device. The method may also include adjusting at least one refresh interval for the memory bank based the operating temperature of the memory bank. Further, the method may include skipping at least one refresh of the memory bank based on at least one of the operation temperature of the memory bank and a number of active signals received at the memory bank. A memory device and an electronic system are also described.
    Type: Application
    Filed: September 11, 2019
    Publication date: December 24, 2020
    Inventors: Yuan He, Yutaka Ito
  • Publication number: 20200402570
    Abstract: A power-supply circuit for a memory includes a bitcell power-supply circuit and a bitcell power-control circuit. The bitcell power-supply circuit includes a first terminal coupled to a bitcell of the memory. The bitcell power-control circuit is coupled to the bitcell power-supply circuit, and controls the bitcell power-supply circuit in a write-assist mode to output a first voltage on the first terminal that is based on a ratio of capacitance of the bitcell and of capacitance of a charge-sharing capacitance. The bitcell power-control circuit further controls the bitcell power-supply circuit in a data-retention mode to output a second voltage on the first terminal that is about one diode drop below a voltage of a main power supply to the bitcell. The bitcell power-control circuit also controls the bitcell power-supply circuit in a power-down mode to turn off power output from the first terminal.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 24, 2020
    Inventors: Sumeer GOEL, Kiran KORATIKERE SRINIVASA, Peter Normand LABRECQUE
  • Publication number: 20200402571
    Abstract: A method of operating a memory macro includes receiving a first signal indicating a first operational mode of the memory macro, receiving a second signal indicating a second operational mode of the memory macro, generating, by a first logic circuit, a third signal and a fourth signal based on the first signal and a fifth signal thereby causing a change in the first operational mode of the memory macro, and generating, by a second logic circuit, the fifth signal and a sixth signal based on at least the second signal and thereby causing a change in the second operational mode of the memory macro. The first logic circuit is coupled to a first memory cell array and a first IO circuit. The second logic circuit is coupled to a first and second set of word line driver circuits.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Pankaj AGGARWAL, Jui-Che TSAI, Ching-Wei WU
  • Publication number: 20200402572
    Abstract: In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventors: Mahmut Sinangil, Chiting Cheng, Hung-Jen Liao, Tsung-Yung Chang
  • Publication number: 20200402573
    Abstract: A memory device includes a memory cell array comprising a plurality of memory cells wherein each of the plurality of memory cells is configured to be in a data state, and a physically unclonable function (PUF) generator. The PUF generator further includes a first sense amplifier, coupled to the plurality of memory cells, wherein while the plurality of memory cells are being accessed, the first sense amplifier is configured to compare accessing speeds of first and second memory cells of the plurality of memory cells, and based on the comparison, provide a first output signal for generating a first PUF signature.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Inventors: Chien-Chen LIN, Wei-Min CHAN, Chih-Yu LIN, Shih-Lien Linus LU, Yen-Huei CHEN
  • Publication number: 20200402574
    Abstract: Some embodiments include apparatuses having non-volatile memory cells, each of the non-volatile memory cells to store more than one bit of information; data lines, at most one of the data lines electrically coupled to each of the non-volatile memory cells; a circuit including transistors coupled to the data lines, the transistors including gates coupled to each other; and an encoder including input nodes and output nodes, the input nodes to receive input information from the data lines through the transistors, and the output nodes to provide output information having a value based on a value of the input information.
    Type: Application
    Filed: June 21, 2019
    Publication date: December 24, 2020
    Inventors: Xiaofei Wang, Dinesh Somasekhar, Clifford Ong, Eric A Karl, Zheng Guo, Gordon Carskadon
  • Publication number: 20200402575
    Abstract: A nonvolatile memory apparatus includes a plurality of cell arrays, each including a near area and a far area. A plurality of memory cells are included in the near area, and a plurality of memory cells are included in the far area. When a memory cell of the plurality of memory cells, included in a near area of at least one cell array, among the plurality of cell arrays, is selected, based on an address signal, the nonvolatile memory apparatus selects memory cells included in far areas of the remaining cell arrays based on the address signal. The nonvolatile memory apparatus performs a first read operation on the selected memory cell of the at least one cell array, and performs a second read operation on the selected memory cells of the remaining cell arrays.
    Type: Application
    Filed: January 28, 2020
    Publication date: December 24, 2020
    Applicant: SK hynix Inc.
    Inventors: Jung Hyuk YOON, In Soo LEE
  • Publication number: 20200402576
    Abstract: A nonvolatile memory apparatus may include a memory cell, a bit line control circuit, and a word line control circuit. The memory cell may be coupled between a global bit line and a global word line. During a read operation, the bit line control circuit may provide a first high voltage to the global bit line and provide a second high voltage to the global bit line when snapback of the memory cell occurs. During the read operation, the word line control circuit may provide a second read supply voltage to the global word line and provide an anneal supply voltage to the global word line when snapback of the memory cell occurs.
    Type: Application
    Filed: January 9, 2020
    Publication date: December 24, 2020
    Applicant: SK hynix Inc.
    Inventors: Moo Hui PARK, Seok Joon KANG, Jun Ho CHEON
  • Publication number: 20200402577
    Abstract: A novel memory device is provided. The memory device including a plurality of memory cells arranged in a matrix, and each of the memory cells includes a transistor and a capacitor. The transistor includes a first gate and a second gate, which include a region where they overlap with each other with a semiconductor layer therebetween. The memory device has a function of operating in a “writing mode”, a “reading mode”, a “refresh mode”, and an “NV mode”. In the “refresh mode”, data retained in the memory cell is read, and then the read data is written to the memory cell again for first time. In the “NV mode”, data retained in the memory cell is read, the read data is written to the memory cell again for second time, and then a potential at which the transistor is turned off is supplied to the second gate. The “NV mode” operation enables data to be stored for a long time even when power supply to the memory cell is stopped. The memory cell can store multilevel data.
    Type: Application
    Filed: December 13, 2018
    Publication date: December 24, 2020
    Inventors: Tatsuya ONUKI, Takanori MATSUZAKI, Kiyoshi KATO, Shunpei YAMAZAKI
  • Publication number: 20200402578
    Abstract: A flash memory of the invention has a plurality of planes, a controller, a switch unit, and a driving control circuit. The controller is configured to select at least one of the planes. The switch unit is configured to electrically connect bit lines of the unselected plane to a reference voltage. The driving control circuit is configured to commonly provide a gate select signal to select transistors of the selected planes and the unselected planes after the bit lines of the unselected plane is electrically connected to the reference voltage. Accordingly, a flash memory that can reliably seek stability of threshold distribution of memory is provided.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 24, 2020
    Applicant: Winbond Electronics Corp.
    Inventor: Sho OKABE
  • Publication number: 20200402579
    Abstract: Nonvolatile memory device includes memory cell region including first metal pad, peripheral circuit region including second metal pad, memory cell array, input current generator, operation cell array and analog-to-digital converter. Peripheral circuit region is vertically connected by first and second metal pads. Memory cell array in memory cell region includes NAND strings storing multiplicand data, wherein first ends of NAND strings are connected to bitlines and second ends of NAND strings output multiplication bits corresponding to bitwise multiplication of multiplicand data stored in NAND strings and multiplier data loaded on bitlines. Input current generator generates input currents. Operation cell array in memory cell region includes switching transistors. Gate electrodes of switching transistors are connected to second ends of NAND strings. Switching transistors selectively sum input currents based on multiplication bits to provide output currents.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Inventor: SE-HWAN PARK
  • Publication number: 20200402580
    Abstract: A method of accessing a nonvolatile memory device which includes a memory block where semiconductor layers including word lines are stacked includes receiving a write request for the memory block, determining whether the write request corresponds to one or more leading word lines, programming, in response to the write request determined as corresponding to the leading word lines, memory cells connected thereto in a first program mode, and programming, when the write request is determined as corresponding to a following word line different from the leading word lines, memory cells connected to the following word line in a second program mode. The second program mode is performed with a second program parameter including at least one of a number of program pulses, a number of program verify pulses, a program start voltage, and a program end voltage that is different from a corresponding first parameter of the first program mode.
    Type: Application
    Filed: January 8, 2020
    Publication date: December 24, 2020
    Applicants: Samsung Electronics Co., Ltd., Seoul National University R&DB Foundation
    Inventors: JIHONG KIM, KYUNGDUK LEE, YOUNG-SEOP SHIM, KIROCK KWON, MYOUNG SEOK KIM
  • Publication number: 20200402581
    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.
    Type: Application
    Filed: September 8, 2020
    Publication date: December 24, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Masanobu SHIRAKAWA, Marie TAKADA, Tsukasa TOKUTOMI, Yoshihisa KOJIMA, Kiichi TACHI
  • Publication number: 20200402582
    Abstract: A storage system comprises a controller connected to blocks of non-volatile memory cells. The memory cells can be operated as single level cell (“SLC”) memory cells or multi-level cell (“MLC”) memory cells. To increase write performance for a subset of memory cells being operated as SLC memory cells, the controller performs a deeper erase process and a weaker program process for the subset of memory cells. The weaker program process results in a programmed threshold voltage distribution that is lower than the “nominal” programmed threshold voltage distribution. Having a lower programmed threshold voltage distribution reduces the magnitude of the programming and sensing voltages needed and, therefore, shortens the time required to generate the programming and sensing voltages, and reduces power consumption.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Niles Yang, Sahil Sharma, Rohit Sehgal, Phil Reusswig
  • Publication number: 20200402583
    Abstract: A flash memory having high reliability and a method for controlling the flash memory is provided for seeking stability of memory cell threshold voltage distribution. A NAND string of the flash memory has: a source-line-side select transistor; a source-line-side dummy cell; a plurality of memory cells; a bit-line-side dummy cell; and a bit-line-side select transistor. A method for controlling the flash memory includes the following step: after erasing a selected block, programming the dummy cell of the selected block into a programmed state by applying a programming voltage to a dummy word line which is connected to the dummy cell.
    Type: Application
    Filed: June 17, 2020
    Publication date: December 24, 2020
    Applicant: Winbond Electronics Corp.
    Inventors: Kenichi ARAKAWA, Sho OKABE
  • Publication number: 20200402584
    Abstract: In a method of programming in a nonvolatile memory device including a memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, wherein the peripheral circuit region is vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory block in the memory cell region including a plurality of stacks disposed in a vertical direction is provided where the memory block includes cell strings each of which includes memory cells connected in series in the vertical direction between a source line and each of bitlines. A plurality of intermediate switching transistors disposed in a boundary portion between two adjacent stacks in the vertical direction is provided, where the intermediate switching transistors perform a switching operation to control electrical connection of the cell strings, respectively.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 24, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Yo-Han LEE
  • Publication number: 20200402585
    Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to inhibit memory cells of a first subset of memory cells from programming during each programming pulse of a first plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of a second plurality of programming pulses, inhibit memory cells of a second subset of memory cells from programming during each programming pulse of the second plurality of programming pulses and enable those memory cells for programming for at least one programming pulse of the first plurality of programming pulses, and enable memory cells of a third subset of memory cells for programming during at least one programming pulse of the first plurality of programming pulses and during at least one programming pulse of the second plurality of programming pulses.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Vishal Sarin, Allahyar Vahidimowlavi
  • Publication number: 20200402586
    Abstract: Memories having a controller configured to perform methods during programming operations including apply a first voltage level to a data line selectively connected to a selected memory cell selected, apply a lower second voltage level to a select gate connected between the data line and the memory cell, decrease the voltage level applied to the data line from the first voltage level to a third voltage level while continuing to apply the second voltage level to the select gate, increase the voltage level applied to the select gate from the second voltage level to a fourth voltage level after the voltage level of the data line settles to the third voltage level, and apply a programming voltage to the memory cell after increasing the voltage level applied to the select gate to the fourth voltage level.
    Type: Application
    Filed: September 4, 2020
    Publication date: December 24, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Violante Moschiano, Purval S. Sule, Han Liu, Andrea D'Alessandro, Pranav Kalavade, Han Zhao, Shantanu Rajwade