Abstract: In a method for spatially localizing mass-spectrometry analysis of an analyte derived from an energy event, an electrical device is used to deliver an energy event to a substrate, and the analyte produced is analyzed using mass spectrometry. Electrical signals sent to and received from the electrical device under different modes of operation are sensed and classified according to each different mode of operation. A location of the electrical device is tracked in three dimensions during the energy event, and a processor is used to perform spatial-temporal alignment of the mass-spectrometry, the determined modes of operation of the electrical device, and the tracked location of the electrical device, wherein mass spectrometry data corresponding to the determined modes of the electrical device are identified and localized within the site of the energy event. The substrate may be tissue in a surgical site, and the electrical device may be an electrocautery device.

Abstract: There is provided a technique that includes (a) forming a first film having a first thickness on an underlayer by supplying a first process gas not including oxidizing gas to a substrate, wherein the first film contains silicon, carbon, and nitrogen and does not contain oxygen, and the underlayer is exposed on a surface of the substrate and is at least one selected from the group of a conductive metal-element-containing film and a nitride film; and (b) forming a second film having a second thickness larger than the first thickness on the first film by supplying a second process gas including oxidizing gas to the substrate, wherein the second film contains silicon, oxygen, and nitrogen, and wherein in (b), oxygen atoms derived from the oxidizing gas and diffuse from a surface of the first film toward the underlayer are absorbed by the first film and the first film is modified.

Abstract: A pattern-forming method includes forming a patterned coating film on a part of a surface layer of a base. The surface layer includes regions each of which includes a material that differs from each other. A part of the regions is the part of the surface layer on which the patterned coating film is formed. The patterned coating film includes a first polymer including at an end of a main chain or a side chain thereof a group including a first functional group that is capable of bonding to an atom present in the part of the region. An atom layer is directly or indirectly formed on the surface layer of the base by a vapor deposition, after the forming of the patterned coating film.

Abstract: A method is disclosed of manufacturing a semiconductor structure comprising an (001) oriented zincblende structure group III-nitride layer, such as GaN. The layer is formed on a 3C—SiC layer on a silicon substrate. A nucleation layer is formed, recrystallized and then the zincblende structure group III-nitride layer is formed by MOVPE at temperature T3 in the range 750-1000° C., to a thickness of at least 0.5 ?m. There is also disclosed a corresponding semiconductor structure comprising a zincblende structure group III-nitride layer which, when characterized by XRD, shows that the substantial majority, or all, of the layer is formed of zincblende structure group III-nitride in preference to wurtzite structure group III-nitride.

Abstract: A method for forming a semiconductor device involves selecting a substrate on which a wurtzite III-nitride alloy layer will be formed, and a piezoelectric polarization and an effective piezoelectric coefficient for the wurtzite III-nitride alloy layer. It is determined whether there is a wurtzite III-nitride alloy composition satisfying the selected effective piezoelectric coefficient. It is also determined whether there is a thickness for a layer formed from the wurtzite III-nitride alloy composition satisfying the selected piezoelectric polarization based on the selected substrate and the selected effective piezoelectric coefficient.

Abstract: Methods of depositing a film selectively onto a first material relative to a second material are described. The substrate is pre-cleaned by heating the substrate to a first temperature, cleaning contaminants from the substrate and activating the first surface to promote formation of a self-assembled monolayer (SAM) on the first material. A SAM is formed on the first material by repeated cycles of SAM molecule exposure, heating and reactivation of the first material. A final exposure to the SAM molecules is performed prior to selectively depositing a film on the second material. Apparatus to perform the selective deposition are also described.

Abstract: The invention relates to a method for creating an organic resist on a surface of a cooled substrate, the method comprising the steps of condensing a vapour into a solid film on the surface of the cooled substrate; patterning at least part of the solid film by exposing selected portions of said solid film to at least one electron beam thereby creating the organic resist on 5 the surface of the cooled substrate in accordance with a predetermined pattern; wherein the created organic resist remains essentially intact at ambient conditions; and using the created organic resist as a mask for creating semiconductor structures and/or semiconductor devices.

Abstract: Semiconductor devices having silicon doping for laser splash protection, along with associated methods and systems, are disclosed herein. In one embodiment, a semiconductor device includes a silicon layer and a circuitry layer with a plurality of semiconductor devices. A doped silicon region is formed on a front side of the silicon layer upon which the circuitry layer is deposited. The doped silicon region is positioned under the circuitry layer. The doped silicon region has a dopant concentration of at least 1015 cm?3.

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Abstract: The present invention discloses an epitaxial lift-off process of graphene-based gallium nitride (GaN), and principally solves the existing problems about complex lift-off technique, high cost, and poor quality of lift-off GaN films. The invention is achieved by: first, growing graphene on a well-polished copper foil by CVD method; then, transferring a plurality of layers of graphene onto a sapphire substrate; next, growing GaN epitaxial layer on the sapphire substrate with a plurality of graphene layers transferred by the metal organic chemical vapor deposition (MOCVD) method; finally, lifting off and transferring the GaN epitaxial layer onto a target substrate with a thermal release tape. With graphene, the present invention relieves the stress generated by the lattice mismatch between substrate and epitaxial layer; moreover, the present invention readily lifts off and transfers the epitaxial layer to the target substrate by means of weak Van der Waals forces between epitaxial layer and graphene.

Abstract: A semiconductor structure includes a substrate. The semiconductor structure further includes a first III-V layer over the substrate, wherein the first III-V layer includes a first dopant type. The semiconductor structure further includes a second III-V layer over the first III-V layer, wherein the second III-V layer has a second dopant type opposite the first dopant type. The semiconductor structure further includes a third III-V layer over the second III-V layer, wherein the third III-V layer has the first dopant type. The semiconductor structure further includes a fourth III-V layer over the third III-V layer, the fourth III-V layer having the second dopant type. The semiconductor structure further includes an active layer over the fourth III-V layer. The semiconductor structure further includes a dielectric layer over the active layer.

Abstract: Systems, apparatuses, and methods related to epitaxial growth on semiconductor structures are described. An apparatus may include a working surface of a substrate material and a storage node connected to an active area of an access device on the working surface. The apparatus may also include a material epitaxially grown over the storage node contact to enclose a non-solid space between the storage node contact and passing sense lines.

Abstract: The present invention generally relates to a method for preparing structurally unique nanomaterials and the products thereof. In particular, the present invention discloses a method for preparing an array of ultra-narrow nanowire or nanorod on a patterned monolayer supported by a 2D material substrate in a controlled environment, wherein said pattered monolayer comprises a polymerizable amphiphiles such as phospholipid with a terminal amine and wherein said controlled environment comprises a major nonpolar solvent, a trace amount of polar solvent, and a unsaturated aliphatic amine. Gold nanowires (AuNWs) so prepared have a highly controlled diameter of about 2 nm, a length up to about 1000 nm, and an AuNW ordering over an area >100 ?m2.

Abstract: An etching method and an etching apparatus improve the shape of a mask deformed by an etching process. The etching method for etching a film with plasma includes a step of providing a substrate, an etching step, and a correction step. In the step of providing a substrate, a substrate having a mask formed on a first film is provided. In the etching step, the first film is etched with plasma generated from a first gas containing Xe, Kr, or Rn so that an aspect ratio of a hole or a groove formed in the first film is 30 or more. In the correction step, the shape of the mask is corrected with plasma generated from a second gas.

Abstract: Methods and apparatuses for performing cycles of aspect ratio dependent deposition and aspect ratio independent etching on lithographically patterned substrates are described herein. Methods are suitable for reducing variation of feature depths and/or aspect ratios between features formed and partially formed by lithography, some partially formed features being partially formed due to stochastic effects. Methods and apparatuses are suitable for processing a substrate having a photoresist after extreme ultraviolet lithography. Some methods involve cycles of deposition by plasma enhanced chemical vapor deposition and directional etching by atomic layer etching.

Abstract: The present invention relates to various high quality n-type and p-type doped gallium-based semiconductor materials, electronic components incorporating these materials, and processes of producing these materials. In particular, The present invention relates processes to achieve high quality, uniform doping of a whole wafer or a thin layer of gallium-based semiconductor materials for various applications such as a vertical power transistor or diode.

Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a source epitaxy structure and a drain epitaxy structure. The semiconductor fin extends along a first direction above a substrate. The gate structure extends across the semiconductor fin along a second direction different from the first direction. The gate structure includes a gate dielectric layer wrapping around the semiconductor fin and a chlorine-containing N-work function metal layer wrapping around the gate dielectric layer. The source epitaxy structure and the drain epitaxy structure are on opposite sides of the gate structure, respectively.

Abstract: A method for fabricating a semiconductor device includes: preparing a substrate; forming an isolation layer defining an active region in the substrate; forming a first insulation structure over the substrate, the first insulation structure defining a line-type opening that exposes the isolation layer and the active region; forming a plug pad through a Selective Epitaxial Growth (SEG) process over the exposed active regions; forming a second insulation structure inside the line-type opening, the second insulation structure defining a contact hole landing on the plug pad; and filling the contact hole with a contact plug.

Abstract: A plasma processing method according to an exemplary embodiment includes generating plasma from a film formation gas in a chamber of a plasma processing apparatus by supplying radio frequency power from a radio frequency power source. The plasma processing method further includes forming a protective film on an inner wall surface of a side wall of the chamber by depositing a chemical species from the plasma on the inner wall surface. In the forming a protective film, a pulsed negative direct-current voltage is periodically applied from a direct-current power source device to an upper electrode of the plasma processing apparatus.

Abstract: In some embodiments of the present disclosure, a method of manufacturing a semiconductor structure includes providing a substrate including a first atom and a second atom; forming a compound over the substrate by bonding the first atom with a ionized etchant; and removing the compound from the substrate by bombarding the compounds with a charged particle having a bombarding energy smaller than a bonding energy between the first atom and the second atom, wherein the charged particle and the ionized etchant include different ions.

Abstract: A method includes depositing a mask layer over a semiconductor substrate, etching the mask layer to form a patterned mask, wherein a sidewall of the patterned mask includes a first sidewall region, a second sidewall region, and a third sidewall region, wherein the first sidewall region is farther from the semiconductor substrate than the second sidewall region and the second sidewall region is farther from the semiconductor substrate than the third sidewall region, wherein the second sidewall region protrudes laterally from the first sidewall region and from the third sidewall region, etching the semiconductor substrate using the patterned mask to form fins, forming a gate stack over the fins, and forming source and drain regions in the fin adjacent the gate stack.

Abstract: A method for selective etching of silicon oxide relative to silicon nitride includes exposing a substrate to a first gas that forms a first layer on the silicon oxide film and a second layer on the silicon nitride film, where the first gas contains boron, aluminum, or both boron and aluminum, exposing the substrate to a nitrogen-containing gas that reacts with the first layer to form a first nitride layer on the silicon oxide film and reacts with the second layer to form a second nitride layer on the silicon nitride film, where a thickness of the second nitride layer is greater than a thickness of the first nitride layer. The method further includes exposing the substrate to an etching gas that etches the first nitride layer and silicon oxide film, where the second nitride layer protects the silicon nitride film from etching by the etching gas.

Abstract: A plasma processing apparatus, including a processing; a first radio frequency power source; a sample stage on which the sample is placed; a second radio frequency power; and a control device configured to control, when the second radio frequency power source is controlled based on a change in a plasma impedance, which is generated when a first gas that is a gas for a first step is switched to a second gas that is a gas for a second step, such that the second radio frequency power is changed from a value of the second radio frequency power in the first step to a value of the second radio frequency power in the second step, and a supply time of the first gas such that a supply time of the second radio frequency power in the first step is substantially equal to a time of the first step.

Abstract: A point etching module using an annular surface-discharge plasma apparatus is disclosed. The point etching module using an annular surface-discharge plasma apparatus comprises: a plate-shaped dielectric; a circular electrode disposed on and in contact with the upper surface of the dielectric; an annular electrode disposed on and in contact with the lower surface of the dielectric and providing a gas receiving space for receiving gas; and a power supplier for applying high voltage between the circular electrode and the annular electrode, wherein when the application of the high voltage starts an electric discharge, filament type plasma is irradiated toward a substrate to be treated, by using plasma flowing in the center direction of the annular electrode from between the inner surface of the annular electrode and the lower surface of the dielectric.

Abstract: Systems and methods for improving process uniformity in a millisecond anneal system are provided. In some implementations, a process for thermally treating a substrate in a millisecond anneal system can include obtaining data indicative of a temperature profile associated with one or more substrates during processing in a millisecond anneal system. The process can include one or more of (1) changing the pressure inside the processing chamber of the millisecond anneal system; (2) manipulating the irradiation distribution by way of the refracting effect of a water window in the millisecond anneal system; (3) adjusting the angular positioning of the substrate; and/or (4) configuring the shape of the reflectors used in the millisecond anneal system.

Abstract: A semiconductor device includes a substrate, a first well, a second well, a metal gate, a poly gate, a source region, and a drain region. The first well and the second well are within the substrate. The metal gate is partially over the first well. The poly gate is over the second well. The poly gate is separated from the metal gate, and a width ratio of the poly gate to the metal gate is in a range from about 0.1 to about 0.2. The source region and the drain region are respectively within the first well and the second well.

Abstract: Apparatus and methods are disclosed for sample preparation, suitable for online or offline use with multilayer samples. Ion beam technology is leveraged to provide rapid, accurate delayering with etch stops at a succession of target layers. In one aspect, a trench is milled around a region of interest (ROI), and a conductive coating is developed on an inner sidewall. Thereby, reliable conducting paths are formed between intermediate layers within the ROI and a base layer, and stray current paths extending outside the ROI are eliminated, providing better quality etch progress monitoring, during subsequent etching, from body or scattered currents. Ion beam assisted gas etching provides rapid delayering with etch stops at target polysilicon layers. Uniform etching at deep layers can be achieved. Variations and results are disclosed.

Abstract: A method for etching a ruthenium film includes a first step of etching the ruthenium film by plasma processing using oxygen-containing gas, and a second step of etching the ruthenium film by plasma processing using chlorine-containing gas. The first step and the second step are alternately performed. In the first step and the second step, the ruthenium film is etched at a target control temperature for a target processing time that are determined based on a pre-obtained relation between an etching amount per one cycle including the first step and the second step as a set, a control temperature of the ruthenium film, and processing times of each of the first step and the second step.

Abstract: To suppress a change in electrical characteristics and to improve reliability in a semiconductor device using a transistor including an oxide semiconductor. The semiconductor device includes a gate electrode over an insulating surface, an oxide semiconductor film overlapping with the gate electrode, a gate insulating film which is between the gate electrode and the oxide semiconductor film and is in contact with a surface of the oxide semiconductor film, a protective film in contact with an opposite surface of the surface of the oxide semiconductor film, and a pair of electrodes in contact with the oxide semiconductor film. In the gate insulating film or the protective film, the amount of gas having a mass-to-charge ratio m/z of 17 released by heat treatment is greater than the amount of nitrogen oxide released by heat treatment.

Abstract: A method includes forming a release film over a carrier, attaching a device over the release film through a die-attach film, encapsulating the device in an encapsulating material, performing a planarization on the encapsulating material to expose the device, detaching the device and the encapsulating material from the carrier, etching the die-attach film to expose a back surface of the device, and applying a thermal conductive material on the back surface of the device.

Abstract: A semiconductor device has a semiconductor die or component, including an IPD, disposed over an attach area of a penetrable film layer with a portion of the semiconductor die or component embedded in the penetrable film layer. A conductive layer is formed over a portion of the film layer within the attach area and over a portion of the film layer outside the attach area. An encapsulant is deposited over the film layer, conductive layer, and semiconductor die or component. The conductive layer extends outside the encapsulant. An insulating material can be disposed under the semiconductor die or component. A shielding layer is formed over the encapsulant. The shielding layer is electrically connected to the conductive layer. The penetrable film layer is removed. The semiconductor die or component disposed over the film layer and covered by the encapsulant and shielding layer form an SIP module without a substrate.

Abstract: An apparatus and a method for performing liquid treatment for a substrate are provided. The apparatus for treating the substrate includes a treating container having a treatment space inside the treating container, a substrate support unit to support a substrate in the treatment space, and a liquid supply unit to supply treatment liquid to the substrate supported by the substrate support unit. The liquid supply unit includes a nozzle, a supply line to supply the treatment liquid to the nozzle and having a first valve mounted in the supply line, and a discharge line branching from a branch point which is a point downstream of the first valve in the supply line to discharge the treatment liquid from the supply line, and having a second valve mounted in the discharge line. A valve is absent in an area between the branch point and the nozzle, in the supply line.

Abstract: A system includes a filter purge apparatus configured to supply a flushing gas to a portion of a factory interface chamber located upstream of a chamber filter to minimize moisture contamination of the chamber filter by ambient air. The filter purge apparatus is configured to supply the flushing gas in association with breach of the factory interface chamber which compromises controlled environment of the factory interface chamber.

Abstract: A cover for a swing member of a substrate processing apparatus includes an upper surface including a first groove, and a first side edge and a second side edge located respectively at both ends of the upper surface in the short-length direction of the cover, where a bottom portion of the first groove is located lower than the first side edge and the second side edge.

Abstract: Provided are a process gas supply apparatus which supplies a process gas onto a wafer to etch an oxide layer by dividing an edge zone into a first zone and a second zone located outside the first zone and dividing the second zone into a plurality of sub-zones and a wafer treatment system including the process gas supply apparatus.

Abstract: Disclosed is a plasma processing device that provides an object to be treated with plasma treatment. A wafer as an object to be treated, which is attached on the upper surface of adhesive sheet held by a holder frame, is mounted on a stage. In a vacuum chamber that covers the stage therein, plasma is generated, by which the wafer mounted on the stage undergoes plasma treatment. The plasma processing device contains a cover member made of dielectric material. During the plasma treatment on the wafer, the holder frame is covered with a cover member placed at a predetermined position above the stage, at the same time, the wafer is exposed from an opening formed in the center of the cover member.

Abstract: A laser annealing apparatus 100 includes a laser irradiation device 10 to emit a plurality of laser beams LB toward an irradiation region R1 of a stage 20, the laser irradiation device including: a laser device to emit a laser beam LA; and a convergence unit that includes a microlens array 34 having a plurality of microlenses 34A arranged in m rows and n columns and a mask 32 having a plurality of apertures 32A, the convergence unit 30 receiving the laser beam from the laser device to form respective convergence points of the plurality of laser beams within the irradiation region R1. The plurality of laser beams are p rows and q columns of laser beams formed by p rows and q columns of microlenses (p<m or q<n) among the m rows and n columns of microlenses.

Abstract: A collet apparatus is provided including a body. A first adsorption unit is connected to the body. A second adsorption unit is connected to the first adsorption unit. The second adsorption unit adsorbs a semiconductor chip. An illumination unit is disposed inside the body, and provides a light to the semiconductor chip adsorbed onto the second adsorption unit to examine the semiconductor chip.

Abstract: An anti-ejection apparatus for wafer units includes a lock bar and a guide pin. The lock bar alternately has a plurality of lock portions and a plurality of unlock portions. The lock portions are located at heights corresponding to those of insertion slots of a side plate of a cassette, and enable blocking of the insertion slots. The unlock portions enable unblocking of the insertion slots. The guide pin is connected to the lock bar and is disposed protruding downward from a bottom portion of the side plate of the cassette. When the guide pin is pressed upward at its lower end portion, the unlock portions and the insertion slots are communicated with each other. When the pressing of the lower end portion of the guide pin is cancelled, on the other hand, the insertion slots are blocked by lock portions.

Abstract: The present disclosure provides systems and methods for monitoring an environment of a front opening universal pod (FOUP). The systems and methods may include an environmental sensor disposed within the FOUP and configured to measure one or more environmental parameters of an interior environment of the FOUP; and a wireless transmitter disposed within the FOUP and in communication with the environmental sensor, wherein the wireless transmitter is configured to wirelessly transmit the one or more environmental parameters from the environmental sensor to a controller disposed outside of the FOUP to decide whether the one or more environmental parameters are within threshold limits and receive a message according to a decision of whether the one or more environmental parameters are within the threshold limits from the controller.

Abstract: A first x-y translation stage, a second x-y translation stage, and a chuck are disposed in a chamber. The chuck is situated above and coupled to the second x-y translation stage, which is situated above and coupled to the first x-y translation stage. The chuck is configured to support a substrate and to be translated by the first and second x-y stages in x- and y-directions, which are substantially parallel to a surface of the chuck on which the substrate is to be mounted. A first barrier and a second barrier are also disposed in the chamber. The first barrier is coupled to the first x-y translation stage to separate a first zone of the chamber from a second zone of the chamber. The second barrier is coupled to the second x-y translation stage to separate the first zone of the chamber from a third zone of the chamber.

Abstract: A scanner includes a light source configured to apply a light to a backside of a wafer. The light is reflected from the backside of the wafer. A first mirror is configured to receive the light from the backside of the wafer and reflect the light. A sensor is configured to receive the light from the first mirror and generate an output signal indicative of a backside topography of the wafer.

Abstract: An electrostatic chuck includes at least one conductor layer; an electrostatic electrode; and a base body in which the electrostatic electrode is embedded, the base body having a first dielectric layer on which the electrostatic electrode is mounted, the base body having a second dielectric layer stacked on the first dielectric layer with covering the electrostatic electrode. The conductor layer is formed on a surface of the first dielectric layer opposite to a surface on which the electrostatic electrode is mounted. The second dielectric layer has a first surface facing the first dielectric layer and a second surface opposite to the first surface, and the second surface is a placement surface on which a suction target is placed. A relative permittivity of the first dielectric layer is lower than a relative permittivity of the second dielectric layer.

Abstract: An electronic device structure and a method for making an electronic device. As non-limiting examples, various aspects of this disclosure provide a method of manufacturing an electronic device that comprises the utilization of a carrier assisted substrate, and an electronic device manufactured thereby.

Abstract: An apparatus includes a transfer substrate with two or more transfer elements. Each of the transfer elements includes an adhesion element having a first surface adhesion at a first temperature and a second surface adhesion at a second temperature. The second surface adhesion less than the first surface adhesion. Each transfer element has a thermal element operable to change a temperature of the adhesion element in response to an input.

Abstract: A method for processing a substrate assembly with a semiconductor device layer includes: arranging an auxiliary carrier at the substrate assembly such that a connection surface of the auxiliary carrier and a first surface of the substrate assembly directly adjoin each other; fixedly attaching the auxiliary carrier to the substrate assembly by melting a carrier portion of the auxiliary carrier and a substrate portion of the substrate assembly that directly adjoins the carrier portion such that the auxiliary carrier and the substrate assembly locally fuse only in fused portions of the auxiliary carrier and the substrate assembly, wherein the fused portions are laterally separated from each other by at least one unfused portion; and processing the semiconductor device layer of the substrate assembly with the auxiliary carrier fixedly attached to the substrate assembly.

Abstract: A carrier assembly is configured to support a wafer, including during back end of line (BEOL) processing. The carrier assembly includes dual carriers. A first carrier includes a stepped structure so as to situate the wafer. A side of the wafer is bonded to the first carrier without adhesive. The first carrier is positioned atop the second carrier, so as to be mechanically supported by the second carrier. Each carrier is made by wet etching of laminated glass, without mechanical polishing.

Abstract: A substrate processing apparatus includes a stage including a first section and a second section, pins, a lifter configured to raise and lower the pins, and a controller configured to control the lifter. On the first section, a substrate is placed. On the second section, an edge ring is placed. The second section is provided at a periphery of the first section. Also, at the second section, holes are provided. The pins are provided in the respective holes so as to move up and down through the holes.

Abstract: A substrate holding apparatus which can stably hold a substrate, such as a wafer, while causing the substrate to make a circular motion and rotating the substrate about its axis is disclosed. The substrate holding apparatus includes: rollers; electric motors configured to rotate the rollers; eccentric shafts arranged around a central axis; and actuators. The eccentric shafts include movable shafts and reference shafts, the actuators are coupled to the movable shafts, respectively, and the actuators are configured to move the movable shafts in a direction closer to the reference shafts and in a direction away from the reference shafts.

Abstract: An apparatus for supporting a substrate includes a rotatable spin head that supports the substrate, a hollow shaft that is connected with the spin head and that transmits torque to the spin head, a nozzle assembly that is disposed in an interior space of the spin head so as not to rotate and that supplies a treatment liquid to a backside of the substrate, and a sealing member that seals a gap between the spin head and the nozzle assembly using a magnetic fluid.