Abstract: A PZT microactuator such as for a hard disk drive has a restraining layer bonded on its side that is opposite the side on which the PZT is mounted. The restraining layer comprises a stiff and resilient material such as stainless steel. The restraining layer can cover most or all of the top of the PZT, with an electrical connection being made to the PZT where it is not covered by the restraining layer. The restraining layer reduces bending of the PZT as mounted and hence increases effective stroke length, or reverses the sign of the bending which increases the effective stroke length of the PZT even further. The restraining layer can be one or more active layers of PZT material that act in the opposite direction as the main PZT layer. The restraining layer(s) may be thinner than the main PZT layer.

Abstract: The present disclosure generally relates to a head assembly of a data storage device. The data storage device may include magnetic media embedded in the device or magnetic media from an insertable cassette or cartridge (e.g., in an LTO drive), where the magnetic head assembly reads from and writes to the magnetic media. During drive operation, the magnetic media moves across the magnetic head assembly. The magnetic head assembly is spaced a distance from the magnetic media such that non-contact recording occurs between the magnetic head assembly and the magnetic media. The magnetic media is supported by either a back plate or an air film generated by one or more fillet edges of the back plate and the velocity of the magnetic media as the magnetic media moves across the magnetic head assembly.

Abstract: In a multi-actuator drive, the effect of moving a first actuator (the so-called “aggressor actuator”) in on a second actuator (the so-called “victim actuator”) is reduced or compensated for. A victim feedforward signal is added to a microactuator control signal of the victim actuator in response to a voice-coil motor (VCM) control signal that is applied to the aggressor actuator. The feedforward signal is configured to compensate for disturbances to the victim microactuator caused by VCM commands provided to the aggressor actuator. The feedforward signal is based on a transfer function that models commands added to the victim microactuator, which is coupled to the head of the victim actuator, as a function of the aggressor VCM control signal applied to the aggressor actuator.

Abstract: According to one embodiment, a magnetic recording and reproducing device includes a perpendicular magnetic recording medium, a perpendicular magnetic recording head, a thermal assisted magnetic recording medium, and a thermal assisted magnetic recording head.

Abstract: A hard disk drive includes a base deck that is coupled to a cover, a motor assembly that is coupled to the base deck, and magnetic recording media that is coupled to the motor assembly. The motor assembly includes a magnetic bearing with a horizontal magnetic bearing component and a vertical magnetic bearing component.

Abstract: According to one embodiment, a magnetic disk device includes a magnetic disk, a magnetic head, a heater a control section. When making the magnetic head carry out the seek operation from the first position to the second position, the control section starts application of a first voltage to the heater while the seek operation is carried out and, after application of the first voltage, makes the voltage to be applied to the heater a second voltage greater than the first voltage before the magnetic head is positioned to the second position and write of data is started by the magnetic head.

Abstract: A user device provides a user interface for video manipulation with face replacement. A method of implementations includes accessing a video comprising a plurality of frames that comprise one or more faces, providing a plurality of stickers comprising alternate face graphics for the one or more faces, receiving, via a user interface of a user device, user selection of one of the stickers and a selected face of the one or more faces, accessing a plurality of face frame sequences of the video, wherein each face frame sequence is a sequence of frames of the video comprising the selected face of the one or more faces, and replacing the selected face with the selected sticker in a first face frame sequence of the plurality of face frame sequences and in a second face frame sequence of the plurality of face frame sequences.

Abstract: Review videos on product pages are enhanced with user interface elements that cause playback of the review videos at points at which particular topics are discussed. A review video is processed by converting speech to text and timestamping the text. Topics are identified in the text, and a time in the review video corresponding to each topic is identified from the timestamps for the text. In some configurations, sentiment is also determined for each topic. User interface elements corresponding to each identified topic are presented with the review video on the product page. When a user viewing the product page selects a user interface element, the review video is played at a time corresponding to the topic of the selected user interface element.

Abstract: A decoding system decodes a video stream, which is encoded video information. The decoding system includes a decoder that acquires the video steam and generates decoded video information, a maximum luminance information acquirer that acquires maximum luminance information indicating the maximum luminance of the video stream from the video stream, and an outputter that outputs the decoded video information along with the maximum luminance information. In in a case where the video stream includes a base video stream and an enhanced video stream, the decoder generates base video information by decoding the base video stream, an enhanced video information by decoding the enhanced video stream, and generates the decoded video information based on the base video information and the enhanced video information, and the outputter outputs the decoded video information, along with the maximum luminance information.

Abstract: A decoding method of a video stream, which is encoded video information. The video stream includes a base video stream, and an enhanced video stream, which is a video stream to enhance luminance of the base video stream, and a describer that contains the combination information of the base video stream and the enhanced video stream. The decoding method includes acquiring the describer, and identifying the combination of the base video steam and the enhanced video stream. The decoding method also includes generating base video information by decoding the base video stream, generating enhanced video information by decoding the enhanced video stream, generating decoded video information based on the base video stream and the enhanced video stream, and outputting the decoded video information.

Abstract: A high resolution impedance adjustment (ZQ) calibration method using a hidden least significant bit (HLSB) is provided. The high resolution ZQ calibration method generates a data input/output (DQ) code of n+1 bits without a calibration time increase by adding the hidden least significant bit (HLSB) to a ZQ code of n bits output in a ZQ calibration operation of an impedance adjustment (ZQ) pad. A change in a termination resistance of the DQ pad is reduced as small as possible by the DQ code of n+1 bits.

Abstract: An integrated circuit includes a first input/output lane comprising first external terminals and first driver circuits. The first driver circuits exchange signals with a first external device through the first external terminals as part of a first external interface. The first input/output lane is part of a sub-bank in an input/output bank that implements at least a part of the first external interface. The integrated circuit includes a second input/output lane comprising second external terminals and second driver circuits. The second driver circuits exchange signals with a second external device through the second external terminals as part of a second external interface. The second input/output lane is part of the sub-bank in the input/output bank that implements at least a part of the second external interface.

Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

Abstract: A magnetic memory device includes a first fixed layer maintaining a particular magnetization direction, a first non-magnetic layer, a free layer having perpendicular magnetic anisotropy and a variable magnetization direction, a second non-magnetic layer, and a second fixed layer maintaining a separate particular magnetization direction that is opposite to the particular magnetization direction of the first fixed layer. A resistance value of a first magnetic tunnel junction (MTJ) element including the first fixed layer, the first non-magnetic layer, and the free layer is different from that of a second MTJ element that includes the second fixed layer, the second non-magnetic layer, and the free layer.

Abstract: The present invention is directed to a nonvolatile memory device that includes one or more memory sectors and a read circuit for sensing the resistance state of a magnetic memory cell in the memory sectors. The read circuit includes first and second input nodes; a sense amplifier having first and second input terminals; a reference resistor connected to the first input node at one end and the first input terminal at the other end; a multiplexer having a first input, a second input, and an output, with the first input being connected to the second input node and the output being connected to the second input terminal; a first target resistor and an offset resistor connected in series between the second input node and the second input; and first and second current sources connected to the first and second input terminals, respectively.

Abstract: A device includes first and second reference storage units, and first and second reference switches. The first reference switch outputs a first current at a first terminal thereof to the first reference storage unit. The first reference storage unit receives the first current at a first terminal thereof and generates a first signal, according to the first current, at a second terminal thereof to an average current circuit. The second reference switch outputs a second current at a first terminal thereof to the second reference storage unit. The second reference storage unit receives the second current at a first terminal thereof, and generates a second signal, according to the second current, at a second terminal thereof to the average current circuit. The first and second reference switches are coupled to a plurality of first memory cells by a first word line.

Abstract: A writing method and erasing method of a fusion memory are provided, and the fusion memory includes a plurality of memory cells, and each memory cell of the plurality of memory cells includes a bulk substrate; a source and a drain on the bulk substrate, a channel region extending between the source and the drain, and a ferroelectric layer and a gate stacked on the channel region; and the writing method includes: applying a first voltage between the gate of at least one memory cell and the bulk of at least one memory cell, in which the first voltage is less than a reversal voltage at which the ferroelectric layer is polarization reversed, and each of the source and the drain is grounded or in a floating state.

Abstract: A power module and a memory device are disclosed. The power module includes: a voltage raise unit for outputting a power voltage; an enabling unit connected to the power output for generating and outputting an enabling signal; a control unit, includes: an oscillator, a pulse generator, and an OR operation unit; the oscillator generates a delayed pulse control signal with a certain period; the pulse generator connects to the output terminal of the enabling unit for receiving the enable signal, synchronously generates an instant pulse control signal; the OR operation unit performs OR calculation to the delay pulse control signal and the instant pulse control signal to generate a boost control signal. The output end of the control unit connects to the voltage raise unit, and outputs the boost control signal to the voltage raise unit. The above-mentioned power module has a high transient response capability and maintains the stability of the output power voltage.

Abstract: Methods, systems, and devices for timing signal calibration for a memory device are described. In some memory devices, operations for accessing memory cells may be performed with timing that is asynchronous with an input signal. To support asynchronous timing, a timing signal generation component of a memory device may include delay components that support generating a timing signal having aspects that are delayed relative to an input signal. Delay components may have characteristics that are sensitive to fabrication or operational variability, such that timing signals may also be affected by such variability. In accordance with examples as disclosed herein, a memory device may include delay components, associated with access operation timing signal generation, that are configured to be selectively enabled or disabled based on a calibration operation of the memory device, which may improve an ability of the memory device to account for various sources of timing signal variability.

Abstract: A nonvolatile memory apparatus may include a control circuit, a sense amplifier, and a reference generator. The control circuit may apply a read voltage across a target memory cell through a selected global bit line and a selected global word line. The sense amplifier may generate an output signal by comparing voltage levels of the selected global word line and a reference line. The reference generator may change the voltage level of the reference line by charging and discharging a capacitor that is coupled to the reference line.

Abstract: A semiconductor memory device includes a substrate including a logic circuit, a memory cell array disposed over the substrate, a first conductive group including a plurality of bit lines and a first upper source line that are coupled to the memory cell array and spaced apart from each other and a first upper wire that is coupled to the logic circuit, an insulating structure covering the first conductive group.

Abstract: Systems and methods for detecting a row hammer in a memory comprising a plurality of memory cells arranged in a plurality of rows may include: a plurality of detection cells in a subject row of memory cells, the detection cells to be set to respective initial states and configured to transition to a state different from their initial states in response to activations of memory cells in an adjacent row of memory cells; a comparison circuit to compare current states of the detection cells with initial states of the detection cells and to determine whether any of the detection cells have a current state that is different from their corresponding initial states; and a trigger circuit to trigger a refresh of the memory cells in the subject row based on a detection of detection cells in the subject row having current states that are different from their corresponding initial states.

Abstract: A memory device includes a cell area in which a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to the plurality of word lines and the plurality of bit lines are disposed, each of the plurality of memory cells including an Ovonic threshold switch element and a memory element connected to each other in series, and a peripheral circuit area including at least one peripheral circuit, configured to input a first refresh voltage turning on the Ovonic threshold switch element to each of at least some refresh cells among the plurality of memory cells to execute a refresh operation, determine each of the refresh cells as a first refresh cell in a first state or a second refresh cell in a second state while the Ovonic threshold switch element is turned on, and input a second refresh voltage, different to the first refresh voltage, to the second refresh cell.

Abstract: A CIM bit cell circuit employing a capacitive storage circuit to store a binary weight data as a voltage occupies half or less of the area of a 6T SRAM CIM bit cell circuit, reducing the increase in area incurred in the addition of a CIM bit cell array circuit to an IC. The CIM bit cell circuit includes a capacitive storage circuit that stores binary weight data in a capacitor and generates a product voltage indicating a binary product resulting from a logical AND-based operation of the stored binary weight data and an activation signal. The capacitive storage circuit may include a capacitor and a read access switch or a transistor. The CIM bit cell circuit includes a write access switch to couple a write bit voltage to the capacitive storage circuit. In a CIM bit cell array circuit, the product voltages are summed in a MAC operation.

Abstract: A memory device accessed by circuits operating based on a first supply voltage. The memory device includes a cell array electrically connected to a plurality of word lines and a plurality of bit lines; a row driver configured to select one word line of the plurality of word lines based on a row address; a precharge circuit configured to precharge the plurality of bit lines based on the first supply voltage; a column driver configured to select at least one bit line of the plurality of bit lines based on a column address; and a read circuit configured to read data stored in the cell array through the at least one bit line. The cell array, the row driver, the column driver, and the read circuit operate based on a second supply voltage, which is higher than the first supply voltage.

Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

Abstract: A semiconductor memory device includes a memory block including a plurality of memory cells programmed to a plurality of program states during a program operation, a voltage generator to generate and apply a program voltage and a select line voltage to the memory block during the program operation, and a read and write circuit to temporarily store program data during the program operation and control a potential of bit lines of the memory block based on the temporarily stored program data. The voltage generator generates the select line voltage as a first select line voltage during a first program operation on some program states among the plurality of program states, or as a second select line voltage for which a potential is lower than a potential of the first select line voltage during a second program operation on remaining program states among the plurality of program states.

Abstract: A non-volatile memory includes a cell array, a current supply circuit, a path selecting circuit, a verification circuit and a control circuit. During a sample period of a verification action, the control circuit controls the current supply circuit to provide n M-th reference currents to the verification circuit and convert the n M-th reference currents into n reference voltages. During a verification period of the verification action, the control circuit controls n multi-level memory cells of a selected row of the cell array to generate n cell currents to the verification circuit and convert the n cell currents into n sensed voltages. The n verification devices generate the n verification signals according to the reference voltages and the sensed voltages. Accordingly, the control circuit judges whether the n multi-level memory cells have reached an M-th storage state.

Abstract: A semiconductor memory device includes a first memory cell for storing data using at least three levels of threshold voltages, including a first level, a second level higher than the first level and a third level higher than the second level. A first word line is connected to the first memory cell. In writing of data to the first memory cell from a state where a threshold voltage of the first memory cell is the first level, a plurality of program operations and verify operations are performed, each program operation including applying a program voltage to the first word line, each verify operation including applying a read voltage lower than the program voltage. The program operations include a program operation for the second level and a program operation for the third level, and the verify operations include a verify operation for the second level, and do not include a verify operation for the third level.

Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.

Abstract: Various embodiments of the present application are directed towards a method for forming an integrated chip. The method includes forming a dielectric structure over a substrate. A first conductive wire is formed along the dielectric structure. The first conductive wire extends laterally along a first direction. A memory stack is formed on a top surface of the first conductive wire. A second conductive wire is formed over the memory stack. The second conductive wire extends laterally along a second direction orthogonal to the first direction. An upper conductive via is formed on the top surface of the first conductive wire. An upper surface of the upper conductive via is above the second conductive wire.

Abstract: Distributing multiply-accumulate currents across segment mirrors by providing a circuit including an array of resistive elements, the array including rows and columns and first stage current mirrors, each of the first stage current mirrors being electrically coupled to a segment, wherein the segment comprises a columnar subset of the resistive elements, providing, by the array, a vector of current outputs equal to an analog vector-matrix product between a vector of voltage inputs to the array and a matrix of analog resistive weights within the array, wherein the voltage inputs encode a vector of analog input values, wherein each row of resistive elements corresponds to a specific voltage input, determining a score for each of the rows, determining a ranking of the rows of the array according to the score of each row, and mapping each row to a segment according to the ranking.

Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.

Abstract: A memory device includes a page buffer circuit including a plurality of page buffer stages each including a plurality of page buffers. The memory device also includes a control circuit configured to generate page buffer control signals for controlling the plurality of page buffers. The control circuit is also configured to probe each of a plurality of page buffer control signal groups configured with the page buffer control signals through a probing path corresponding to each of the plurality of page buffer control signal groups.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

Abstract: Memory having an array of memory cells might include control logic configured to cause the memory to program each memory cell of a plurality of memory cells whose respective data state is higher than or equal to a first particular data state of a plurality of data states while inhibiting programming of each memory cell of the plurality of memory cells whose respective data state is lower than the first particular data state, and program each memory cell of the plurality of memory cells whose respective data state is lower than or equal to a second particular data state of the plurality of data states after programming each memory cell of the plurality of memory cells whose respective data state is higher than or equal to the first particular data state.

Abstract: Embodiments of erasing methods for a three-dimensional (3D) memory device are disclosed. The 3D memory device includes multiple decks vertically stacked over a substrate, wherein each deck includes a plurality of memory cells. The erasing method includes checking states of the plurality of memory cells of an erase-inhibit deck and preparing the erase-inhibit deck according to the states of the plurality of memory cells. The erasing method also includes applying an erase voltage at an array common source, applying a hold-release voltage on unselected word lines of the erase-inhibit deck, and applying a low voltage on selected word lines of a target deck.

Abstract: A nonvolatile memory device includes cell strings commonly connected between bitlines and a source line where the cell strings are grouped into memory blocks. During a precharge period, channels of the cell strings of a selected memory block are precharged by applying a gate induced drain leakage (GIDL) on voltage to gates of GIDL transistors included in the cell strings of the selected memory block where the GIDL on voltage has a voltage level to induce GIDL. During the precharge period, precharge of channels of the cell strings of an unselected memory block are prevented by controlling a gate voltage of GIDL transistors included in the cell strings of the unselected memory block to prevent the GIDL. During a program execution period after the precharge period, memory cells of the selected memory block connected to a selected wordline are programmed by applying a program voltage to the selected wordline.

Abstract: Systems and methods that may be implemented for that may be implemented to compensate for NAND flash memory voltage threshold (Vth) shift by using one or more designated calibration wordlines that are programmed into the NAND flash memory with a pre-defined data pattern. In one example configuration, the disclosed systems and methods may be automatically implemented by a SSD controller when needed to compensate for flash memory voltage threshold (Vth) shift that occurs, e.g., due to NAND memory cell charge loss due to power-off data retention over an extended period of time.

Abstract: According to the present technology, a memory device may include memory cells configured to be programmed so that each of the memory cells has a threshold voltage corresponding to any one of a plurality of program states, a peripheral circuit configured to perform a read operation or a program operation on the memory cells, and control logic configured to control the peripheral circuit to perform a test read operation of reading the memory cells using a test read voltage that is any one read voltage among preset default read voltages, and perform a refresh program operation of applying a refresh program voltage to some memory cells among the memory cells according to the number of memory cells having a threshold voltage greater than the test read voltage.

Abstract: A solid-state memory may have many non-individually erasable memory cells arranged into calibration groups with each memory cell in each respective calibration group using a common set of read voltages to sense programmed states. An evaluation circuit of the solid-state memory may be configured to measure at least one read parameter for each calibration group responsive to read operations carried out upon the memory cells in the associated calibration group. An adjustment circuit of the solid-state memory may redistribute the memory cells of an existing calibration group into at least one new calibration group in response to the at least one measured read parameter.

Abstract: A method for writing to electrically erasable and programmable non-volatile memory and a corresponding integrated circuit are disclosed. In an embodiment a method includes operatively connecting a filter circuit belonging to a communication interface to an oscillator circuit, wherein the communication interface is physically connected to a bus, generating, by the oscillator circuit, an oscillation signal and regulating the oscillation signal by the filter circuit so as to generate a clock signal for timing a write cycle.

Abstract: A system may include multiple memory cells to store logical data, age tracking circuitry to track a time since a previous access of a particular memory cell, and control circuitry to access the memory cell. Such access may include a read operation of the memory cell, a write operation to the memory cell, or both. The control circuitry may determine an electrical parameter of the memory cell based at least in part on the tracked time since the previous access of the memory cell.

Abstract: A measure associated with a characteristic of a die of a memory device is obtained. It is determined whether the measure satisfies a first criterion to group one or more die into a first die family. If it is determined that the measure satisfies the first criterion, the die is associated with the first die family.

Abstract: A layout structure of a small-area one time programmable (OTP) memory using a complementary FET (CFET) is provided. The OTP memory has transistors TP as a program element and transistors TS as a switch element. The transistors TP are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The transistors TS are three-dimensional transistors of which channel portions overlap each other as viewed in plan. The OTP memory of two bits is implemented in a small area.

Abstract: A non-volatile memory device includes a first and a second memory regions including first and second memory cells and first and second analog circuits, respectively; a control logic circuit determining on/off states of the analog circuits, and converting an external power supply voltage into an internal operating voltage for operation of each of the memory cells; and input/output circuit selecting an input/output memory region for performing input/output of data using the internal operating voltage, wherein input/output of data for the first and second memory cells are sequentially performed, and at least one of the each of the first and second analog circuits are turned on together while the input/output of data for the first memory cells is performed.

Abstract: A storage device may include a memory device and a memory controller. The memory device may include a memory block including a plurality of pages. When a sudden power off is detected in which power supplied to the memory device is abnormally interrupted during a normal program operation on one page among the plurality of pages, the memory controller may control the memory device to perform a dummy program operation on a selected page among the plurality of pages after the sudden power-off. The memory controller may control the memory device to perform the normal program operation and the dummy program operation by using an Incremental Step Pulse Program (ISPP) method. The memory controller may control the memory device to perform the dummy program operation in a smaller number of program loops as compared with the normal program operation.

Abstract: Disclosed is a memory device including an error logic unit suitable for determining whether an error is present in command signals to generate a command error signal; a replica delay circuit suitable for replicating a delay value of the error logic unit and generating an input strobe signal by delaying a strobe signal of the command signals; an output strobe signal generation circuit suitable for generating an output strobe signal activated after a command error latency elapses from a time point at which the command signals are received; and a pipe circuit suitable for receiving and storing the command error signal in response to the input strobe signal and outputting the stored command error signal in response to the output strobe signal.

Abstract: A first sequence of operations corresponding to an error recovery process of a memory sub-system is determined. A value corresponding to an operating characteristic of a memory sub-system is determined, the operating characteristic corresponding to execution of a first sequence of operations of an error recovery process. A determination is made that the value satisfies a condition. In response to the value satisfying the first condition, a second sequence of operations corresponding to the error recovery process is executed.

Abstract: A non-transitory computer-readable recording medium storing a structure search program that causes a computer to execute a process, the process includes determining an objective function including a constraint term which is a term for making a coefficient value to a predetermined value, the coefficient value expressing an inter-group distance with reference a shortest distance among distances between lattice points of a plurality of lattice points in a three-dimensional lattice space, the inter-group distance being a distance between a first group that is arranged at a first lattice point and a second group that is arranged at a second lattice point and is linked to the first group, and creating a three-dimensional structure of a compound in the three-dimensional lattice space by arranging a plurality of groups at lattice points in the three-dimensional lattice space that is a set of the plurality of lattice points based on the objective function.