Abstract: A hermetic package includes a base body, wherein dielectric material of a bottom of the base body is made of an organic material, an optical component mounted on the base body, and inorganic material hermetically enclosing the optical component along all surrounding sides.

Abstract: A method of manufacturing a light emitting device includes: placing a light-emitting element above a light-transmitting portion of a first resin layer; placing a protective element above the first resin layer or a first surface of the light-emitting element; forming a second resin layer on the first resin layer so as to cover an entirety of the light-emitting element and an entirety of the protective element; removing a portion of the second resin layer such that an anode and a cathode of the light-emitting element and a first electrically-conductive structure and a second electrically-conductive structure of the protective element are exposed from the second resin layer; and forming a first electrode, which is electrically connected to the anode and the first electrically-conductive structure, and a second electrode, which is electrically connected to the cathode and the second electrically-conductive structure.

Abstract: A display system includes (a) a display element having an organic light emitting diode-containing display active area disposed over a silicon backplane, (b) a display driver integrated circuit (DDIC) attached to the display element and electrically connected with the display active area, and (c) a thermal barrier disposed within the silicon backplane, where the thermal barrier is configured to inhibit heat flow through the silicon backplane and into the display active area.

Abstract: An integrated circuit structure includes a cell on a metal level, the cell defined by a cell boundary. A plurality of substantially parallel interconnect lines are inside the cell boundary. A first power track and a second power track are both dedicated to power and are located completely inside the cell boundary without any power tracks along the cell boundary on the metal level.

Abstract: A semiconductor device includes first cell rows and second cell rows. The first cell rows extend in a first direction. Each of the first cell rows has a first row height. The second cell rows extend in the first direction. Each of the second cell rows has a second row height. The first row height is greater than the second row height. The first cell rows and the second cell rows are interlaced in a periodic sequence. A first row quantity of the first cell rows in the periodic sequence is greater than a second row quantity of the second cell rows in the periodic sequence.

Abstract: An integrated circuit device includes a substrate having a first intellectual property (IP) core including a cell region and a first edge dummy region, fin-type active regions protruding from the cell region, dummy fin-type active regions protruding from the first edge dummy region, gate lines extending, over the cell region of the substrate, the gate lines including two adjacent gate lines spaced apart from each other with a first pitch and two adjacent gate lines spaced apart with a second pitch greater than the first pitch, dummy gate lines over the first edge dummy region of the substrate and equally spaced apart from each other with the first pitch.

Abstract: A semiconductor device with large memory capacity is provided. A semiconductor device includes first to fourth insulators, a first conductor, a second conductor, and a first semiconductor, and the first semiconductor includes a first surface and a second surface. A first side surface of the first conductor is included on the first surface of the first semiconductor, and a first side surface of the first insulator is included on a second side surface of the first conductor. The second insulator is included in a region including a second side surface and a top surface of the first insulator, a top surface of the first conductor, and the second surface of the first semiconductor. The third insulator is included on a formation surface of the second insulator, and the fourth insulator is included on a formation surface of the third insulator. The second conductor is included in a region overlapping the second surface of the first semiconductor in a region where the fourth insulator is formed.

Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

Abstract: Provided is a metal gate structure and related methods that include performing a metal gate cut process. The metal gate cut process includes a plurality of etching steps. For example, a first anisotropic dry etch is performed, a second isotropic dry etch is performed, and a third wet etch is performed. In some embodiments, the second isotropic etch removes a residual portion of a metal gate layer including a metal containing layer. In some embodiments, the third etch removes a residual portion of a dielectric layer.

Abstract: An integrated circuit device including a pair of first fin type active areas protruding from a substrate in a vertical direction and extending in parallel with each other, a gate interposed between the pair of first fin type active areas, spaced apart from each of the pair of first fin type active areas in a first horizontal direction, and longitudinally extending in parallel with the pair of first fin type active areas, a gate insulating layer filling a first space between one of the pair of first fin type active areas and the gate and a second space between the other of the pair of first fin type active areas and the gate, and a pair of source/drain areas at both sides of the gate, respectively, in a second horizontal direction perpendicular to the first horizontal direction and on the pair of first fin type active areas may be provided.

Abstract: An integrated circuit structure includes a first transistor, a second transistor, a first conductive via, a second conductive via, and a connection line. The first transistor includes a first active region, a first gate electrode over the first active region; and a first channel in the first active region and under the first gate electrode. The second transistor includes a second active region, a second gate electrode over the second active region, and a second channel in the second active region and under the second gate electrode. The first conductive via is electrically connected to the first gate electrode. The second conductive via is electrically connected to the second gate electrode. The connection line electrically connects the first and second conductive vias. The first transistor and the first conductive via and the second transistor and the second conductive via are arranged mirror-symmetrically with respect to a symmetry plane.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a gate structure, a source structure, a drain structure, a source contact, and a drain contact. The semiconductor fin extends upwardly from the substrate. The gate structure extends across the semiconductor fin. The source structure is on the semiconductor fin. The drain structure is on the semiconductor fin, in which the source and drain structures are respectively on opposite sides of the gate structure in a plan view. The source contact lands on the source structure and forms a rectangular pattern in the plan view. The drain contact lands on the drain structure and forms a circular pattern in the plan view, in which the rectangular pattern of the source contact has a length greater than a longest dimension of the circular pattern of the drain contact.

Abstract: A semiconductor device includes: a first active pattern on a substrate and including a first active fin and a second active fin; a device isolation layer defining the first active pattern; a gate electrode crossing the first active pattern; a first source/drain pattern and a second source/drain pattern on the first active fin and the second active fin, respectively; an inner fin spacer between the first and second source/drain patterns; and a buffer layer between the first and second active fins, wherein the inner fin spacer includes: a first inner spacer portion contacting the first source/drain pattern; a second inner spacer portion contacting the second source/drain pattern; and an inner extended portion extending from the first and second inner spacer portions, wherein the inner extended portion is between the first and second active fins, wherein the buffer layer has a dielectric constant higher than that of the inner fin spacer.

Abstract: Stacked nanosheet complementary metal-oxide-semiconductor field effect transistor devices include a lower semiconductor channel sheet on a substrate. An upper semiconductor channel sheet is on the substrate above the lower semiconductor channel sheet. The upper semiconductor channel sheet is a different semiconductor material than the lower semiconductor channel sheet. A dielectric substitute partition sheet is on the substrate between the upper semiconductor channel sheet and the lower semiconductor channel sheet.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.

Abstract: A region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are formed separately in one oxide semiconductor film. The region containing a high proportion of crystal components is formed so as to serve as a channel formation region and the other region is formed so as to contain a high proportion of amorphous components. It is preferable that an oxide semiconductor film in which a region containing a high proportion of crystal components and a region containing a high proportion of amorphous components are mixed in a self-aligned manner be formed. To separately form the regions which differ in crystallinity in the oxide semiconductor film, first, an oxide semiconductor film containing a high proportion of crystal components is formed and then process for performing amorphization on part of the oxide semiconductor film is conducted.

Abstract: Provided is a method to manufacture a liquid crystal display device in which a contact hole for the electrical connection of the pixel electrode and one of the source and drain electrode of a transistor and a contact hole for the processing of a semiconductor layer are formed simultaneously. The method contributes to the reduction of a photography step. The transistor includes an oxide semiconductor layer where a channel formation region is formed.

Abstract: The present disclosure provides a manufacturing method of a display substrate, a display substrate and a display device, belongs to the field of display technology, and can at least partially solve a problem of residual sand in the display substrate. The manufacturing method of the display substrate includes: providing a base; forming a passivation layer on a surface of the base; forming an amorphous oxide conductive material layer on a surface of the passivation layer facing away from the base; forming a photoresist pattern on the oxide conductive material layer, the photoresist pattern having an exposure region; etching a portion of the oxide conductive material layer in the exposure region of the photoresist pattern to form a hollow position exposing a portion of the passivation layer; and removing a certain thickness material of the portion of the passivation layer exposed through the hollow position.

Abstract: Disclosed are a crystalline oxide semiconductor thin film including a crystalline oxide semiconductor including indium, gallium, and tin, the crystalline oxide semiconductor exhibiting a (009) diffraction peak in an X-ray diffraction spectrum, and a method of forming the same, a thin film transistor and a method of manufacturing the same, a display panel, and an electronic device.

Abstract: A method for manufacturing an active matrix substrate includes: (A) a step of forming a laminated film including a lower conductive film, a lower insulating film, and a semiconductor film in this order on a substrate; (B) a step of forming a first resist layer; (C) a step of performing a patterning on the laminated film, the step including, in the first formation region, forming the first substructure including a first lower conductive layer, a first lower insulating layer, and a first semiconductor layer respectively formed from the lower conductive film, the lower insulating film, and the semiconductor film, and (D) a step of forming source and drain electrodes electrically connected to the first semiconductor layer.

Abstract: Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

Abstract: A 3D micro display, the 3D micro display including: a first level including a first single crystal layer, the first single crystal layer includes a plurality of LED driving circuits; a second level including a first plurality of light emitting diodes (LEDs), the first plurality of LEDs including a second single crystal layer; a third level including a second plurality of light emitting diodes (LEDs), the second plurality of LEDs including a third single crystal layer, where the first level is disposed on top of the second level, where the second level includes at least ten individual first LED pixels; and a bonding structure, where the bonding structure includes oxide to oxide bonding.

Abstract: An optical package structure and a method for manufacturing an optical package structure are provided. The optical package structure includes a sensor, an optical component and a fixing element. The optical component directly contacts the sensor. An interfacial area is defined by a contacting region of the optical component and the sensor. The fixing element is disposed outside of the interfacial area for bonding the optical component and the sensor.

Abstract: Provided are a color separation element and an image sensor including the same. The color separation element includes a spacer layer; and a color separation lens array, which includes at least one nano-post arranged in the spacer layer and is configured to form a phase distribution for splitting and focusing incident light according to wavelengths, wherein periodic regions in which color separation lens arrays are repeatedly arranged are provided, and the color separation lens array is configured to interrupt phase distribution at the boundary of the periodic regions.

Abstract: Photoelectric conversion apparatus includes semiconductor layer in which first photoelectric converters are arranged in light-receiving region and second photoelectric converters are arranged in light-shielded region, light-shielding wall arranged above the semiconductor layer and defining apertures respectively corresponding to the first photoelectric converters, and light-shielding film arranged above the semiconductor layer. The light-shielding film includes first portion extending along principal surface of the semiconductor layer to cover the second photoelectric converters. The first portion has lower surface and upper surface. The light-shielding wall includes second portion whose distance from the semiconductor layer is larger than distance between the upper surface and the principal surface. Thickness of the first portion in direction perpendicular to the principal surface is larger than thickness of the second portion in direction parallel to the principal surface.

Abstract: An image sensing device includes a pixel array including a plurality of unit pixels consecutively arranged and structured to generate an electrical signal in response to incident light by performing photoelectric conversion of the incident light. The unit pixels are isolated from each other by first device isolation structures. Each of the unit pixels includes a photoelectric conversion element structured to generate photocharges by performing photoelectric conversion of the incident light, a floating diffusion region structured to receive the photocharges, a transfer transistor structured to transfer the photocharges generated by the photoelectric conversion element to the floating diffusion region, and a well tap region structured to apply a bias voltage to a well region. The well tap region is disposed at a center portion of a corresponding unit pixel.

Abstract: A photoelectric converting device including: a semiconductor layer with a front surface and a back surface, the semiconductor layer including a photoelectric conversion portion; a wire structure including an insulating film, the wire structure being disposed on the front surface of the semiconductor layer; a first insulator portion disposed in a trench provided in the semiconductor layer; and a second insulator portion disposed between the first insulator portion and the insulating film, wherein the first insulator portion has a maximum width larger than a maximum width of the second insulator portion.

Abstract: An electronic device includes a substrate semiconductor wafer with semiconductor portions separated from one another by through-passages. Electronic circuits and a dielectric layer with a network of electrical connections are formed at a front face of the substrate semiconductor wafer. Electrically conductive fillings are contained within the through-passages and are connected to the network of electrical connections. Interior dielectric layers for anti-diffusion protection are provided in the through-passages between the electrically conductive fillings and the semiconductor portions. Back side dielectric layers are joined to the interior dielectric layers.

Abstract: A first circuit layer including a first semiconductor substrate with photoelectric conversion unit that photoelectrically converts incident light and generates charge, and a first wiring layer with wiring that reads out signal based upon charge generated by the photoelectric conversion unit; second circuit layer including a second wiring layer with wiring connected to the wiring of the first wiring layer, and a second semiconductor substrate with a through electrode connected to the wiring of the second wiring layer; third circuit layer including a third semiconductor substrate with a through electrode connected to the through electrode of the second circuit layer, and third wiring layer with wiring connected to the through electrode of the third semiconductor substrate; and a fourth circuit layer including a fourth wiring layer with wiring connected to the wiring of the third wiring layer, and fourth semiconductor substrate connected to the wiring of the fourth wiring layer.

Abstract: A light-emitting device includes: a first light-emitting element portion including: an n-side nitride semiconductor layer, a first light-emitting layer over the n-side nitride semiconductor layer, and a first p-side nitride semiconductor layer over the first light-emitting layer; a second light-emitting element portion including: a second light-emitting layer over the n-side nitride semiconductor layer, and a second p-side nitride semiconductor layer over the second light-emitting layer; an n-side electrode connected to the n-side nitride semiconductor layer; a first p-side electrode disposed over the first p-side nitride semiconductor layer via an upper n-type semiconductor layer; and a second p-side electrode connected to the second p-side nitride semiconductor layer. The first p-side nitride semiconductor layer and the upper n-type semiconductor layer form a tunnel junction.

Abstract: In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.

Abstract: A display device includes a first pixel and a second pixel; a light emitting layer; a color conversion layer on the light emitting layer; and a color filter layer on the color conversion layer, the light emitting layer including one or more light emitting elements in the first pixel and the second pixel, the color conversion layer including a first color conversion layer in the first pixel and a second color conversion layer in the second pixel. The color filter layer includes a first color filter layer in the first pixel and a second color filter layer in the second pixel, the light emitting elements capable of emitting a first light having a first wavelength, each of the first color conversion layer and the second color conversion layer including first color conversion particles and second color conversion particles.

Abstract: An embodiment relates to a method and manufacture of robust, high-performance devices. The method comprises preparing a unit cell of a Silicon Carbide (SiC) substrate comprising a first conductivity type substrate and a first conductivity type drift layer; forming a second conductivity type well region; forming a first conductivity type source region within the second conductivity type well region; and forming a second conductivity type shield region surrounding the first conductivity type source region. The second conductivity type shield region formed comprises a portion of the second conductivity type shield region located on a SiC surface.

Abstract: A semiconductor device includes a layer stack with first semiconductor layers and second semiconductor layers of opposite doping types arranged alternatingly. A first semiconductor region of a first semiconductor device adjoins the first semiconductor layers, and has a first end arranged in a first region of the first semiconductor device and extends from the first end into a second region of the first semiconductor device. Second semiconductor regions of the first semiconductor device adjoin at least one of the second semiconductor layers. A third semiconductor region of the first semiconductor device adjoins the first semiconductor layers. The first semiconductor region extends from the first region into the second region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions.

Abstract: A semiconductor device includes a layer stack with first and second semiconductor layers of complementary doping types are arranged alternatingly between first and second surfaces of the layer stack. A first semiconductor region adjoins the first semiconductor layers and has a first end arranged in a first device region and extends from the first end into a second device region. Second semiconductor regions adjoin at least one of the second semiconductor layers. A third semiconductor region adjoins the first semiconductor layers. The first semiconductor region extends from the first device region into the second device region and is spaced apart from the third semiconductor region. The second semiconductor regions are arranged between, and spaced apart from, the third and first semiconductor regions.

Abstract: A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin.

Abstract: A semiconductor device including an active region protruding from an upper surface of a substrate and extending in a first horizontal direction, at least two gate electrodes extending in a second horizontal direction and crossing the active region, the second horizontal direction crossing the first horizontal direction, a source/drain region in the active region between the gate electrodes may be provided. The source/drain region includes a recess region, an outer doped layer on an inner wall of the recess region, an intermediate doped layer on the outer doped layer, and an inner doped layer on the intermediate doped layer and filling the recess region. One of the outer doped layer or the intermediate doped layer includes antimony, and the inner doped layer includes phosphorous.

Abstract: Devices and methods for switch body connections to achieve soft breakdown. In some embodiments, a field-effect transistor (FET) can include an assembly of source, gate, and drain implemented on an active region, a first body contact implemented at a first end of the assembly, and a second body contact implemented at a second end of the assembly. The second end can be distal from the first end along a width of the field-effect transistor.

Abstract: An power semiconductor device having a barrier region is provided. A power unit cell of the power semiconductor device has at least two trenches that may both extend into the barrier region. The at least two trenches may both have a respective trench electrode coupled to a control terminal of the power semiconductor device. For example, the trench electrodes are structured to reduce the total gate charge of the power semiconductor device. The barrier region may be p-doped and vertically confined, i.e., in and against the extension direction, by the drift region. The barrier region can be electrically floating.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack and a plurality of linear arrays of gates above the quantum well stack to control quantum dot formation in the quantum well stack. An insulating material may be between a first linear array of gates and a second linear array of gates, the insulating material may be between individual gates in the first linear array of gates, and gate metal of the first linear array of gates may extend over the insulating material.

Abstract: A semiconductor film, a sheet like object, and a semiconductor device are provided that have inhibited semiconductor properties, particularly leakage current, and excellent withstand voltage and heat dissipation. A crystalline semiconductor film or a sheet like object includes a corundum structured oxide semiconductor as a major component, wherein the film has a film thickness of 1 ?m or more. Particularly, the semiconductor film or the object includes a semiconductor component of oxide of one or more selected from gallium, indium, and aluminum as a major component. A semiconductor device has a semiconductor structure including the semiconductor film or the object.

Abstract: A method of producing a semiconductor device includes: forming, in a semiconductor substrate, a drift region of a first conductivity type, a body region of a second conductivity type above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; forming rows of spicular-shaped field plate structures in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; forming stripe-shaped gate structures in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and forming a current spread region of the first conductivity type below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures, the current spread region configured to increase channel current distribution in the semiconductor mesas.

Abstract: A method includes: forming a trench in a first major surface of a semiconductor substrate, the trench having a base and a side wall extending from the base to the first major surface; forming a first insulating layer on the trench base and side wall; forming a sacrificial layer on the first insulating layer on the trench side wall; forming a second insulation layer on the sacrificial layer; inserting conductive material into the trench that at least partially covers the second insulation layer; selectively removing portions of the second insulation layer uncovered by the conductive material; selectively removing the sacrificial layer to form a recess that is positioned adjacent the conductive material in the trench and that is bounded by the first insulation layer and the second insulating layer; and forming a third insulating layer in the trench that caps the recess to form an enclosed cavity in the trench.

Abstract: A thin film transistor including a gate electrode, a semiconductor layer, and source and drain electrodes contacting the semiconductor layer. The source and drain electrodes include a metal oxide having a crystal size in a c-axis direction Lc(002) that ranges from 67 ? or more to 144 ? or less.

Abstract: A semiconductor device including a lower contact pattern including a first metal, an upper contact pattern including a second metal, a first resistivity of first metal being greater than a second resistivity of the second metal, and a metal barrier layer between the lower contact pattern and a lower portion of the upper contact pattern, the metal barrier layer including a third metal, the third metal being different from the first and second metals may be provided. A lower width of the upper contact pattern may be less than an upper width of the lower contact pattern.

Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.

Abstract: A semiconductor device includes a semiconductor layer structure, a gate insulating pattern on the semiconductor layer structure, a gate electrode on the gate insulating pattern, and an interface layer between the gate insulating pattern and the semiconductor layer structure, the interface layer having a first segment and a second segment with a gap therebetween.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a first metal gate structure in a first dielectric layer. The method includes forming a second metal gate structure in the first dielectric layer, and the second metal gate structure includes a second metal electrode over a second gate dielectric layer. The method also includes forming a mask structure covering the first metal gate structure. The method includes etching a portion of the second gate dielectric layer and a portion of the second metal electrode of the second metal gate structure to form a first conductive portion extending above a top surface of the second gate dielectric layer. The method includes forming a metal layer over the first conductive portion, and the metal layer has a recess, and a top portion of the first conductive portion extends into the recess.

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.