Abstract: A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of 18O greater than 10 percent.

Abstract: A method of fabricating a semiconductor structure includes forming a GaN-based semiconductor layer on a substrate, forming a silicon-containing insulating layer on the GaN-based semiconductor layer, forming a recess in the silicon-containing insulating layer in a first etching step, wherein the first etching step is performed by using a fluorine-containing etchant and applying a first bias power, and enlarging the recess to extend into the GaN-based semiconductor layer in a second etching step, wherein the second etching step is performed by using the same fluorine-containing etchant as the first etching step and applying a second bias power that is greater than the first bias power. In addition, a method of fabricating a high electron mobility transistor is provided.

Abstract: A semiconductor device according to the present disclosure includes a channel member including a first connection portion, a second connection portion and a channel portion disposed between the first connection portion and the second connection portion, a first inner spacer feature disposed over and in contact with the first connection portion, a second inner spacer feature disposed under and in contact with the first connection portion, and a gate structure wrapping around the channel portion of the channel member. The channel member further includes a first ridge on a top surface of the channel member and disposed at an interface between the channel portion and the first connection portion. The first ridge partially extends between the first inner spacer feature and the gate structure.

Abstract: Fabricating a nanosheet transistor includes receiving a substrate structure having a set of nanosheet layers stacked upon a substrate, the set of nanosheet layers including at least one silicon (Si) layer, at least one silicon-germanium (SiGe) layer, a fin formed in the nanosheet layers, a gate region formed within the fin, and a trench region adjacent to the fin. A top sacrificial spacer is formed upon the fin and the trench region and etched to form a trench in the trench region. An indentation is formed within the SiGe layer in the trench region, and a sacrificial inner spacer is formed within the indentation. A source/drain (S/D) region is formed within the trench. The sacrificial top spacer and sacrificial inner spacer are etched to form an inner spacer cavity between the S/D region and the SiGe layer. An inner spacer is formed within the inner spacer cavity.

Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a fin structure over a semiconductor substrate. The semiconductor device structure also includes a gate stack covering a portion of the fin structure, and the gate stack includes a work function layer and a metal filling over the work function layer. The semiconductor device structure further includes an isolation element over the semiconductor substrate and adjacent to the gate stack. The isolation element is in direct contact with the work function layer and the metal filling.

Abstract: Disclosed are a memory device including a vertical stack structure and a method of manufacturing the memory device. The memory device includes an insulating structure having a shape including a first surface and a protrusion portion protruding in a first direction from the first surface, a recording material layer covering the protrusion portion along a protruding shape of the protrusion portion and extending to the first surface on the insulating structure a channel layer on the recording material layer along a surface of the recording material layer, a gate insulating layer on the channel layer, and a gate electrode formed at a location on the gate insulating layer to face a second surface which is a protruding upper surface of the protrusion portion, wherein a void exists between the gate electrode and the insulating structure, defined by the insulating structure and the recording material layer.

Abstract: A vertical bipolar junction transistor may include an intrinsic base epitaxially grown on a first emitter or collector, the intrinsic base being compositionally graded, a second collector or emitter formed on the intrinsic base, and an extrinsic base formed all-around the intrinsic base. The extrinsic base may be isolated from the first emitter or collector by a first spacer. The extrinsic base may be isolated from the second collector or emitter by a second spacer. The extrinsic base may have a larger bandgap than the intrinsic base. The intrinsic base may be doped with a p-type dopant, and the first emitter or collector, and the second collector or emitter may be doped with an n-type dopant. The first emitter or collector, the intrinsic base, and the second collector or emitter may be made of a III-V semiconductor material.

Abstract: According to one embodiment, a semiconductor device includes first, and second conductive members, a first electrode including first and second electrode regions, a second electrode electrically connected to a first semiconductor film portion, a first semiconductor region including first to fourth partial regions, a second semiconductor region including the first semiconductor film portion, a third semiconductor region including a first semiconductor layer portion, a fourth semiconductor region provided between the first electrode and the first semiconductor region, and a first insulating member including insulating portions. The first partial region is between the first electrode region and the first conductive member. The second partial region is between the second electrode region and the second conductive member. The third partial region is between the first and second partial regions and between the first electrode and the fourth partial region.

Abstract: [Overview] [Problem to be Solved] To provide a switching transistor and a semiconductor module having lower distortion generated in a signal. [Solution] A switching transistor including: a channel layer including a compound semiconductor and having sheet electron density equal to or higher than 1.7×1013 cm?2; a barrier layer formed on the channel layer by using a compound semiconductor that is of a different type from the channel layer; a gate electrode provided on the barrier layer; and a source electrode and a drain electrode provided on the barrier layer with the gate electrode interposed between the source electrode and the drain electrode.

Abstract: A high electron mobility transistor (HEMT) includes a substrate; a source on the substrate; a drain on the substrate spaced from the source; and a gate between the source and the drain, wherein the gate has a stem contacting the substrate, the stem having a source side surface and a drain side surface, wherein a source side angle is defined between the source side surface and an upper planar surface of the substrate and a drain side angle is defined between the drain side surface and the upper planar surface of the substrate, and wherein the source side angle and the drain side angle are asymmetric. Methods for making the HEMT are also disclosed.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: In an SiC-MOSFET with a built-in Schottky diode, a bipolar current may be passed in a second well region formed at a terminal part to reduce the breakdown voltage of the terminal part. In the SiC-MOSFET with the built-in Schottky diode, a source electrode forming non-ohmic connection such as Schottky connection with the second well region is provided on the second well region formed below a gate pad in the terminal part. By the absence of ohmic connection between the second well region and the source electrode, reduction in breakdown voltage is suppressed at the terminal part.

Abstract: A high voltage transistor structure including a substrate, a first drift region, a second drift region, a first cap layer, a second cap layer, a gate structure, a first source and drain region, and a second source and drain region is provided. The first and second drift regions are disposed in the substrate. The first and second cap layers are respectively disposed on the first and second drift regions. The gate structure is disposed on the substrate and located over at least a portion of the first drift region and at least a portion of the second drift region. The first and second source and drain regions are respectively disposed in the first and second drift regions and located on two sides of the gate structure. The size of the first drift region and the size of the second drift region are asymmetric.

Abstract: A semiconductor device is provided. The semiconductor device includes a base substrate; a first well region and a second well region in the base substrate; a gate electrode structure, sidewall spacers, a doped source layer and a doped drain layer over the base substrate; a dielectric layer on the base substrate; and an isolation layer in the dielectric layer. The dielectric layer covers sidewalls of the sidewall spacers, the doped source layer and the doped drain layer, and exposes a top surface of the gate electrode structure. The isolation layer is in the gate electrode structure of the second well region and the base substrate of the second well region, and adjacent to the sidewalls of the sidewall spacer over the second well region.

Abstract: A high voltage semiconductor device includes a semiconductor substrate, an isolation structure, a gate oxide layer, and a gate structure. The semiconductor substrate includes a channel region, and at least a part of the isolation structure is disposed in the semiconductor substrate and surrounds the channel region. The gate oxide layer is disposed on the semiconductor substrate, and the gate oxide layer includes a first portion and a second portion. The second portion is disposed at two opposite sides of the first portion in a horizontal direction, and a thickness of the first portion is greater than a thickness of the second portion. The gate structure is disposed on the gate oxide layer and the isolation structure.

Abstract: A SiO2 layer is disposed in the bottom portion of a Si pillar and on an i-layer substrate. A gate HfO2 layer 11b is disposed so as to surround the side surface of the Si pillar, and a gate TiN layer is disposed so as to surround the HfO2 layer. P+ layers are disposed that contain an acceptor impurity at a high concentration, serve as a source and a drain, and are simultaneously or separately formed by a selective epitaxial crystal growth method on the exposed side surface of the bottom portion of and on the top portion of the Si pillar. Thus, an SGT is formed on the i-layer substrate.

Abstract: The disclosure discloses a structure of high-voltage (HV) transistor which includes a substrate. An epitaxial doped structure with a first conductive type is formed in the substrate, wherein a top portion of the epitaxial doped structure includes a top undoped epitaxial layer. A gate structure is disposed on the substrate and at least overlapping with the top undoped epitaxial layer. A source/drain (S/D) region with a second conductive type is formed in the epitaxial doped structure at a side of the gate structure. The first conductive type is different from the second conductive type.

Abstract: A semiconductor structure includes a source/drain (S/D) feature disposed in a semiconductor layer, a metal gate stack (MG) disposed in a first interlayer dielectric (ILD) layer and adjacent to the S/D feature, a second ILD layer disposed over the MG, and an S/D contact disposed over the S/D feature. The semiconductor structure further includes an air gap disposed between a sidewall of a bottom portion of the S/D contact and the first ILD layer, where a sidewall of a top portion of the S/D contact is in direct contact with the second ILD layer.

Abstract: A semiconductor nanostructure and an epitaxial semiconductor material portion are formed on a front surface of a substrate, and a planarization dielectric layer is formed thereabove. Recess cavities are formed to expose a first active region and the epitaxial semiconductor material portion. A metallic cap structure is formed on the first active region, and a sacrificial metallic material portion is formed on the epitaxial semiconductor material portion. A connector via cavity is formed by anisotropically etching the sacrificial metallic material portion and an underlying portion of the epitaxial semiconductor material portion while the metallic cap structure is masked with a hard mask layer. A connector via structure is formed in the connector via cavity. Front-side metal interconnect structures are formed on the connector via structure and the metallic cap structure, and a backside via structure is formed through the substrate on the connector via structure.

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

Abstract: According to one embodiment, a semiconductor layer includes a base, a scanning line disposed over the base, a signal line disposed over the base, a transistor overlapping the scanning line and the signal line and including a first oxide semiconductor layer connected to the signal line, and second oxide semiconductor layers disposed in a same layer as the first oxide semiconductor layer. The second oxide semiconductor layers are disposed around the transistor, and the second oxide semiconductor layers are floating.

Abstract: The transistor includes a first gate electrode, a first insulating film over the first gate electrode, an oxide semiconductor film over the first insulating film, a source electrode over the oxide semiconductor film, a drain electrode over the oxide semiconductor film, a second insulating film over the oxide semiconductor film, the source electrode, and the drain electrode, and a second gate electrode over the second insulating film. The first insulating film includes a first opening. A connection electrode electrically connected to the first gate electrode through the first opening is formed over the first insulating film. The second insulating film includes a second opening that reaches the connection electrode. The second gate electrode includes an oxide conductive film and a metal film over the oxide conductive film. The connection electrode and the second gate electrode are electrically connected to each other through the metal film.

Abstract: A thin-film transistor comprises an annealed layer comprising crystalline zinc oxide. A passivation layer is adjacent to the thin-film transistor. The passivation layer has a thickness and material composition such that when a dose of radiation from a radiation source irradiates the thin-film transistor, a portion of the dose that includes an approximate maximum concentration of the dose is located within the annealed layer. The annealed layer has a thickness and threshold displacement energies after it has been annealed such that: a) a difference between a transfer characteristic value of the thin-film transistor before and after the dose is less than a first threshold; and b) a difference between a transistor output characteristic value of the thin-film before and after the dose is less than a second threshold. The thresholds are based on a desired performance of the thin-film transistor.

Abstract: A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first thickness and a second section with a second thickness greater than the first thickness. The second section is between the first section and at least one of the source or drain. The first nanowire includes a channel when a voltage is applied to the gate electrode.

Abstract: In some implementations, one or more semiconductor processing tools may deposit a first dielectric layer on a substrate of a semiconductor device. The one or more semiconductor processing tools may deposit a floating gate on the first dielectric layer. The one or more semiconductor processing tools may deposit a second dielectric layer on the floating gate and on the substrate of the semiconductor device. The one or more semiconductor processing tools may deposit a first control gate on a first portion of the second dielectric layer. The one or more semiconductor processing tools may deposit a second control gate on a second portion of the second dielectric layer, wherein a third portion of the second dielectric layer is between the first control gate and the floating gate and between the second control gate and the floating gate.

Abstract: A method for fabricating a solar cell and the and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, are described. The method can include: providing a solar cell having metal foil having first regions that are electrically connected to semiconductor regions on a substrate at a plurality of conductive contact structures, and second regions; locating a carrier sheet over the second regions; bonding the carrier sheet to the second regions; and removing the carrier sheet from the substrate to selectively remove the second regions of the metal foil.

Abstract: A thin-film coating applicator assembly is disclosed for coating substrates in outdoor applications. The innovative thin-film coating applicator assembly is adapted to apply performance enhancement coatings on installed photovoltaic panels and glass windows in outdoor environments. The coating applicator is adapted to move along a solar panel or glass pane while applicator mechanisms deposit a uniform layer of liquid coating solution to the substrate's surface. The applicator assembly comprises a conveyance means disposed on a frame. Further disclosed are innovative applicator heads that comprise a deformable sponge-like core surrounded by a microporous layer. The structure, when in contact with a substrate surface, deposits a uniform layer of coating solution over a large surface.

Abstract: Electroplating of aluminum may be utilized to form electrodes for solar cells. In contrast to expensive silver electrodes, aluminum allows for reduced cell cost and addresses the problem of material scarcity. In contrast to copper electrodes which typically require barrier layers, aluminum allows for simplified cell structures and fabrication steps. In the solar cells, point contacts may be utilized in the backside electrodes for increased efficiency. Solar cells formed in accordance with the present disclosure enable large-scale and cost-effective deployment of solar photovoltaic systems.

Abstract: The present embodiment provide a method for evaluating anion permeability of a graphene-containing membrane and also to provide a photoelectric conversion device employing a graphene-containing membrane having controlled anion permeability.

Abstract: An electromagnetic wave detector includes a light-receiving element, an insulating film, a two-dimensional material layer, a first electrode part, and a second electrode part. The light-receiving element includes a first semiconductor portion of a first conductivity type and a second semiconductor portion. The second semiconductor portion is joined to the first semiconductor portion. The second semiconductor portion is of a second conductivity type. The insulating film is disposed on the light-receiving element. The insulating film has an opening portion. The two-dimensional material layer is electrically connected to the first semiconductor portion in the opening portion. The two-dimensional material layer extends from on the opening portion onto the insulating film. The first electrode part is disposed on the insulating film. The first electrode part is electrically connected to the two-dimensional material layer. The second electrode part is electrically connected to the second semiconductor portion.

Abstract: The present invention generally relates to artificial photosystems and methods of their use, for example in artificial photosynthesis, wherein the artificial photosystems comprise one or more light-harvesting antenna (LHA) comprising a conjugated polyelectrolyte (CPE) complex (CPEC) comprising a donor CPE and an acceptor CPE, wherein the donor CPE and acceptor CPE are an electronic energy transfer (EET) donor/acceptor pair.

Abstract: A solar cell device having a solid state light absorber region that incorporates a donor-acceptor particle structure. The particle structure includes acceptor particles that generate a flow of electrons in the solid state light absorber region in response to absorbed photons; and donor particles comprising a phosphorescent material, wherein each donor particle is coupled to a group of acceptor particles, and wherein the phosphorescent material absorbs high energy photons and emits lower energy photons that are absorbed by the acceptor particles.

Abstract: A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a substrate having a light-receiving surface and a back surface. The solar cell can include a first semiconductor region of a first conductivity type disposed on a first dielectric layer, wherein the first dielectric layer is disposed on the substrate. The solar cell can also include a second semiconductor region of a second, different, conductivity type disposed on a second dielectric layer, where a portion of the second thin dielectric layer is disposed between the first and second semiconductor regions. The solar cell can include a third dielectric layer disposed on the second semiconductor region. The solar cell can include a first conductive contact disposed over the first semiconductor region but not the third dielectric layer.

Abstract: In a described example, an apparatus includes: a photon detector array with a first signal output pad coupled to a photon detector array pixel; a die carrier comprising a readout integrated circuit (ROIC) die and a conductor layer having conductors that couple a first signal input pad on the conductor layer to an input signal lead of the ROIC die; and the first signal output pad coupled to the first signal input pad.

Abstract: There are provided methods of growing arrays of light emitters on substrates. An example method includes adjusting a growth parameter of a given light emitter of an array of light emitters on a substrate to obtain an adjusted growth parameter. The adjusting may be based on a location of the given light emitter on the substrate. The adjusting may be to compensate for nonuniformity in a growth profile of the light emitters across the substrate. The nonuniformity may be associated with a corresponding nonuniformity among wavelengths of light generated by the light emitters. Adjusting the growth parameter may be to adjust the corresponding nonuniformity. The method may also include growing the given light emitter on the substrate based on the adjusted growth parameter. Arrays of corresponding light emitters are also described.

Abstract: An embodiment discloses an ultraviolet light emitting element including: a light emitting structure including a first conductive semiconductor layer, a second conductive semiconductor layer, an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, and an etched region in which the first conductive semiconductor layer is exposed; a first insulating layer disposed on the light emitting structure and including a first hole which exposes a portion of the etched region; a first electrode electrically connected to the first conductive semiconductor layer; and a second electrode electrically connected to the second conductive semiconductor layer, wherein the light emitting structure includes an intermediate layer regrown on the first conductive semiconductor layer exposed in the first hole, the first electrode is disposed on the intermediate layer, the etched region includes a first etched region disposed at an inner side and a second etched region disp

Abstract: A light-emitting diode (LED) includes a first semiconductor layer, an active layer, and a second semiconductor layer that are sequentially stacked, and includes a first electrode pad, a second electrode pad and a third electrode pad disposed on the second semiconductor layer in a direction from a corner of the second semiconductor layer to an opposite corner of the second semiconductor layer. An LED includes a first electrode pad disposed at a center of the LED and in contact with a P-type semiconductor layer and a second electrode pad in contact with an N-type semiconductor layer, wherein the second electrode pad is disposed a maximum distance away from the first electrode pad on the same surface.

Abstract: A light emitting diode (LED) including a first contact. The LED further includes a first semiconductor layer over the first contact. The first semiconductor layer comprises hexagonal Boron Nitride. Additionally, the LED includes a second semiconductor layer over the first semiconductor layer. The second semiconductor layer comprises at least one hexagonal Boron Nitride quantum well and at least one hexagonal Boron Nitride quantum barrier. Moreover, the LED includes a third semiconductor layer over the second semiconductor layer. The third semiconductor layer comprises hexagonal Boron Nitride. Further, the LED includes a second contact over the third semiconductor layer.

Abstract: Embodiments of the present invention relate to a display device in which, in a structure in which an oxide semiconductor thin film transistor is disposed on an upper layer of a low temperature polycrystalline silicon thin film transistor, the hydrogen adsorption layer is disposed on the capacitor electrode located on the driving transistor among low temperature polycrystalline silicon thin film transistors, so that it is possible to prevent the reduction of an S factor due to the re-hydrogenation of the driving transistor in the heat treatment process of the oxide semiconductor thin film transistor.

Abstract: Disclosed is a semiconductor device package comprising: first insulation layers disposed between first wiring lines and second wiring lines; a plurality of first pads electrically connected to the first wiring lines, respectively; and a plurality of second pads electrically connected to the second wiring lines, respectively, wherein the line having the longest length extended in a first direction, among the plurality of first wiring lines, has an area of a region, which is overlapped with an electrically connected semiconductor structure, that is larger than that of the line having the shortest extended length.

Abstract: A semiconductor light-emitting device includes a junction or active layer between doped semiconductor layers coextensive over a contiguous device area, corresponding sets of electrical contacts connected to the semiconductor layers, and multiple nanostructured optical elements at a surface of one semiconductor layer opposite the other semiconductor layer. Composite electrical contacts of one set include a conductive layer, a transparent dielectric layer between the conductive and semiconductor layers, and vias through the dielectric layer connecting the conductive and semiconductor layers. The nanostructured elements redirect light, propagating laterally in optical modes supported by the semiconductor layers, to exit the device. The composite electrical contacts can be independent and define independently addressable pixel areas of the device. The nanostructured elements and thin semiconductor layers can yield high contrast between adjacent pixel areas without trenches between them.

Abstract: A lithium foil laminating apparatus for an anode material of a lithium metal battery comprises a pair of lithium foil unwinders; a pair of tension guide rolls; a pair of horizontal guide rolls; a pair of first release film winders; a copper foil unwinder; a copper foil tension regulator; a pair of lithium foil cutters; a pair of guide plates; a pair of guide rolls; a pair of press rolls; a first release film unwinder; and an anode material winder.

Abstract: An apparatus for forming an electrode film mixture can have a first source including a polymer dispersion comprising a liquid and a polymer, a second source including a second component of the electrode film mixture, and a fluidized bed coating apparatus including a first inlet configured to receive from the first source the dispersion, and a second inlet configured to receive from the second source the second component.

Abstract: A positive active material for a rechargeable lithium battery includes a first positive active material including a secondary particle including at least two agglomerated primary particles, where at least one part of the primary particles has a radial arrangement structure, as well as a second positive active material having a monolith structure. The first and second positive active materials may both include nickel-based positive active materials. A method of preparing the positive active material, and a rechargeable lithium battery including a positive electrode including the positive active material are also provided.

Abstract: A method of manufacturing lithium-metal nitride including suspending a lithium-metal-oxide-powder (LMOP) within a gaseous mixture, incrementally heating the suspended LMOP to a holding temperature of between 400 and 800 degrees Celsius such that the LMOP reaches the holding temperature, and maintaining the LMOP at the holding temperature for a time period in order for the gaseous mixture and the LMOP to react to form a lithium-metal nitride powder (LMNP).

Abstract: Provided is a composite anode active material including: a carbonaceous material; a metal alloyable with lithium, located on a surface of the carbonaceous material; and a silicon coating layer located on a surface of the carbonaceous material, on a surface of the metal alloyable with lithium, or a combination thereof.

Abstract: Materials and methods for coating an electrochemically active electrode material for use in a lithium-ion battery are provided. In one example, an electrochemically active electrode material comprises: a polymer coating applied directly to an exterior surface of the electrochemically active electrode material; a metal plating catalyst adhered to the continuous polymer; and a continuous metal coating that completely covers the metal catalyst and continuous polymer coating. The electrochemically active electrode material may comprise a powder comprising one or more secondary particles, and the polymer and metal coatings may be applied to exterior surfaces of these secondary particles.

Abstract: An anode active material, an anode including the anode active material; and a lithium secondary battery including the anode, the anode active material including a core including a carbonaceous material; and a polycyclic compound on a surface of the core, the polycyclic compound being represented by Formula 1:

Abstract: Processes for preparing a niobate material include the following steps: (i) providing a niobium-containing source; (ii) providing a transitional metal source (TMS), a post-transitional metal source (PTMS), or both; (iii) dissolving (a) the niobium-containing source, and (b) the TMS, the PTMS, or both in an aqueous medium to form an intermediate solution; (iv) forming an intermediate paste by admixing an inert support material with the intermediate solution; (v) optionally coating the intermediate paste on a support substrate; and (vi) removing the inert support material by subjecting the intermediate paste to a calcination process and providing a transition-metal-niobate (TMN) and/or a post-transition-metal-niobate (PTMN). Anodes including a TMN and/or PTMN are also provided.

Abstract: A nickel hydroxide includes stacked nickel hydroxide layers. Each of the nickel hydroxide layers includes Ni2+ and OH?. At least one of the nickel hydroxide layers further includes a type of polyatomic anions. The polyatomic anions include a type of anions that are not SO42? or CO32?.